User's Manual

GS2101M Architecture GS2101M Low Power WiFi Module Data Sheet
Architecture Description
26 Confidential GS2101M-DS-001270, Release 1.0
• Client and AP modes support
• Encryption support including: AES-CCMP, legacy WPA-TKIP, legacy WEP
ciphers and key management
• WiFi Protected Setup 2.0 (WPS2.0) including both PIN and push button options
• 802.11e based QoS (including WMM, WMM-PS)
• WiFi Direct with concurrent mode, including Device/Service Discovery, Group
Formation/Invitation, Client Power Save, WPS-PIN/Push Button
2.1.2.2 802.11 PHY
The 802.11 PHY implements all the standard required functionality and GainSpan specific
functionality for 802.11b/g/n protocols. It also implements the Radar detection
functionality to support 802.11h. The PHY implements the complete baseband Tx and Rx
pipeline. It interfaces with the MAC to perform transmit and receive operations. It
interfaces directly to the ADC and DAC. The PHY implements the Transmit power control,
receive Automatic Gain Control and other RF control signals to enable transmit and
receive. The PHY also computes the CCA for MAC use.
Key Features
• Compliant to 2.4GHz IEEE 802.11b/g/n (11n – 2009)
• Support 802.11g/n OFDM with BPSK, QPSK, 16-QAM and 64-QAM; 802.11b
with BPSK, QPSK and CCK
• Support for following data rates:
– 802.11n (20MHz): MCS0 - 7; 7.2, 14.4, 21.7, 28.9, 43.3, 57.8, 65.0, 72.2
Mbps
– 802.11g: 6, 9, 12, 18, 24, 36, 48, 54 Mbps
– 802.11b: 1, 2, 5.5, 11 Mbps
• Support Full (800ns) & Half (400ns) Guard Interval (GI) modes (SGI and LGI)
• Support Space time block coding (STBC) for receive direction
• Complete front-end radio integration including PA, LNA and RF Switch
• Support for external PA, LNA and control of external RF Switch (GS2101MIE
only)
2.1.2.3 RF/Analog
The RF/Analog is a single RF transceiver for IEEE 802.11b/g/n (WLAN). The RF Interface
block provides the access to the RF and analog control and status to the CPU. This block is
accessible only from the WLAN CPU. It implements registers to write static control words.
It provides read only register interface to read static status. It generates the dynamic control
signals required for TX and RX based on the PHY signals. The AGC look up table to map
the gain to RF gain control word is implemented in this block.