User's Manual

GS2101M Architecture GS2101M Low Power WiFi Module Data Sheet
Architecture Description
28 Confidential GS2101M-DS-001270, Release 1.0
A 64KB dual port memory is used for exchange of data between the two CPU domains.
Each CPU subsystem can read or write to this memory using an independent memory port.
SW must manage the memory access to avoid simultaneous write to the same memory
location. The dual port memory appears as a single bank to each CPU subsystem.
2.1.4.2 ROM
ROM is provided in each CPU subsystem to provide the boot code and other functional
code that are not expected to change regularly. Each CPU has 512KB of ROM.
2.1.4.3 OTP ROM
The GS2000 device includes a 64Kbit OTP ROM used for storing MAC ID and other
information such as security keys etc. The APP and WLAN subsystem each contain
32Kbits (4Kbytes) of OTP memory.
2.1.4.4 Flash Interface
The GS2000 SoC has only internal ROM and RAM for code storage. There is no embedded
Flash memory on the SoC. Any ROM patch code and new application code must reside in
the on-module Flash device of the GS2101M module. Flash access from the two CPUs are
independent. The APP CPU is considered the system Master and the code running on this
CPU is required to initialize the overall chip and common interfaces. WLAN CPU access
to the Flash is restricted to read DMA. Any write to the Flash from the WLAN CPU must
be done through the APP CPU. The operational parameters of the DMA accesses are set by
the APP CPU at system startup. The Flash code is transferred to internal RAM before
execution.
2.1.5 Clocks
The GS2101M includes four basic clock sources:
– Low power 32KHz clock (see 2.1.6 Real Time Clock (RTC) Overview, page 29)
– 40MHz Xtal Oscillator
– PLL to generate the internal 120MHz (CPU) and 80MHz (PHY) clocks from the
40MHz Xtal.
– High speed RC oscillator 80MHz
Intermediate modes of operation, in which high speed clocks are active but some modules
are inactive, are obtained by gating the clock signal to different subsystems. The clock
control blocks within the device are responsible for generation, selection and gating of the
clocked used in the module to reduce power consumption in various power states.