User's Manual

GS2101M Architecture GS2101M Low Power WiFi Module Data Sheet
Architecture Description
32 Confidential GS2101M-DS-001270, Release 1.0
interrupts to the CPU to indicate specific events such as FIFO full/empty, block complete,
no ack error, and arbitration failure.
2.1.7.5 GPIO
The GPIO block provides programmable inputs and outputs that can be controlled from the
CPU SW through an APB interface. Any number of inputs can be configured as an interrupt
source. The interrupts can be generated based on the level or the transition of a pin. At reset,
all GPIO lines defaults to inputs. Each pin can be configured as input or output from SW
control.
2.1.7.6 Sigma Delta ADC
The ADC and DAC are 16-bit sigma-delta converters. There are 3 ADC channels, each
having a differential pair for a total of six input pins. The sample rate can be 32KHz to
80KHz. The sigma delta converter ratio is 250. The ADC is a 3 channel converter. Each
channel can have an optional pre-amplifier stage. The gain can be set to 0db, 6db, 12db,
18db, or 24db. The delay between the second and third channels of the ADC can be
adjusted under SW control. The digital interface for the ADCs and the DAC are 2’s
complement. ADC channel 0 (only) can alternatively be used as a differential DAC.
2.1.7.7 PWM
The PWM consists of three identical PWM function blocks. The PWM function blocks can
be used in two modes of operations:
• Independent PWM function blocks providing output signal with programmable
frequency and duty cycle
• Synchronized PWM function blocks with programmable phase delay between
each PWM output
The PWM has the following features:
• 32-bit AMBA APB interface to access control, and status information
• Three identical PWM function blocks
• Each PWM block can be enabled independently
• All three PWM blocks can be started synchronously or chained with
programmable delay
• Programmable 6-bit prescaler for the input clock (see 2.1.5 Clocks, page 28)
• Programmable frequency and duty cycle using 16-bit resolution in terms of clock
cycles for ON and OFF interval time
• Combined interrupt line with independent masking of interrupts