User's Manual

GS2101M Low Power WiFi Module Data Sheet GS2101M Architecture
Architecture Description
GS2101M-DS-001270, Release 1.0 Confidential 33
2.1.8 System States
The system states of the GS2101Mxx system are as follows:
Power OFF: No power source connected to the system.
Standby: In the standby state, the GS2101M is in its lowest power state. In this state
power is on to the VRTC and VIN_3V3 input. The RTC portion of the GS2000 chip is
powered from the VRTC pin.
In standby state, the 32.768KHz oscillator is running and RTC RAM retains the state
(how many banks retain their state is SW configurable). SRAM, CPUs and I/Os are
powered off using the internal switches within the device thus reducing overall power
consumption.
Exit from standby occurs when a pre-specified wakeup time occurs, or when the
RTC_IO configured as alarm inputs sees the programmed polarity of signal edge.
System Configuration: When a power-up is requested, the system transitions from the
Standby state to the System Configuration state. In this state, the APP CPU is released
from reset by the RTC. The WLAN CPU remains in the reset state during System
Configuration. The APP CPU then executes the required system configurations,
releases the WLAN CPU from reset, and transitions to the Power-ON state.
The System Configuration state is also entered on transition from the Power-ON state
to the Standby state, to complete necessary preparations before shutting off the power
to the core system.
Power-ON: This is the active state where all system components can be running. The
Power-ON state has various sub-states, in which unused parts of the system can be in
sleep mode, reducing power consumption. Sleep states are implemented by gating the
clock signal off for a specific system component. Additionally, unneeded clock sources
can be turned off. For example, receiving data over a slave SPI interface could be done
with only the 80MHz RC oscillator active, and the 40MHz crystal and PLL turned off.
Sleep: In the Sleep state, the 40MHz crystal and the 80MHz RC oscillator remains
running, but it is gated off to one or both CPUs. Each CPU can independently control
its own entry into Sleep state. Any enabled interrupt will cause the interrupted CPU to
exit from Sleep state, and this will occur within a few clock cycles.
Deep Sleep: Deep sleep is entered only when both CPUs agree that the wakeup latency
is OK. In Deep Sleep mode, the 40MHz crystal oscillator and 80MHz RC oscillator are
turned off to save power, but all power supplies remain turned on. Thus all registers,
memory, and I/O pins retain their state. Any enabled interrupt will cause an exit from
Deep Sleep state.
EXT_RTC_RESET_n pin: This is an input pin for resetting the entire module,
including the RTC section of the device. This pin should not be left floating. An
external 10K pull up resistor to VRTC is recommended.
NOTE: During first battery plug, i.e., when power is applied the first time to the
RTC power rail (VRTC), the power detection circuit in the RTC also causes a
wakeup request.