User’s Guide Publication number 16500-97022 August 1997 For Safety information, Warranties, and Regulatory information, see the pages behind the Index © Copyright Hewlett-Packard Company 1987, 1990, 1993, 1994, 1996, 1997 All Rights Reserved HP 16500C /16501A Logic Analysis System
HP 16500C—At a Glance A system of measurement modules The HP 16500C is the mainframe of the Hewlett-Packard Logic Analysis System. It offers a modular structure for plug-in cards with a wide range of state, timing, oscilloscope, and pattern generator capabilities. A powerful, easy-to-use interface The touchscreen interface offers pop-up menus and color graphics to lead you through measurement configurations without having to remember lots of steps.
HP 16500C HP 16501A iii
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In This Book This User’s Guide shows you how to use the HP 16500C Logic Analysis System in your everyday debugging work. Chapter 1, “Triggering,” shows you how to set up the analyzer to trigger on the various kinds of events present in your system. Advanced triggering capability allows you to look at only the program states of interest when you are solving a particular problem.
about specific application problems and how to solve them using an HP logic analyzer. See Also For general information on setup and operation of the HP 16500C, see the HP 16500C /16501A Logic Analysis System User’s Reference. For information on programming the HP 16500C using a computer controller such as a workstation or personal computer, see the HP 16500C/16501A Logic Analysis System Programmer’s Guide. The Programmer’s Guide is available from your HP Sales Office.
Contents 1 Triggering To store and time the execution of a subroutine 1–3 To trigger on the nth iteration of a loop 1–5 To trigger on the nth recursive call of a recursive function 1–6 To trigger on entry to a function 1–8 To capture a write of known bad data to a particular variable 1–10 To trigger on a loop that occasionally runs too long 1–11 To verify that all stacks and registers are restored correctly before exiting a subroutine 1–12 To trigger after all status bus lines finish transitioning 1–13 To
Contents To capture state flow showing how your target system processes an interrupt 2–16 To test a circuit using stimulus-response 2–17 To use a state analyzer to trigger timing analysis of a count-down on a set of data lines 2–18 To monitor the activity of two coprocessors in a target system 2–19 Special displays 2–21 To interleave trace lists 2–22 To view trace lists and waveforms together on the same display 2–24 Skew Adjustment 2–26 To adjust for minimum skew between two modules involved in an inter
Contents 4 Concepts The Trigger Sequencer 4–3 The Inverse Assembler 4–10 Configuration Translation for Analyzer Modules 4–13 5 If You Have a Problem Analyzer Problems 5–3 Intermittent data errors 5–3 Unwanted triggers 5–3 No Setup/Hold field on format screen 5–4 No activity on activity indicators 5–4 Capacitive loading 5–4 No trace list display 5–5 Preprocessor Problems 5–6 Target system will not boot up 5–6 Slow clock 5–7 Erratic trace measurements 5–7 Inverse Assembler Problems 5–9 No inverse assembly
Contents Messages 5–12 “Default Calibration Factors Loaded” (HP 16540, 16541, and 16542) 5–12 “. . . Inverse Assembler Not Found” 5–12 “Measurement Initialization Error” 5–13 “No Configuration File Loaded” 5–14 “Selected File is Incompatible” 5–14 “Slow or Missing Clock” 5–14 “State Clock Violates Overdrive Specification” 5–15 “Time from Arm Greater Than 41.
1 Triggering
Triggering As you begin to understand a problem in your system, you may realize that certain conditions must occur before the problem occurs. You can use sequential triggering to ensure that those conditions have occurred before the analyzer recognizes its trigger and captures information. You set up sequential triggering as follows: • Select the Trigger menu for the module you are using. • In the Trigger menu, define terms and associated values to be used when searching through the sequence.
Triggering To store and time the execution of a subroutine To store and time the execution of a subroutine Most systems software of any kind is composed of a hierarchy of functions and procedures. During integration, testing, and performance evaluation, you will want to look at specific procedures to verify that they are executing correctly and that the implementation is efficient.
Triggering To store and time the execution of a subroutine Example Suppose you want to trigger on entry to a routine called MY_SUB. You can define the address of MY_SUB in the Format menu, allowing you to reference the symbol name when setting up the trace specification. Assume that MY_SUB extends for 0A hex locations. You can set up the trigger sequencer as shown in the display.
Triggering To trigger on the nth iteration of a loop To trigger on the nth iteration of a loop Traditional debugging requires print statements around the area of interest. This is not possible in most embedded systems designs. But, the analyzer allows you to view the system’s behavior when a particular event occurs. Suppose that your system behaves incorrectly on the last iteration of a loop, which, in this instance, happens to be the 10th iteration.
Triggering To trigger on the nth recursive call of a recursive function To trigger on the nth recursive call of a recursive function 1 Select the state analyzer Trigger menu. 2 Define the terms CALL_ADD, F_START, and F_END to represent the called address of the recursive function, and the start and end addresses of the function. Define F_EXIT to represent the address of the first program statement executed after the original recursive call has terminated.
Triggering To trigger on the nth recursive call of a recursive function Triggering on the 22nd Call of a Recursive Function 1–7
Triggering To trigger on entry to a function To trigger on entry to a function This sequence triggers on entry to a function only when it is called by one particular function. 1 Select the state analyzer Trigger menu. 2 Define the terms F1_START and F1_END to represent the start and end addresses of the calling function. Define F2_START to represent the start address of the called function.
Triggering To trigger on entry to a function Triggering on Entry to a Function 1–9
Triggering To capture a write of known bad data to a particular variable To capture a write of known bad data to a particular variable The trigger specification ANDs the bad data on the data bus, write transaction on the status bus, and address of the variable on the address bus. 1 Select the state analyzer Trigger menu. 2 Define the terms BAD_DATA, WRITE, and VAR_ADDR to represent the bad data value, write status, and the address of the variable.
Triggering To trigger on a loop that occasionally runs too long To trigger on a loop that occasionally runs too long This example assumes the loop normally executes in 14 µs. 1 Select the state analyzer Trigger menu. 2 Define terms LP_START, LP_END, and Timer1 to represent the start and end addresses of the loop, and the normal duration of the loop. You can make the sequence specification closer to the problem domain by renaming Timer1 to LOOP_DUR.
Triggering To verify that all stacks and registers are restored correctly before exiting a subroutine To verify that all stacks and registers are restored correctly before exiting a subroutine The exit code for a function will often contain instructions for deallocating stack storage for local variables and restoring registers that were saved during the function call.
Triggering To trigger after all status bus lines finish transitioning To trigger after all status bus lines finish transitioning In some applications, you will want to trigger a measurement when a particular pattern has become stable. For example, you might want to trigger the analyzer when a microprocessor’s status bus has become stable during the bus cycle.
Triggering To find the nth assertion of a chip select line To find the nth assertion of a chip select line 1 Select the timing analyzer Trigger menu. 2 Define the glitch/edge1 term to represent the asserting transition on the chip select line. You can rename the Edge1 term to make it correspond more closely to the problem domain, for example, to CHIP_SEL.
Triggering To verify that the chip select line of a memory chip is strobed after the address is stable To verify that the chip select line of a memory chip is strobed after the address is stable 1 Select the timing analyzer Trigger menu. 2 Define a term called ADDRESS to represent the address in question and the Edge1 term to represent the asserting transition on the chip select line. You can rename the Edge1 term to suit the problem, for example, to MEM_SEL.
Triggering To trigger when expected data does not appear on the data bus from a remote device when requested To trigger when expected data does not appear on the data bus from a remote device when requested 1 Select the timing analyzer Trigger menu. 2 Define a term called DATA to represent the expected data, the Edge1 term to represent the chip select line of the remote device, and the Timer1 term to identify the time limit for receiving expected data.
Triggering To trigger when expected data does not appear on the data bus from a remote device when requested Triggering When I/O Data Not Returned 1–17
Triggering To test minimum and maximum pulse limits To test minimum and maximum pulse limits 1 Select the timing analyzer Trigger menu. 2 Define the Edge1 term to represent the positive-going transition, and define the Edge2 term to represent the negative-going transition on the line with the pulse to be tested. You can rename these terms to POS_EDGE and NEG_EDGE. 3 Define the Timer1 term to represent the minimum pulse width, and the Timer2 term to represent the maximum pulse width.
Triggering To test minimum and maximum pulse limits Triggering when a Pulse Exceeds Minimum or Maximum Limits 1–19
Triggering To detect a handshake violation To detect a handshake violation 1 Select the timing analyzer Trigger menu. 2 Define the Edge1 term to represent either transition on the first handshake line, and the Edge2 term to represent either transition on the second handshake line. You can rename these terms to match your problem, for example, to REQ and ACK.
Triggering To detect bus contention To detect bus contention In this sequencer setup, the trigger occurs only if both devices assert their bus transfer acknowledge lines at the same time. 1 Select the timing analyzer Trigger menu. 2 Define the Edge1 term to represent assertion of the bus transfer acknowledge line of one device, and Edge2 term to represent assertion of the bus transfer acknowledge line of the other device. You can rename these to BTACK1 and BTACK2.
Cross-Arming Trigger Examples The following examples use cross arming to coordinate measurements between two instruments. The cross-arming is set up in the Arming Control menu (obtained by selecting Arming Control in the Trigger menu). When coordinating measurements between two or more analyzers, select Count Time so you can correlate the measurements made by the two analyzers. See Also Chapter 2, “Intermodule Measurements.
Triggering To examine software execution when a timing violation occurs To examine software execution when a timing violation occurs The timing analyzer triggers when the timing violation occurs, and when it triggers, it also sets its “arm” level to true. When the state analyzer receives the arm signal, it triggers immediately on the present state. 1 Select the timing analyzer Trigger menu. 2 Define the Edge1 term to represent the control line where the timing violation occurs.
Triggering To look at control and status signals during execution of a routine To look at control and status signals during execution of a routine The state analyzer will trigger on the start of the routine whose control and status signals are to be examined with finer resolution than once per bus cycle. When it triggers, it will switch its “arm” level true. The timing analyzer will trigger when it receives the true arm level and detects the transition represented by glitch/edge1.
2 Intermodule Measurements
Intermodule Measurements An intermodule measurement is a measurement that is coordinated between two or more modules to capture different types of information related to a problem you are trying to solve. This chapter shows you how to make several kinds of intermodule measurements. Intermodule measurements can involve state analyzers, timing analyzers, oscilloscopes, and pattern generators.
Intermodule Measurements Intermodule Bus Block Functional Diagram 2–3
Intermodule Measurement Examples To set up an intermodule measurement, you must use the Intermodule menu. All modules that will participate in the intermodule measurement must be represented in this menu and their relationships must be shown under the Group Run field. To set up a group run of modules within the HP 16500C Modules are armed in the configuration tree by either an individual module or the Group Run field.
Intermodule Measurements To set up a group run of modules within the HP 16500C The analyzer in slot B is armed when the oscilloscope in slot D finds its trigger condition.
Intermodule Measurements To start a group run of modules from an external trigger source To start a group run of modules from an external trigger source 1 Connect the arm signal from the external instrument or system to the PORT IN BNC connector on the rear panel of the HP 16500 frame. 2 Select the Intermodule menu. 3 Set up the group run specification. 4 Select the PORT IN/OUT field.
Intermodule Measurements To start a group run of modules from an external trigger source Both the analyzer in slot B and the oscilloscope in slot D are armed when the PORT IN signal arrives.
Intermodule Measurements To start an external instrument on command from a module within the HP 16500 and 16501 mainframe To start an external instrument on command from a module within the HP 16500 and 16501 mainframe You can set up a module in a group run so that it sends a pulse through the PORT OUT rear panel BNC. The pulse can be used to start or stop a measurement in an external instrument or system. 1 Set up the group run specification.
Intermodule Measurements To start an external instrument on command from a module within the HP 16500 and 16501 mainframe The analyzer in slot B drives port out after finding its trigger.
Intermodule Measurements To see the status of a module within an intermodule measurement To see the status of a module within an intermodule measurement 1 Select the Intermodule menu. 2 Find the name of the module under the “Modules” list, and read the status under the module name. The status can be either Running or Stopped. You can interpret these indications as follows: • If a module was running and is now stopped, assume it received its arming signal, triggered, and finished its measurement properly.
Intermodule Measurements To see the status of a module within an intermodule measurement Both modules are running because neither has found its respective trigger condition.
Intermodule Measurements To see time correlation of each module within an intermodule measurement To see time correlation of each module within an intermodule measurement Time correlation in the intermodule menu can help you see when the trigger occurred for each module and the relative time range of data captured by that module. 1 Select Time in the Count field of the trigger menu of each logic state analyzer whose measurement will be time-correlated with the other modules.
Intermodule Measurements To see time correlation of each module within an intermodule measurement This portion of the bar indicates the relative time range of data acquired by this module. T indicates the time at which the trigger was found.
Intermodule Measurements To use a timing analyzer to detect a glitch To use a timing analyzer to detect a glitch The following setup uses a state analyzer to capture state flow occurring at the time of the glitch. This can be useful in troubleshooting. For example, you might find that the glitch is ground bounce caused by a number of simultaneous signal transitions. 1 Select the Intermodule menu. 2 Select the timing analyzer from the Modules list and set it to Group Run.
Intermodule Measurements To capture the waveform of a glitch To capture the waveform of a glitch The following setup uses the triggering capability of the timing analyzer and the acquisition capability of the oscilloscope. 1 Select the Intermodule Menu. 2 Select the timing analyzer from the Modules list and set it to Group Run. Select the oscilloscope module and set it to respond to the arm signal from the timing analyzer. 3 Select the timing analyzer module.
Intermodule Measurements To capture state flow showing how your target system processes an interrupt To capture state flow showing how your target system processes an interrupt Use an oscilloscope with a sample rate faster than the microprocessor clock rate to trigger on the asynchronous interrupt request. 1 Select the Intermodule menu. 2 Select the oscilloscope from the Modules list and set it to Group Run.
Intermodule Measurements To test a circuit using stimulus-response To test a circuit using stimulus-response 1 Select the Intermodule menu. 2 Select the pattern generator from the Modules list and set it to Group Run. Select the oscilloscope module and set it to respond to the arm signal from the pattern generator. Select the state analyzer and set it to respond to the arm signal from the pattern generator.
Intermodule Measurements To use a state analyzer to trigger timing analysis of a count-down on a set of data lines To use a state analyzer to trigger timing analysis of a count-down on a set of data lines 1 Select the Intermodule menu. 2 Select the state analyzer from the Modules list and set it to Group Run. Select the timing analyzer and set it to respond to the arm signal from the state analyzer. 3 Select the state analyzer Trigger menu.
Intermodule Measurements To monitor the activity of two coprocessors in a target system To monitor the activity of two coprocessors in a target system Debugging coprocessor systems can be a complex task. Replicated systems and contention for shared resources increase the potential problems. Using two state analyzers with preprocessors can make it much easier to discover the source of such problems.
Intermodule Measurements To monitor the activity of two coprocessors in a target system 7 Select Group Run from the upper right corner of the display. After the measurement is complete, you can interleave the trace lists of both state analyzers to see the activity executed by both coprocessors during related clock cycles.
Special displays Interleaved Trace Lists Interleaved trace lists allow you to view data captured by two or more analyzers in a single trace list. When you interleave the traces, you see each state that was captured by each analyzer. These states are shown on consecutive lines. You can interleave state listings from HP 16510B, 16540A, 16540D, and 16550A state analyzers, when two or more are used together in a group run.
Intermodule Measurements To interleave trace lists To interleave trace lists 1 Set up the analyzers whose data you wish to interleave as part of a group run. You won’t need to do this if the two measurement modules for which you want mixed display are really part of the same module. For example, you might have an HP 16550A state/timing analyzer configured as two separate analyzers, one a state analyzer, the other a timing analyzer.
Intermodule Measurements To interleave trace lists Labels for the interleaved states are shown above those for the primary analyzer. Interleaved states are shown in yellow with line numbers indented from those of the primary analyzer. Interleaved Trace Lists on the HP 16550A See Also “To set up a group run of modules within the HP 16500C” in this chapter.
Intermodule Measurements To view trace lists and waveforms together on the same display To view trace lists and waveforms together on the same display 1 Set up the modules whose data you wish to view as part of a group run. You won’t need to do this if the two measurement modules for which you want mixed display are really part of the same module. For example, you might have an HP 16550A state/timing analyzer configured as two separate analyzers, one a state analyzer, the other a timing analyzer.
Intermodule Measurements To view trace lists and waveforms together on the same display You can use the Mixed Display feature in the state analyzer menus to show both waveforms and trace lists in the same display, making it easier to correlate the events of interest. If you are using mixed display as part of a group run, you may need to adjust intermodule skew to ensure proper time correlation and display results.
Skew Adjustment You can modify the skew or timing deviation between modules within the intermodule measurement. This allows you to compensate for any known delay of the system under test, or to compare two signals by first removing any displayed skew between the signal channels. Skew adjustments can correct module delays to within 2 ns of other modules.
Intermodule Measurements To adjust for minimum skew between two modules involved in an intermodule measurement To adjust for minimum skew between two modules involved in an intermodule measurement 1 Connect an input signal from each module to the same signal. An ideal signal for testing skew is a single-shot signal with fast risetime. Such a signal simplifies triggering and makes it easier to correlate the input event between the modules.
Intermodule Measurements To adjust for minimum skew between two modules involved in an intermodule measurement 8 Record the differences shown by the two modules. You can use the X and O markers to measure the differences in delays. 9 Select the Intermodule Menu. 10 Select Skew, then enter a skew correction value for one of the modules using the knob or the keyboard. 11 Return to the module waveform display and recheck the skew adjustment.
3 File Management
File Management A host computer such as a PC or UNIX workstation can enhance the HP 16500C in many ways. You can use the host to store configuration files or measurement results for later review. Screen images from the HP 16500C can be saved in bitmap files for inclusion in reports developed using word processors or desktop publishing tools. Or, you can develop programs on the PC that manipulate measurement results to satisfy your problem-solving needs.
Transferring Files Using the Flexible Disk Drive Because the flexible disk drive on the HP 16500C will read and write double-sided, double density or high-density disks in MS-DOS format, it is a useful tool for transferring images to and from IBM PC-compatible computers as well as other systems that can read and write MS-DOS format. You can save measurement configuration files, measurement results, and even menu and measurement images from the screen.
File Management To save a measurement configuration To save a measurement configuration You can save measurement configurations on a 3.5-inch disk or on the internal hard disk for later use. This is especially useful for automating repetitive measurements for production testing. 1 Select System from the module field. 2 Select Hard Disk or Flexible Disk from the menu field. 3 Select Store from the disk operations field. 4 Select the module for which you want to save the configuration from the module list.
File Management To save a measurement configuration Saving the Oscilloscope Configuration for Skew Testing If you want to save your file in a directory other than the root, you can select Change Directory from the disk operations field. Then type the name of the desired directory in the directory name field, or select it from the list of visible directories using the knob.
File Management To load a measurement configuration To load a measurement configuration You can quickly load a previously saved measurement configuration, saving the trouble of manually setting up the measurement parameters for each module. 1 Select System from the module field. 2 Select Hard Disk or Flexible Disk from the Menu field. Your choice here depends on where you saved the configuration. 3 Select Load from the disk operations field.
File Management To load a measurement configuration Loading Configuration for all HP 16500C Modules and the System 3–7
File Management To save a trace list in ASCII format To save a trace list in ASCII format Some HP 16500C displays, such as file lists and trace lists, contain columns of ASCII data that you may want to move to a PC for further manipulation or analysis. You can save these displays as ASCII files, using a procedure similar to that for creating graphics images.
File Management To save a trace list in ASCII format 68332EVS - State Listing Label ADDR CPU32 Mnemonic STAT __________ _____ ______________________________________ _________________ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 406F4 ANDI.L #********,(A6)+ 0FF7A 0004 data write 0FF7C 06F6 data write 40992 BSR.B 0004093E 40994 nu MOVE.B ********,(****,A7) 0FF76 0004 data write 0FF78 0994 data write 4093E MOVE.
File Management To save a menu or measurement as a graphic image To save a menu or measurement as a graphic image You can save menus and measurements to disk in one of four different graphics formats. 1 Insert a DOS-formatted flexible disk in the flexible disk drive. 2 Set up the menu whose image you want to capture, or run a measurement from which you want to save data. 3 Select Print Disk from the Print menu. 4 Select the Filename field and specify a file name to which the screen will be printed.
File Management To save a menu or measurement as a graphic image An Oscilloscope Display Saved as a TIF Image 3–11
File Management To load system software To load system software 1 2 3 4 5 6 7 8 Insert the first disk containing the system software. Select System from the module field. Select Hard Disk from the menu field. Select Change Directory from the disk operation field. Select the directory SYSTEM using the knob, and select Execute. Select Flexible Disk from the menu field. Select Copy from the disk operation field. Select the file you want to update using the knob, then select Execute.
Using the LAN Interface The LAN Interface of the HP 16500C extends the Logic Analysis System by making it look like a NFS (Network File System) node. Using NFS utilities for the PC or NFS on a UNIX workstation, you can transfer files to and from the HP 16500C as if it were a disk drive attached to your machine. The LAN Interface also creates virtual directories and files for measurement configurations and results, so you can store and retrieve these as though they were ordinary files.
File Management To set up the HP 16500C To set up the HP 16500C You can set up the HP 16500C from the front panel, or via the LAN. To set up the system via the LAN, you can use one of three methods: • Copy a configuration file from your PC or workstation to one of the files called setup.raw in the HP 16500C directory tree. • Remotely load a configuration file into the system from one of the local disk drives of the HP 16500C.
File Management To set up the HP 16500C Example You want to load a configuration file called “486_bus” from the hard disk of the HP 16500C into an HP 16550A state/timing module. The HP 16550A is installed in slot B of the HP 16500C mainframe. To load the configuration file from the HP 16500C hard disk, you need to send the programming command to the analyzer.
File Management To transfer data files from the HP 16500C system to your computer To transfer data files from the HP 16500C system to your computer You can transfer data from the HP 16500C system to your PC or workstation by copying files. Data files in binary format are available in file locations \slot_x\data.raw. These binary files can be transferred to your computer and then reloaded into the HP 16500C system later. For some types of measurement modules, data files in ASCII format are also available.
File Management To transfer data files from the HP 16500C system to your computer Example You have an HP 16550A state/timing analyzer installed in slot C of your HP 16500C mainframe. The name of analyzer 1 of the HP 16550A is 68000_BUS. You have created some labels under analyzer 1 of the HP 16550A, including one called “addr_lo.” The directory structure of the HP 16500C system looks like this: After setting up a measurement and acquiring data, you want to analyze the data for label addr_lo on your PC.
File Management To transfer graphics files from the HP 16500C system to your computer To transfer graphics files from the HP 16500C system to your computer The current display of the HP 16500C is available in four different formats. 1 Set up the display you want to transfer. 2 Copy the file in the format of your choice from the directory \system\graphics. • The file screen.tif is a color Tagged Image File Format file, in TIFF version 5.0 format. • The file screenbw.
4 Concepts
Concepts Understanding how the analyzer does its job will help you use it more effectively and minimize measurement problems. This chapter explains the general operation of the trigger sequencer and the inverse assembler.
The Trigger Sequencer Logic state and timing analyzer modules for the HP 16500C have triggering and data storage features that allow you to capture only the system activity of interest. Understanding how these features work will help you set up analyzer trigger specifications that satisfy your measurement needs. There are several different logic analyzers available for the HP 16500C. This discussion will focus on the HP 16550A, a 100-MHz state/500-MHz timing analyzer.
Concepts A sequence-else specification can branch to the same state... Sequence-advance specifications always branch to the next state. to a previous state... or a later state. Each state can have a unique storage specification. State Analyzer Sequencer with Four States Each state, except for the last, has two branch conditions. These are the sequence-advance and sequence-else specification.
Concepts Sequence-Else Specification The sequence-else branch, sometimes called the “else if” branch or secondary branch, may branch to any other state, including the current state, a previous state, or a later state. The sequence-else specification looks like the following: Else on "" go to level If the Sequence-Else specification is satisfied before the sequence-advance specification is satisfied, the sequencer begins at .
Concepts you want to capture activity after the trigger is captured, define an additional sequence level and specify the desired storage qualification for post-trigger activity (for example, store “anystate”). Analyzer Resources The sequence-advance, sequence-else, storage, and trigger-on specifications are set by a combination of up to 10 pattern terms, 2 range terms, and 2 timers. Different analyzer models may vary in the number of resources available.
Concepts Where can be a single value on a set of labels, any value within a range of values on a set of labels, or a glitch or edge transition on a bit or set of bits. Limitations Affecting Use of Analyzer Resources There are limitations on the way resources can be combined to form complex pattern expressions. Resources are combined in a four-level hierarchy. First, resources are divided into two groups. The groups can be combined with AND or OR.
Concepts Table 4-1 HP 16550A Resource Division Group Group 1 Pair Pair 1 Pair 2 Pair 3 Pair 4 Group 2 Pair 1 Pair 2 Pair 3 Pair 4 Resource Operation Off, On, Negate Off, On, Negate Off, On, Negate Off, In Range, Out of Range Off, On, Negate Off, On, Negate Off, On, Negate Off, <, > Off, On, Negate Off, On, Negate Off, On, Negate Off, In Range, Out of Range Off, On, Negate Off, On, Negate Off, On, Negate Off, <, > Resource a b c Range 1 d Edge 1 e Timer 1 f g h Range 2 i Edge 2 j Timer 2 Pair Links C
Concepts The following figure shows the possible combinations of the a, b, c and Range1 terms: Combining a, b, c, and Range1 Terms The following combination is not valid, because pairs cross group boundaries: ((a+b) + (h • In_Range2)) • (j xor Timer2 > 400 ns) Note that the analyzer interface will not allow you to enter invalid combinations, however, you need to be aware of what combinations are legal, so that you can make the desired measurement.
The Inverse Assembler When the analyzer captures a trace, it captures binary information. The analyzer can then present this information in binary, octal, decimal, hexadecimal, or ASCII. Or, if given information about the meaning of the data captured, the analyzer can inverse assemble the trace. The inverse assembler makes the trace list more readable by presenting the trace results in terms of processor opcodes and data transactions.
Concepts The inverse assembler synchronizes at the first line in the trace list... not at the cursor position Inverse Assembly Synchronization If you roll the trace list to a new position and press Invasm again, the inverse assembler repeats the above process. However, it does not work backward in the trace list from the starting position. This may cause differences in the trace list above and below the point where you synchronized inverse assembly.
Concepts Symbols When you specify symbols as the format for displaying the address bus in the trace list, the symbol lookup happens independently of inverse assembly. Thus, you can have symbols in the address field without inverse-assembled data and status. The HP E2450A symbol download utility allows you to download symbols from OMF (Object Module Format) files. See Also The Preprocessor User’s Guide for more information on switch settings.
Configuration Translation for Analyzer Modules Configuration files provide an easy way for you to save and restore measurement setups, simplifying repeated measurements. However, sometimes you might change analyzer modules in the HP 16500C Logic Analysis System to gain additional measurement features. Or, you might want to use a configuration file from one HP 16500C system on another HP 16500C with a different analyzer module.
Concepts remove pod assignments. Which pods are removed from the configuration will depend on the widths of each pod in the original analyzer and new analyzer. The configuration translation also needs to account for many differences in the format and trace menus between the analyzers, including • • • • • • • • label names, polarities, thresholds, symbols, clocking, number of sequence levels, branch conditions, and patterns, among others.
Concepts When you move a configuration file from one analyzer to another, the trace data from previous measurements is not moved. If you need to store trace data for future reference, see “To save a trace list in ASCII format” in chapter 3.
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5 If You Have a Problem
If You Have a Problem Occasionally, a measurement may not give the expected results. If you encounter difficulties while making measurements, use this chapter to guide you through some possible solutions. Each heading lists a problem you may encounter, along with some possible solutions. Error messages which may appear on the logic analyzer are listed below in quotes “ ”. Symptoms are listed without quotes.
Analyzer Problems This section lists general problems that you might encounter while using the analyzer. Intermittent data errors This problem is usually caused by poor connections, incorrect signal levels, or marginal timing. Remove and reseat all cables and probes; ensure that there are no bent pins on the preprocessor interface or poor probe connections. Adjust the threshold level of the data pod to match the logic levels in the system under test.
If You Have a Problem No Setup/Hold field on format screen No Setup/Hold field on format screen The HP 16540 and 16541 (A and D models), or HP 16542A logic analyzer cards are not calibrated. Refer to your logic analyzer reference manual for procedures to calibrate the cards. No activity on activity indicators On the HP 16510A Logic Analyzer, check the fuse that allows power to the preprocessor interface.
If You Have a Problem No trace list display No trace list display If there is no trace list display, it may be that your analysis specification is not correct for the data you want to capture, or that the trace memory is only partially filled. Check your analysis sequencer specification to ensure that it will capture the events of interest. Try stopping the analyzer; if the trace list is partially filled, this should display the contents of trace memory.
Preprocessor Problems This section lists problems that you might encounter when using a preprocessor. If the solutions suggested here do not correct the problem, you may have a defective preprocessor. Refer to the User’s Guide for your preprocessor for test procedures. Contact your local Hewlett-Packard Sales Office if you need further assistance.
If You Have a Problem Slow clock Slow clock If you have the preprocessor interface hooked up and running and observe a slow clock or no activity from the interface board, the +5 V supply coming from the analyzer may not be getting to the interface board. To check the +5 V supply coming from the analyzer, disconnect one of the logic analyzer cables from the preprocessor and measure across pins 1 and 2 or pins 39 and 40.
If You Have a Problem Erratic trace measurements Try doing a full reset of the target system before beginning the measurement. Some preprocessor designs require a full reset to ensure correct configuration. Ensure that your target system meets the timing requirements of the processor with the preprocessor probe installed. See “Capacitive Loading” in this chapter. While preprocessor loading is slight, pin protectors, extenders, and adapters may increase it to unacceptable levels.
Inverse Assembler Problems This section lists problems that you might encounter while using the inverse assembler. When you obtain incorrect inverse assembly results, it may be unclear whether the problem is in the preprocessor or in your target system. If you follow the suggestions in this section to ensure that you are using the preprocessor and inverse assembler correctly, you can proceed with confidence in debugging your target system.
If You Have a Problem Inverse assembler will not load or run Check the activity indicators for status lines locked in a high or low state. Verify that the STAT, DATA, and ADDR format labels have not been modified from their default values. These labels must remain as they are configured by the configuration file. Do not change the names of these labels or the bit assignments within the labels. Some preprocessors also require other data labels; check your Preprocessor User’s Guide for more information.
Intermodule Measurement Problems Some problems occur only when you are trying to make a measurement involving multiple modules. An event wasn’t captured by one of the modules If you are trying to capture an event that occurs very shortly after the event that arms one of the measurement modules, it may be missed, due to internal analyzer delays.
Messages This section lists some of the messages that the analyzer displays when it encounters a problem. “Default Calibration Factors Loaded” (HP 16540, 16541, and 16542) The default calibration file for the logic analyzer was loaded. The logic analyzer must be calibrated when using HP 16540A/D, HP 16541A/D or HP 16542A cards. Refer to the Logic Analyzer Reference for procedures to calibrate the master clocking system, and ensure that the “cal factors” file is saved.
If You Have a Problem “Measurement Initialization Error” “Measurement Initialization Error” This error occurs when you have installed the cables incorrectly for one or two HP 16550A logic analysis cards. The following diagrams show the correct cable connections for one-card and two-card installations. Ensure that your cable connections match the drawing, then repeat the measurement.
If You Have a Problem “No Configuration File Loaded” “No Configuration File Loaded” This is usually caused by trying to load a configuration file for one type of module or the system into a different type of module. Verify that the appropriate module has been selected from the Load {module} from File {filename} in the HP 16500 disk operation menu. Selecting Load {All} will cause incorrect operation when loading most preprocessor interface configuration files.
If You Have a Problem “State Clock Violates Overdrive Specification” “State Clock Violates Overdrive Specification” At least one 16-channel pod in the state analysis measurement stored a different number of states before trigger than the other pods. This is usually caused by sending a clocking signal to the state analyzer that does not meet all of the specified conditions, such as minimum period, minimum pulse width, or minimum amplitude. Poor pulse shaping could also cause this problem.
If You Have a Problem “Waiting for Trigger” “Waiting for Trigger” If a trigger pattern is specified, this message indicates that the specified trigger pattern has not occurred. Verify that the triggering pattern is correctly set. When analyzing microprocessors that fetch only from long-word aligned addresses, if the trigger condition is set to look for an opcode fetch at an address not corresponding to a long-word boundary, the trigger will never be found.
6 Application Notes
Application Notes Hewlett-Packard has prepared several application notes and product notes that show you how to get more out of your HP 16500C Logic Analysis System. Each note focuses on a particular application or problem, showing you the components of the problem, the approach required to solve it, the instrumentation, and the measurement results. The following table lists the application notes and product notes relevant to the HP 16500C Logic Analysis System.
Application Notes Note Number HP Part Number Title Description Application Note 1225-3 5091-5447E Digital Video Testing with the HP 16542A Uses the deep memory of the HP 16542A with the complex triggering capabilities of that module and of the 16550A state/timing analyzer to capture and analyze data from a digital video stream. Application Note 1244-1 5962-8620E Discusses physical and electrical considerations for probing circuits with an analyzer.
6–4
Glossary acquisition Denotes one complete cycle of data gathering by a module. For example, in the HP 16532 oscilloscope, one complete cycle gathers 8000 samples of information and stores them in acquisition memory. arm The arm output from a module is set false when the module begins running and is set true when the module finds its trigger condition. Other measurement modules that take the arm signal as an input are unable to capture data or search for their triggers until they receive their arm signal.
Glossary in the Delay field, and is set by using the knob or the keypad. deskewing To cancel or nullify the effects of differences between two different internal delay paths for a signal. Deskewing is normally done by routing a single test signal to the inputs of two different modules, then adjusting the delay path to one of the modules so that both modules recognize the signal at the same state at the same time.
Glossary ment to make interactive measurements, either with other modules in the mainframe or with external modules. labels Labels are the names of pods/bits that are used to identify signal channels or buses. A label is assigned to identify a bit or set of bits. low The most-negative portion of a logic signal. Used in pattern trigger measurements, it is represented by an L in the pattern selector.
Glossary can be set from 1:1 to 1000:1 in increments of 1. range terms In the analyzer, the range terms represent ranges of values to be found on labeled sets of bits. For example, a range of addresses to be found on the address bus or a range of data values to be found on the data bus. Range terms are satisfied by any value within the range for “In_Range,” and by any value outside the range for “Out_Range.
Glossary You should adjust measurement modules to eliminate as much skew as possible so that it does not affect the accuracy of your measurements. source field In the oscilloscope, the field that allows you to select a channel for edge triggering and trigger level setting. state sequence levels The individual states for the trigger sequencer in the state analyzer. For example, the HP 16550A has twelve states in its trigger sequencer.
Glossary trigger Trigger is a reference event around which you want to gather information. In the analyzer, you might want to trigger on a glitch in hardware or entry to a subroutine in software. When beginning, you might want to trigger on the first occurrence of any kind (trigger on “anystate”). As you learn more about the problem you are trying to isolate, you may enter more specific trigger conditions.
Glossary -002, etc), and states captured after the trigger are numbered with positive numbers (001, 002, etc). vertical position See offset field. V/div See vertical sensitivity vertical sensitivity In the oscilloscope, the voltage value that determines the amplitude of the waveform on the screen. It is measured in volts per division and is viewed in the V/div field. You change the vertical sensitivity using the knob or the keypad. when field In the oscilloscope, part of the Pattern Mode menu.
Glossary–8
Index A Activation record, 1–6 Address bus, 4–10 Address ranges, 1–3 Analyzer concepts, 4–2 Analyzer problems, 5–3 capacitive loading, 5–4 intermittent data errors, 5–3 no activity on activity indicators, 5–4 no setup/hold field on format screen, 5–4 unwanted triggers, 5–3 Anystate, 1–5, 2–4, 4–5 Arm input, 2–2 Arm level, 1–24 Arm signal, 1–23 Arming Control menu See Intermodule Measurements ASCII format, 3–16 files, 3–16 Asynchronous interrupt request trigger on, 2–16 E Else-if branch, 4–5 Encapsulated P
Index N NFS node, 3–13 No state, 1–3, 4–5 Non-reference channel, 2–26 Not, 4–5 O Onscreen keypad, 2–6 Output Disk menu, 3–8 Output Format field, 3–8 P Pair boundaries, 4–8 Pairs, 4–7 Pattern expression, 4–7 Pattern generators, 2–17 Pattern terms, 4–6 PC Paintbrush files, 3–10 Pipelining add depth to start address, 1–4 PORT IN BNC connector, 2–6 PORT IN BNC level, 2–6 PORT IN/OUT Field, 2–6 Port input line, 2–2 PORT OUT choices, 2–8 Preprocessor problems, 5–6 erratic trace measurements, 5–7 slow clock, 5–7
Index V Verifying chip select line is strobed, 1–15 correct execution, 1–3 correct storage, 1–12 efficiency, 1–3 Viewing trace lists and waveforms together, 2–25 W Watchdog timer behavior, 2–20 Waveforms deleting, 2–27 inserting, 2–27 viewing with trace lists, 2–25 Index–3
Index–4
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