HP Compilers for HP Integrity Servers (September 2011)

extensive use of sophisticated Itanium processor family features such as predication,
speculation, and data prefetching.
Figure 1 Internal structure of the HP compilers
Optimizing for Integrity servers
The Intel Itanium architecture seeks to reduce execution time by maximizing instruction-level
parallelism—the concurrent execution of multiple instructions. It provides three key features
that enable the compiler to maximize instruction-level parallelism (ILP):
• Predication
• Speculation, both of control and data
• Explicit parallelism
While support from the architecture for these features is critical, the compiler must exploit
these features to their utmost in order to deliver superior application performance.
Predication
Predication is the conditional execution of an instruction based on the setting of a boolean
value contained in a predicate register. The Intel Itanium architecture provides 64
predicate registers that can be used to control the execution of nearly all instructions.
In the example below, both assignments to x can execute in the same cycle (because
both predicates are never simultaneously true), saving two instructions and at least one
execution cycle, and avoiding any risk of branch misprediction.
Optimizing for Integrity servers 5