HP Compilers for HP Integrity Servers (September 2011)

Example 5 Code from Example 4 using control speculation
ld.s t1 = [p] ;;
add b = t1,2
cmp.ne.unc p1,p0 = condition,0 ;;
(p1) chk.s t1, L2
L1:
...
L2: ld t1 = [p] ;;
add b = t1,2
br L1
If the NaT bit on register t1 is set, the chk.s instruction branches to the recovery code
located at L2. Recovery code reloads t1 without speculation, then recomputes the result
in b. (p1) is a predicate used to determine whether the result is needed.
A variety of factors could cause a speculative load to result in a NaT token and potentially
trigger the execution of recovery code. Loads from invalid addresses usually generate
an exception on a traditional architecture; speculative loads from invalid addresses result
in NaT. In addition, a miss in the translation-lookaside buffer (TLB) on the control
speculative load usually results in a NaT when recovery code is present. A TLB is a cache
of translations from virtual memory addresses to physical addresses and physical
addresses to virtual memory addresses.
Data speculation
Data speculation involves the early execution of a load prior to one or more store
instructions that both:
• preceded the load in original program order.
• might write to the same memory location as is read by the load.
Data speculation can reduce the overall number of required cycles because it increases
instruction level parallelism.
Example 6 Using data speculation
int a,b
extern int *p;
extern int *q;
*p = a;
b = *q + 2;
Use of data speculation moves the last statement performing a load of *q above the
store of *p, even though *p and *q may be the same memory location.
The Intel Itanium architecture allows the compiler to exploit this type of speculation safely
by providing a facility to dynamically identify address conflicts and by allowing the
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