HP Caliper 5.3 User Guide (5900-1558, February 2011)

L1I_PREFETCHES Provides information about the number of issued L1 cache
line prefetch requests (64 bytes/line). The reported number
includes streaming and non-streaming prefetches. Hits and
misses in L1 instruction cache are both included.
L1 Instruction Cache Read Misses Number of L1 instruction cache read misses.
L1 Instruction Cache Demand Miss
Percentage
Percentage of demand fetch reads that missed.
Total L1 Instruction Cache References Sum of demand fetch reads and L1 cache line prefetch
requests.
Metrics for Integrity Servers Dual-Core Itanium 2 and Itanium 9300 Quad-Core Processor Systems
BACK_END_BUBBLE.ALL Full Pipe Bubbles in Main Pipe due to all causes.
This is the number of cycles lost (stall cycles) due to any of
five possible events (FPU/L1D, RSE, EXE, branch/exception,
or the front-end).
BACK_END_BUBBLE.FE Full Pipe Bubbles in Main Pipe due to front end.
This is the number of cycles lost (stall cycles) due to
instruction cache ITLB and branch execution stalls.
CPU_OP_CYCLES.ALL Number of elapsed CPU operating cycles.
IA64_INST_RETIRED Number of retired IA–64 instructions. The count includes
predicated on and predicated off instructions, and nops,
but excludes hardware-inserted RSE operations.
L1I_PREFETCHES Number of issued L1 cache line prefetch requests (64
bytes/line). For more information, see L1I_PREFETCHES.
L1I_READS Number of demand fetch reads to the L1 instruction cache
(32-byte chunks). For more information, see L1I_READS .
L2I_DEMAND_READS Number of instruction requests to L2 instruction cache due
to L1 instruction cache demand fetch misses. This includes
the number of demand fetches that miss both the L1
instruction cache and the ISB, regardless of whether they
hit or miss in the RAB.
L2I_PREFETCHES Number of prefetch requests issued to the L2 instruction
cache. This includes streaming and non-streaming prefetches.
L2I_READS.ALL.ALL Number of cacheable code reads handled by the L2
instruction cache.
L2I_READS.MISS.ALL Number of demand fetch and prefetch misses in cacheable
code reads handled by the L2 instruction cache. This only
includes the primary misses.
L2I_READS.MISS.DMND Number of demand fetch misses in cacheable code reads
handled by the L2 instruction cache. This includes the
primary misses.
% of Cycles lost due to all stalls
(lower is better)
Percentage of cycles lost due to all stalls.
% of Cycles lost due to Front end
stalls (ICACHE, ITLB and branch
execution)
Percentage of cycles lost due to instruction cache, instruction
translation lookaside buffer, and branch execution stalls.
L1 instruction cache references Number of L1 instruction cache references.
L1 instruction cache misses Number of L1 instruction cache prefetch and demand fetch
misses.
L1 instruction cache miss percentage Percentage of L1 instruction demand fetch and prefetch that
are misses.
icache Measurement Report Description 205