HP Caliper 5.3 User Guide (5900-1558, February 2011)

BE_LOST_BW_DUE_TO_FE.IMISS Number of invalid bundles at the exit from Instruction Buffer
due to instruction cache miss stalls (only if the back end is
not stalled for other reasons).
BE_LOST_BW_DUE_TO_FE.TLBMISS Number of invalid bundles at the exit from Instruction Buffer
due to instruction TLB miss stalls (only if the back end is not
stalled for other reasons).
CPU_OP_CYCLES.ALL Number of elapsed CPU operating cycles.
IA64_INST_RETIRED Number of retired IA-64 instructions. The count includes
predicated on and predicated off instructions and nops, but
excludes hardware-inserted RSE operations.
ITLB_MISSES_FETCH.L1ITLB Number of L1 ITLB misses for demand fetch.
ITLB_MISSES_FETCH.L2ITLB Number of L2 ITLB misses for demand fetch.
L1ITLB_INSERTS_HPW Number of instruction TLB inserts done by the hardware
page walker (HPW).
L1I_READS The number of data memory read references issued into the
memory pipeline that are serviced by L1D (only integer
loads), RSE loads, L1-hinted loads (L1D returns data if it hits
in L1D but does not do a fill), and check loads (ld.c).
Non-cacheable reads, VHPT loads, semaphores,
floating-point loads, and lfetch instructions are not counted
here because L1D does not handle these. The count includes
wrong path operations but excludes predicated off
operations.
% of Cycles lost due to all stalls
(lower is better)
Percentage of cycles lost due to all stalls.
% of Cycles lost due to Front end
stalls (ICACHE, ITLB, and branch
execution)
Pecentage of cycles lost due to ICACHE, ITLB and branch
execution stalls.
% of Cycles lost due to instruction TLB
stalls
Percentage of cycles lost due to instruction TLB miss stalls.
% of Cycles lost due to instruction
cache stalls
Perdcentage of cycles lost due to instruction cache miss
stalls.
% of Cycles lost due to instruction
access stalls (ICACHE and ITLB)
Perdcentage of cycles lost due to instruction cache miss and
instruction TLB miss stalls.
% of Cycles lost due to branch
execution
Percentage of cycles lost due to branch execution (branch
re-steer).
Total L1 instruction TLB references Number of L1 instruction TLB references.
L1 instruction TLB miss percentage Percentage of L1 instuction TLB accesses that missed.
L2 instruction TLB misses Number of L2 instruction TLB misses.
Percentage of L2 ITLB misses covered
by the HPW
Percentage of L2 ITLB misses that were serviced by the
hardware page walker (HPW).
L1 ITLB miss per 1000 instructions
retired
Number of L1 ITLB misses per 1000 instructions retired.
L2 ITLB miss per 1000 instructions
retired
Number of L2 ITLB misses per 1000 instructions retired.
itlb Measurement Report Metrics
See Table 28 (page 210).
In this table, “program object” refers to any of the following:
• Thread
• Load module
itlb Measurement Report Description 209