HP Caliper 5.3 User Guide (5900-1558, February 2011)

traps Metrics Summed for Entire Run
This section describes the metrics summed over the entire run of your application under HP Caliper.
BACK_END_BUBBLE.FE Full pipe bubbles in main pipe due to front end. This is the
number of cycles lost (stall cycles) due to instruction cache,
ITLB, and branch execution stalls.
BE_EXE_BUBBLE.ALL Full pipe bubbles in main pipe due to execution unit stalls.
This is the number of cycles lost (stall cycles) due to stalls
caused by the execution unit.
BE_EXE_BUBBLE.FRALL Full Pipe Bubbles in Main Pipe due to FR/FR or FR/load
dependency stalls. This is the number of cycles lost (stall
cycles) due to FR/FR or FR/load dependency.
BE_EXE_BUBBLE.GRALL Full pipe bubbles in main pipe due to general
register/general register or general register/load
dependency stalls. This is the number of cycles lost (stall
cycles) due to general register/general register or general
register/load dependency.
BE_EXE_BUBBLE.GRGR Full Pipe Bubbles in Main Pipe due to GR/GR dependency
stalls. This is the number of cycles lost (stall cycles) due to
GR/GR dependency stalls.
BE_FLUSH_BUBBLE.ALL Full Pipe Bubbles in Main Pipe due to pipeline flushes. This
is the number of cycles lost (stall cycles) due to branch
misprediction or exception/interruption flush.
BE_L1D_FPU_BUBBLE.ALL
BE_L1D_FPU_BUBBLE.L1D Full Pipe Bubbles in Main Pipe due to L1D cache. This is the
number of cycles lost (stall cycles) due to L1D cache and
L1/L2 DTLB.
BE_RSE_BUBBLE.ALL Full Pipe Bubbles in Main Pipe due to RSE stalls. Percentage
of cycles lost due to stalls in RSE spilling/filling registers
to/from memory.
CPU_OP_CYCLES.ALL Number of elapsed CPU operating cycles. (Note: This event
is called CPU_CYCLES on Itanium 2 systems.)
When HyperThreading is on, this is the number of elapsed
CPU operating cycles used by only this process's
hyperthread.
CPU_OP_CYCLES.ALL:all_threads=true Number of elapsed CPU operating cycles used by both
hyperthreads. Available only when HyperThreading is on.
% Unstalled execution (higher is
better)
Percentage of unstalled cycles with respect to total number
of elapsed CPU operating cycles.
% of Cycles lost due to front end
stalls (lower is better)
Percentage of cycles lost due to instruction cache, ITLB, and
branch execution stalls.
% of Cycles lost due to Pipeline flush
stalls (lower is better)
Percentage of cycles lost due to branch misprediction or
interruption flush.
% of Cycles lost due to data access
stalls (lower is better)
Percentage of stall cycles lost due to DCACHE and DTLB
stalls.
% of Cycles lost due to RSE stalls
(lower is better)
Percentage of cycles lost due to stalls in RSE spilling/filling
registers to/from memory.
% of Cycles lost due to Scoreboard
stalls (lower is better)
Percentage of stall cycles lost due to FPU and register
dependency stalls. It excludes FR/FR dependency stalls.
% of Cycles lost due to front-end stalls Percentage of stall cycles lost due to front-end stalls.
% of Cycles lost due to pipeline-flush
stalls
Percentage of stall cycles lost due to pipeline-flush stalls.
216 Descriptions of Measurement Reports