HP Caliper 5.3 User Guide (5900-1558, February 2011)

The metrics are:
• Total - Misses per Sec
This is the total number of L1D cache misses per second.
• NON RSE - Misses per Sec
This is the number of non-RSE L1D cache misses per second.
• RSE - Misses per Sec
This is the number of RSE load L1D cache misses per second.
• Total - Misses per Kinst
This is the total number of L1D cache misses per 1000 retired instructions retired, including
nops, predicated off instructions, and speculative instructions/associated recovery code.
• NON RSE - Misses per Kinst
This is the number of non-RSE L1D cache misses per 1000 retired instructions retired, including
nops, predicated off instructions, and speculative instructions/associated recovery code.
• RSE - L1 Misses per Kinst
This is the number of RSE load L1D cache misses per 1000 retired instructions, including nops,
predicated off instructions, and speculative instructions/associated recovery code.
• All - Inst per L1D Access
This is the ratio of the total number of instructions retired per L1D cache access, including
nops and predicated off instructions.
• NON RSE - Inst per L1D Access
This is the ratio of the total number of instructions retired per non-RSE L1D cache access,
including nops and predicated off instructions.
• RSE - Inst per L1D Access
This is the ratio of the total number of instructions retired per RSE L1D cache access, including
nops and predicated off instructions.
• % Miss - All
This is the percentage of the total number of L1 data cache misses out of the total number of
L1 data cache accesses. Data cache accesses include all integer loads, RSE loads, L1_hinted
loads, and load checks (ld.c). It does not include integer stores, floating-point loads or stores,
VHPT loads, or semaphores.
• %Miss - Non RSE
This is the percentage of the total number of integer loads that miss the L1 data cache out of
the total number of integer loads that referenced the L1 data cache. This cache is not referenced
by integer stores, RSE stores, VHPT loads, or floating-point loads/stores.
• %Miss - RSE
This is the percentage of the total number of RSE load misses out of the total number of RSE
loads. RSE stores do not access this cache, but expect to update an already existing line in
the L1 data cache to ensure proper cache coherence.
l1icache Event Set
The l1icache event set provides information on L1 instruction cache miss rates for both demand
fetches and prefetches.
If you use this event set, the default is to make the measurements irrespective of CPU operating
state (that is, user, system, or interrupt states). By default, the idle state is not included in the
l1icache Event Set 233