HP Caliper 5.3 User Guide (5900-1558, February 2011)

The metrics are:
• Total - Misses Per Second
This is the total number of L2 data cache misses per second. It includes all data load and store
misses.
• Load - Misses Per Second
This is the number of data load requests that miss the L2 cache per second.
• Store - Misses Per Second
This is the number of data store requests that miss the L2 cache per second.
• Writebacks Per Second
This is the total number of L2 data cache writebacks (L3 hit and miss) per second.
• Total - Misses Per Kinst
This is the number of data (load and store) requests that miss the L2 data cache per 1000
retired instructions, including nops and predicated off instructions.
• Load - Misses Per Kinst
This is the number of load operations that miss the L2 data cache per 1000 retired instructions.
Uncache loads and semaphore operations are excluded from this metric.
• Store - Misses Per Kinst
This is the number of store operations that miss the L2 data cache per 1000 retired instructions,
including nops and predicated off instructions. Uncache stores and semaphore operations
are excluded from this metric.
• Writebacks Per Kinst
This is the total number of L2 data cache writebacks (L3 hit and miss) per 1000 retired
instructions, including nops and predicated off instructions.
• Writeback Hits Per Kinst
This is the number of cache line writebacks that hit the L3 cache per 1000 retired instructions,
including nops and predicated off instructions.
• Writeback Misses Per Kinst
This is the number of cache line writebacks that miss the L3 cache per 1000 retired instructions,
including nops and predicated off instructions. Writeback misses are sent directly to memory;
they do not allocate the line in the L3 cache.
• Instr Per Access
This is the ratio of the total number of instructions retired per L2 data cache access, including
nops and predicated off instructions. The L2 data cache accesses include RSE stores, VHPT
loads, all integer and RSE loads that miss the L1 data cache, all integer stores, all floating-point
loads/stores, and semaphore (counted once) operations.
• %Miss
This is the percentage of all the L2 data cache misses out of the total number of L2 data cache
accesses. Accesses include all integer and RSE loads that miss the L1 data cache, all RSE and
integer stores, all floating-point loads/stores, and semaphore (counted once) operations.
l2icache Event Set
The l2icache event set provides miss rate information for the L2 data cache on dual-core Itanium
2 and Itanium 9300 quad-core processor systems. On other Itanium 2 systems, use the l2cache
event set, which provides the miss rate information for the unified L2 cache.
238 Event Set Descriptions for CPU Metrics