HP Caliper 5.3 User Guide (5900-1558, February 2011)

memreq Event Set
Available only on Itanium 9300 quad-core processor systems.
The memreq event set provides data about memory read latency and cacheable and uncacheable
memory requests.
If you use this event set, the default is to make the measurements irrespective of CPU operating
state (that is, user, system, or interrupt states). By default, the idle state is not included in the
measurement. You can use command-line options to limit the scope of the measurement. Specifically,
you can:
• Limit measurement to a specific privilege level: -m event_set[:all|user|kernel]
• Include idle: --exclude-idle False
• Exclude the interruption state: --measure-on-interrupts off
• Only measure the interruption state: --measure-on-interrupts only
Metrics Available from this Measurement
The following metrics are available from this event set. These descriptions do not take into account
any command-line options you might use.
The metrics are:
• Read Rate
Number of memory read requests per second.
• Live Reads
This is the average number of outstanding reads per cycle. This gives some idea about the
memory request density.
• Ave Latency - Cycle
Average system memory read latency in CPU cycles.
• Ave Latency - Nsec
Average system memory read latency in nanoseconds.
• Pftch
This is total number of cacheable instruction prefetch memory requests per 1000 retired
instructions, including nops and predicated off instructions.
• Dmnd
This is total number of cacheable instruction demand fetch memory requests per 1000 retired
instructions, including nops and predicated off instructions.
• Load
This is total number of cacheable loads per 1000 retired instructions, including nops and
predicated off instructions.
• Store
This is total number of cacheable RFO (Read For Ownership) stores per 1000 retired
instructions, including nops and predicated off instructions.
• Hint
This is total number of cacheable RFO (Read For Ownership) hints per 1000 retired instructions,
including nops and predicated off instructions.
• WB - 128
This is total number of cacheable 128-byte write backs per 1000 retired instructions, including
nops and predicated off instructions.
242 Event Set Descriptions for CPU Metrics