HP Caliper 5.3 User Guide (5900-1558, February 2011)

The metrics are:
• TS Per Sec
Number of thread switches each second.
• TS Per Kinst
Number of thread switches every 1000 instructions.
• L3miss
Percentage of all thread switches that were caused by a miss in the Level 3 cache. A large
value indicates a “good” use of HyperThreading: while this process is waiting on memory,
another process can execute.
• Timer
Percentage of all thread switches due to the “fair share” timer. A large value indicates a
“poor” use of HyperThreading: both processes are competing for processor execution cycles.
• Hint
Percentage of all thread switches that were triggered by the “hint@pause” instruction. This is
when the measured process voluntarily gives up the processor because it is about to wait for
something (like a mutex). A non-zero value indicates a “good” use of HyperThreading: this
process has natural “idle” time that another process can make use of.
• Other
Percentage of all other reasons that thread switches occurred.
• 0–3
Percentage of thread switches that were triggered after the processor had stalled for 0 to 3
cycles. A large value indicates efficient HyperThreading.
• 4–15
Percentage of thread switches that were triggered after the processor had stalled for 4 to 15
cycles. A non-zero value represents wasted processor cycles.
• 16–63
Percentage of thread switches that were triggered after the processor had stalled for 16 to
63 cycles. A non-zero value represents wasted processor cycles.
• 64–255
Percentage of thread switches that were triggered after the processor had stalled for 64 to
255 cycles. A non-zero value represents wasted processor cycles.
• >=256
Percentage of thread switches that were triggered after the processor had stalled for 256 or
more cycles. A non-zero value represents wasted processor cycles.
• Overhead Cycles Per Sec
Number of processor cycles per second consumed by the thread switching itself. A large value
indicates that many cycles were lost to the process in overhead.
• Gated Cycles Per Sec
Number of processor cycles per second that a pending thread switch was held up waiting for
some blocking condition to clear.
tlb Event Set
The tlb event set provides information related to translation lookaside buffer (TLB) misses.
250 Event Set Descriptions for CPU Metrics