HP Caliper User Guide Release 5.5 (5900-2351, August 2012)

dcache Metrics Summed for Entire Run
This section describes the metrics summed over the entire run of your application under HP Caliper.
Metrics for Integrity Servers Itanium 2 Systems
L1D_READS The number of data memory read references issued into
memory pipeline that are serviced by the L1 data cache
(only integer loads), register stack engine (RSE) loads,
L1-hinted loads (L1 data cache returns data if it hits in L1
data cache but does not do a fill) and check loads (ld.c).
Non-cacheable reads, virtual hash page table (VHPT) loads,
semaphores, floating-point loads, and lfetch instructions are
not counted here because the L1 data cache does not handle
these. The count includes wrong path operations but
excludes predicated off operations.
L1D_READ_MISSES.ALL Number of L1 data cache read misses. L1 data cache is
write through; therefore, write misses are not counted. The
count only includes misses caused by references counted
by an L1D_READS event. It will include L1 data cache misses
that missed the ALAT, but not those that hit in the ALAT.
Semaphores are not handled by the L1 data cache and are
not included in this count.
DATA_REFERENCES The number of data memory references issued into memory
pipeline. Includes check loads, non-uncacheable accesses,
RSE operations, semaphores, and floating-point memory
references. The count includes wrong path operations but
excludes predicated off operations. This event does not
include VHPT memory references.
L1 Data Cache Miss Percentage Percentage of L1 data cache reads that are misses.
Percent of Data References Accessing
L1 Data Cache
Percentage of data references that access the L1 data cache.
Metrics for Integrity Servers Dual-Core Itanium 2 and Itanium 9300 Quad-Core Processor Systems
BE_EXE_BUBBLE.FRALL Full Pipe Bubbles in Main Pipe due to FR/FR or FR/load
dependency stalls. This is the number of cycles lost (stall
cycles) due to FR/FR or FR/load dependency.
BE_EXE_BUBBLE.GRALL Full Pipe Bubbles in Main Pipe due to GR/GR or GR/load
dependency stalls. This is the number of cycles lost (stall
cycles) due to GR/GR or GR/load dependency.
BE_EXE_BUBBLE.GRGR Full Pipe Bubbles in Main Pipe due to GR/GR dependency
stalls. This is the number of cycles lost (stall cycles) due to
GR/GR dependency.
CPU_OP_CYCLES.ALL Number of elapsed CPU operating cycles.
DATA_REFERENCES The number of data memory references issued into memory
pipeline. Includes check loads, non-uncacheable accesses,
RSE operations, semaphores, and floating-point memory
references. The count includes wrong path operations but
excludes predicated off operations. This event does not
include VHPT memory references.
IA64_INST_RETIRED Number of retired IA-64 instructions. The count includes
predicated on and predicated off instructions and nops, but
excludes hardware-inserted RSE operations.
L1D_READS The number of data memory read references issued into
memory pipeline that are serviced by the L1 data cache
(only integer loads), RSE loads, L1-hinted loads (the L1 data
192 Descriptions of Measurement Reports