HP Caliper User Guide Release 5.5 (5900-2351, August 2012)

cache returns data if it hits in the L1 data cache but does
not do a fill), and check loads (ld.c). Non-cacheable reads,
VHPT loads, semaphores, floating-point loads, and lfetch
instructions are not counted here because the L1 data cache
does not handle these. The count includes wrong path
operations but excludes predicated off operations.
L1D_READ_MISSES.ALL Number of L1 data cache read misses. L1 data cache is
write through; therefore, write misses are not counted. The
count only includes misses caused by references counted
by an L1D_READS event. It will include L1 data cache misses
which missed the ALAT, but not those which hit in the ALAT.
Semaphores are not handled by the L1 data cache and are
not included in this count.
L2D_INSERT_MISSES Number of times a cacheable data request missed in the
L2D cache on its first lookup. This does not include
secondary misses and other misses that were forced to
recirculate.
L2D_MISSES Number of L2 data cache misses (in terms of the number of
L2 data cache line requests sent to L3). It includes all
cacheable data requests. This does not include secondary
misses of the L2D.
L2D_REFERENCES.ALL Number of requests made to L2D due to a data read and/or
write accesses. Semaphore operations are counted as one
read and one write.
% of Cycles lost due to GR/load
dependency stalls (lower is better)
Percentage of cycles lost due GR/load dependency stalls.
% of Cycles lost due to GR/GR
dependency stalls (lower is better)
Percentage of cycles lost due GR/GR dependency stalls.
% of Cycles lost due to FR/load and
FR/FR dependency stalls (lower is
better)
Percentage of cycles lost due to FR/load and FR/FR
dependency stalls
L1 data cache miss percentage Percentage of L1 data cache reads that are misses.
Percent of data references accessing
L1 data cache
Percentage of data references that access the L1 data cache.
L2 data cache miss percentage Percentage of L2 data cache reads that are misses.
L1 data cache misses per 1000
instructions retired
Number of L1 data cache misses per 1000 instruction
retired.
L2 data cache misses per 1000
instructions retired
Number of L2 data cache misses per 1000 instruction
retired.
Instructions retired per L1 data cache
access
Number of instructions retired per L1 data cache access.
Instructions retired per L2 data cache
access
Number of instructions retired per L2 data cache access.
Metrics for Integrity Servers Intel® Itanium® 9500 Processors Systems
CPU_OP_CYCLES.ALL Number of elapsed CPU operating cycles
CYC_BE_BUBBLE.ANY Number of cycles lost (stall cycles) due to replays, flushes,
bubbles, or partial replays.
CYC_BE_IBD_STALL.GR_LOAD This is the number of cycles lost (stall cycles) due to GR load
RAW or WAW dependency condition of the instruction.
CYC_BE_EXE_REPLAY.GR_LOAD_RAW This is the number of cycles lost (stall cycles) in replay due
to RAW hazard in an instruction's GR load.
dcache Measurement Report Description 193