HP Caliper User Guide Release 5.5 (5900-2351, August 2012)

dtlb Metrics Summed for Entire Run
This section describes the metrics summed over the entire run of your application under HP Caliper.
Metrics for Integrity Servers Itanium 2 Systems
DATA_REFERENCES The number of data memory references issued into memory
pipeline. Includes check loads, non-cacheable accesses,
RSE operations, semaphores, and floating-point memory
references. The count includes wrong path operations but
excludes predicated off operations. This event does not
include virtual hash page table (VHPT) memory references.
L2DTLB_MISSES The number of L2 DTLB misses (which is the same as
references to HPW, DTLB_HIT=0) for demand requests.
DTLB_INSERTS_HPW The number of virtual hash page table entries inserted into
DTLB by hardware page walker (HPW).
Total L1 Data TLB References Total number of L1 data TLB references.
Percentage of Data References
Covered by L1 and L2 DTLB
Percentage of data references that was satisfied in L1 DTLB
or L2 DTLB. This is calculated as the following: 100 * (1–
L2DTLB_MISSES / DATA_REFERENCES).
Percentage of Data References
Covered by the HPW
Percentage of data references that were satisfied by the
hardware page walker (HPW). This is calculated as the
following: 100 * (DTLB_INSERTS_HPW /
DATA_REFERENCES).
Percentage of Data References
Covered by Software Trap
Percentage of data references that were serviced by the
software trap handler for the TLB misses fault. This is
calculated as the following: 100 * ((L2DTLB_MISSES -
DTLB_INSERTS_HPW) / DATA_REFERENCES).
Percentage of L2 DTLB Misses
Covered by the HPW
Percentage of L2 DTLB misses that were serviced by the
hardware page walker (HPW). This is calculated as the
following: 100 * (DTLB_INSERTS_HPW / L2DTLB_MISSES).
Metrics for Integrity Servers Dual-Core Itanium 2 and Itanium 9300 Quad-Core Processor Systems
BACK_END_BUBBLE.ALL Number of cycles when the backend of the pipeline was
stalled. This is the number of cycles lost (stall cycles) due to
any of five possible events (FPU/L1D, RSE, EXE,
branch/exception, or the frontend).
BE_EXE_BUBBLE.FRALL Full Pipe Bubbles in Main Pipe due to FR/FR or FR/load
dependency stalls. This is the number of cycles lost (stall
cycles) due to FR/FR or FR/load dependency stalls.
BE_EXE_BUBBLE.GRALL Full Pipe Bubbles in Main Pipe due to GR/GR or GR/load
dependency stalls. This is the number of cycles lost (stall
cycles) due to GR/GR or GR/load dependency.
BE_EXE_BUBBLE.GRGR Full Pipe Bubbles in Main Pipe due to GR/GR dependency
stalls. This is the number of cycles lost (stall cycles) due to
GR/GR dependency stalls.
CPU_OP_CYCLES.ALL Number of elapsed CPU operating cycles.
DATA_REFERENCES The number of data memory references issued into memory
pipeline. Includes check loads, non-cacheable accesses,
RSE operations, semaphores, and floating-point memory
references. The count includes wrong path operations but
excludes predicated off operations. This event does not
include VHPT memory references.
DTLB_INSERTS_HPW Number of virtual hash page table entries inserted into the
DTLB by the hardware page walker (HPW).
200 Descriptions of Measurement Reports