HP Caliper User Guide Release 5.5 (5900-2351, August 2012)

IA64_INST_RETIRED Number of retired IA-64 instructions. The count includes
predicated on and predicated off instructions and nops, but
excludes hardware-inserted RSE operations.
L1DTLB_TRANSFER Number of times an L1 DTLB miss hits in the L2 DTLB for an
access counted in L1D_READS.
L1D_READS The number of data memory read references issued into
memory pipeline that are serviced by the L1 data cache
(only integer loads), RSE loads, L1-hinted loads (the L1 data
cache returns data if it hits in the L1 data cache but does
not do a fill), and check loads (ld.c). Non-cacheable reads,
VHPT loads, semaphores, floating-point loads, and lfetch
instructions are not counted here because the L1 data cache
does not handle these. The count includes wrong path
operations but excludes predicated off operations.
L2DTLB_MISSES The number of L2 DTLB misses (which is the same as
references to HPW, DT LB_HIT=0) for demand requests.
% of Cycles lost due to all stalls
(lower is better)
Percentage of cycles lost due to all stalls.
% of Cycles lost due to GR/load
dependency stalls (lower is better)
Percentage of cycles lost due GR/load dependency stalls.
% of Cycles lost due to GR/GR
dependency stalls (lower is better)
Percentage of cycles lost due GR/GR dependency stalls.
% of Cycles lost due to FR/load and
FR/FR dependency stalls (lower is
better)
Percentage of cycles lost due to FR/load and FR/FR
dependency stalls
Total L1 data TLB references Number of L1 data TLB references.
L1 data TLB for L1D miss percentage Percentage of L1 DTLB accesses that are misses.
L2 data TLB misses Number of L2 data TLB misses.
L2 data TLB miss percentage Percentage of L2 DTLB accesses that are misses.
Percentage of L2 DTLB misses
covered by the HPW
Percentage of L2 DTLB misses that were serviced by the
hardware page walker (HPW).
Percentage of data references
covered by L1 and L2 DTLB
Percentage of data references that was satisfied in L1 DTLB
or L2 DTLB.
Percentage of data references
covered by the HPW:
Percentage of data references that were satisfied by the
hardware page walker (HPW).
Percentage of data references
covered by software trap
Percentage of data references that were serviced by the
software trap handler for the TLB misses fault.
L1 DTLB miss per 1000 instructions
retired
Number of L1 DTLB misses per 1000 instructions retired.
L2 DTLB miss per 1000 instructions
retired
Number of L2 DTLB misses per 1000 instructions retired.
Metrics for Integrity Servers Intel® Itanium® 9500 Processors Systems
FLD_LOAD.ANY Count of any FLD loads.
FLDTLB_LOAD_MISS.ANY Count of any FLDLD operations that miss the FLDTLB.
FLDTLB_INS_REQ.NON_RETIRED Number of DTB transfer request from something other than
a retired instruction.
FLDTLB_INS_REQ.RETIRED Number of DTB transfer request from retired instructions.
DTLB_HPWREQ_BLK_MISS.ANY Number of blocking inst misses DTB, launches HPW request.
DTLB_HPWREQ_SPEC_MISS Number of speculative inst commits and misses the DTB.
dtlb Measurement Report Description 201