HP Caliper User Guide Release 5.5 (5900-2351, August 2012)

L1 instruction cache misses per 1000
instructions retired
Number of instructions retired per L1 instruction cache miss.
L1 instruction prefetch misses per
1000 instructions retired
Number of instructions retired per L1 instruction prefetch
miss.
L1 instruction demand misses per
1000 instructions retired
Number of instructions retired per L1 instruction demand
fetch miss.
L2 instruction cache misses per 1000
instructions retired
Number of instructions retired per L2 instruction cache miss.
L2 instruction prefetch misses per
1000 instructions retired
Number of instructions retired per L2 instruction prefetch
miss.
L2 instruction demand misses per
1000 instructions retired
Number of instructions retired per L2 instruction demand
fetch miss.
Metrics for Integrity Servers Intel® Itanium® 9500 Processors Systems
CPU_OP_CYCLES.ALL Number of elapsed CPU operating cycles.
CYC_BE_IBD_STALL.ANY Number of cycles lost to backend IBD bubbles for any
reason.
FLI_READ.PREF L1 or first level instruction cache (FLI) prefetch requests.
FLI_READ.DMND FLI demand fetch reads.
MLI_READ.ANY_ANY L2 or mid-level instruction cache (MLI) read all: demand or
prefetch.
MLI_READ.ANY_PREF MLI read all prefetch.
MLI_READ.ANY_DMND MLI read all demand.
MLI_READ.MISS_DMND MLI read miss demand.
CYC_BE_BUBBLE.ANY Number of cycles lost to replays, flushes or stalls, including
partial replay cycles.
IA64_INST_RETIRED Number of retired IA-64 instructions. The count includes
predicated on and predicated off instructions and nops, but
excludes hardware-inserted RSE operations.
CYC_BE_IBD_STALL.FEBUB Number of backend bubbles due to FE bubbles - the
instruction fetch engine has not provided anything to issue.
MLI_READ.MISS_ANY MLI read miss: demand or prefetch.
MLI_READ.MISS_PREF MLI read miss prefetch.
CYC_BE_NO_BUBBLE Number of cycles an entire issue group was able to retire.
% of Cycles lost due to all stalls
(lower is better)
Percentage of cycles lost due to all stalls.
Cycles lost due to issue bubbles
(lower is better)
Number of cycles lost due to issue bubbles.
Cycles lost due to frontend bubbles
(lower is better)
Number of cycles lost due to frontend bubbles.
L1 instruction cache references Number of references to FLI cache.
L1 instruction cache misses Number of FLI cache misses.
% L1 instruction cache miss Percentage of FLI cache misses.
% L1 instruction cache prefetch
misses
Percentage of FLI cache prefetch misses.
% L1 instruction cache demand
misses
Percentage of FLI cache demand misses.
L2 instruction cache demand misses Number of MLI cache demand misses.
L2 instruction cache prefetch misses Number of MLI cache prefetch misses.
icache Measurement Report Description 215