User's Manual

microNode Integration Specification DC and AC Characteristics
On-Ramp Wireless, Inc. 6 014-0033-00 Rev. H
a. There are power differences between the Voltage/Current numbers in this table and the
data provided in Figure 4, Figure 5, and Figure 6. These figures show representative
characterization of Power over Voltage/Temperature characterization and are only
representative behavior.
b. The Table 4 refers to a maximal current draw that the Host system should be designed
to accommodate.
2. Measured at:
 microNode1: +20.8 dBm TX output (Typ=50Ω), 3.6V, range includes VSWR ≤ 1.5:1 (Po
not compensated).
 microNode2: +23.3dBm TX output (Typ=50Ω), 3.6V, range includes VSWR ≤ 1.5:1 (Po
not compensated).
3. Sensitivity at maximum spreading factor of 13 (2048) with 10% FER.
4. The upper frequency range is market dependent:
a. FCC/IC: CH38; 2475.63 MHz.
b. ETSI: CH40; 2479.61 MHz.
c. Japan: CH41; 2481.60 MHz.
5. Maximum TX RF power:
 microNode1: This is limited by FCC/IC grant to 20.8 dBm in these markets. Transmit
power is configured during the provisioning process to meet country-specific
deployment and regulatory requirements. The configurable range is 0 – 20.8 dBm.
 microNode2: This is limited by FCC/IC grant to 23.3 dBm in these markets. Transmit
power is configured during the provisioning process to meet country-specific
deployment and regulatory requirements. The configurable range is 0 – 20.8 dBm.
6. Spec and test method comes from FCC 15.247(d); Band Edge Emissions, 2 MHz offset.
7. At any TX power level, VSWR ≤ 3:1. Harmonics fall into FCC restricted bands.
8. Estimated sum of all contributors with VSWR ≤ 1.5:1. Normal link mode.
9. At any TX power level, VSWR ≤ 3:1. Applies to spurious, not ACPR or harmonics. Generally
the largest spurious output outside the 2.40-2.48GHz band is at 2/3LO and 4/3LO.
10. Maximum VSWR for spec compliance applies at 25°C only. Slightly degraded ACPR/mask and
power variation can be expected at temperature extremes.
11. The SPI clock has a maximum rate of 26 MHz/3 and a minimum of 100 kHz. There is no
physical limitation on the minimum clock rate but the 100 kHz is deemed “marginal” and is
not absolute. Depending on the data traffic model and level of debug traffic, 100 kHz may
cause a backup of SPI traffic, which then causes buffer overflow conditions. The application
must be validated to ensure that the SPI clock is sufficient to support required traffic.
2.3 Effects of Temperature and Voltage
The microNode is based largely on Complementary Metal–Oxide–Semiconductor (CMOS)
technology. The current drain of CMOS circuitry can vary substantially over Temperature. The RF
circuitry and its performance also vary substantially over Temperature.
The microNode utilizes two main power domains when it is functioning: