User's Manual

microNode Integration Specification Electrical Interface
On-Ramp Wireless, Inc. 12 014-0033-00 Rev. H
5. VBATT
a. The microNode operating voltage is 2.2V - 5.5V, which drives a buck/boost regulator
(3.3V) internal to the microNode.
b. The internal 3.3V regulator drives the RF and PA circuitry of the microNode which also
drives its operating CMOS I/O voltages.
6. CMOS_I
The Node input voltages are 3.3V CMOS levels. VIH = 2.0V (minimum) and VIL = 0.8V
(maximum).
7. CMOS_O
The Node output voltages are 3.3V CMOS levels (4mA). VOH = 2.4V (minimum) and
VOL = 0.4V (maximum).
8. SPI inputs to the node (SCLK, MOSI, CS) must be tri-stated or driven low when the node may
be sleeping (MRQ and SRQ are both low). See section 4: SPI Interface and Sequences for
more details.
3.1 Signal Descriptions
3.1.1 VBATT
This is the main power to the microNode. This needs a low impedance source to the Host’s
power source. It is recommended that the Host have provision for up to a 100 µF (47 µF nominal)
low ESR capacitor. Use an additional 0.1 µF capacitor to bypass the large bulk capacitor. These
capacitors help shunt high frequency noise (0.1 µF) and aid in smoothing surge currents as the
Node turns itself ON/OFF during normal operations.
3.1.2 POWER_ON
This signal controls the power-on of the LDO circuitry for the microNode. It must be shut off
prior to starting the microNode power-up sequence as defined in section 4.4: Startup (Power
On) Sequence. After the microNode is powered up, this signal is to remain logic high during
normal operational modes.
3.1.3 RESET_N
The microNode has a basic RC Reset circuit that should be cleared during the startup sequence
for the microNode. This signal is an Open Collector/Drain style of signal that can be cleared
(grounded) for Reset and allowed to float when the microNode is operational.
CAUTION: This pin should never be exposed to a voltage greater than 1.8V. Signals greater
than 1.8 V could damage the Node.