User's Manual

On-Ramp Wireless, Inc. 16 014-0033-00 Rev. H
4 SPI Interface and Sequences
4.1 SPI System Interface Overview
The SPI slave interface is currently the only supported interface for Host-to-Node communication.
NOTE: The microNode must be the only SPI slave on the bus.
The SPI slave interface provides communication with an external Host through a 7-wire interface.
The Host is the SPI master and the microNode is the SPI slave. In addition to the four standard SPI
signals, three additional signals are used to complement the SPI bus: MRQ, SRQ, and SRDY. The
additional signals are included to support microNode state transitions and bi-directional message
traffic.
The SPI signals include four that are controlled by the master and three that are controlled by the
slave.
Master-controlled Signals (Host)
 MOSI
 SCLK
 CS
 MRQ
Slave-controlled Signals (microNode)
 MISO
 SRQ
 SRDY
When MRQ and SRQ are low, the remaining Master controlled signals (MOSI, SCLK, and CS) must
be held low or tri-stated. This is to prevent these signals from back-driving the microNode (Slave)
that may be in deep sleep. When either MRQ or SRQ assert high, the Master should set each of
the three signals appropriately according to their standard usage. No pull-up resistors should ever
be applied to any signals on the microNode since it often needs to fall into a Deep Sleep mode (all
internal regulators turned off).