User's Manual
Table Of Contents
- Contents
- 1 Overview
- 2 DC and AC Characteristics
- 3 Electrical Interface
- 4 SPI Interface and Sequences
- 5 Power States
- 6 Messaging Protocol
- 7 microNode Provisioning
- 8 Antenna Diversity
- 9 Regulatory Considerations
- 10 Manufacturing Considerations
- 11 Errata
- Appendix A Abbreviations and Terms
- Appendix B PCB Land Pattern and Vias
- Appendix C REACH AND RoHS Compliance
- Appendix D On-Ramp Wireless RMA Process
- Appendix E microNode Mechanical Drawing
microNode Integration Specification SPI Interface and Sequences
On-Ramp Wireless, Inc. 17 014-0033-00 Rev. H
4.2 SPI Mode and Timing
MOSI
(from master)
1
NSS
(to slave
)
MISO
(from slave)
SPCK
(CPOL = 0)
2 3 4 5 6 7 8
SPCK Cycle
(for reference)
MSB
MSB
LSB
LSB
*
6 5 4 3 2 1
6 5 4 3 2 1
Figure 8. SPI Timing, CPOL = 0, CPHA = 0
4.3 Host Initialization
What is described here is the initialization of the Host, its operating software, and the control
sequences used to drive the microNode.
Due to specific clock and memory requirements, the microNode must go through specific
Initialization and Wake sequences.
NOTE: Some CPUs have internal pull-up resistors that are active after Power On Reset. Through
CMOS leakage, the Host CPU can supply voltages to the microNode I/O bus prior to the
Host CPU fully initializing and disabling the pull-up resistors. It must be noted that during
the brief initialization period, the POWER_ON signal must be “low.” Activating the
POWER_ON signal with other microNode signals being pulled “high” can cause CMOS
latchup within the microNode.
4.4 Startup (Power On) Sequence
During, and immediately after Power On Reset (POR), the Host has no control of its I/O power
states. For instance, some CPUs have GPIO that tri-state or act as inputs during power up. Other
CPU brands have programmable pull-ups on its I/O and need the Host CPU to disable those pull-
ups for the Host’s GPIO to work correctly with the microNode. This setup and configuration of
GPIO takes a finite time during the Host boot process. This is detailed in the following figure.
Whereas the power-up sequence is described here, it is recommended the Integrator not attempt
this entire startup sequence without assistance. On-Ramp Wireless offers a formal and controlled
library to help with this startup and communication interface. For more information, refer to the
rACM Developer Guide (010-0105-00) and the Host Common Software Integration Application
Note (010-0024-00). These documents are described in section 1.3: Referenced Documents.