User's Manual

microNode Integration Specification SPI Interface and Sequences
On-Ramp Wireless, Inc. 19 014-0033-00 Rev. H

t5 After the assertion of t4, the microNode begins its “wake sequence.” The
microNode must boot, initialize its operating system and hardware and when it is
ready for communications it raises its SRDY signal back to the Host. At this point,
communications (Arbitration) can begin.
 t6 At this point the microNode signals its readiness by asserting the SRDY pin. The
Host can now begin communications with the microNode.
4.5 Wake Sequence
The microNode can be awakened in two manners:
 MRQ assertion from the Host. The Host desires communications with the microNode and
awakens the microNode by asserting the MRQ line. This is a Synchronous Wake Sequence.
 The microNode can “self-awaken” due to network events. In this case, a timer internal to the
microNode “pops” and triggers the microNode to “wake.” When the microNode is awake it
asserts its SRDY as a matter of course to indicate to the Host (if it needs to) that it can start
communicating with the microNode while it is awake. This is an Asynchronous Wake
Sequence.
4.5.1 Wake Sequence (Synchronous)
The following sequence demonstrates the timing required of the Host to awaken the microNode
from a sleep state.
Assumptions:
 The microNode has been previously Powered On and Arbitrated.
 The power (VBATT) has remained stable and the microNode has not been Reset (Reset is set
to tri-state/float).
t
0
t
1
t
2
t
3
SRDY
SPI
System
MRQ
Hi-Z
4 ms
(Driven as appropriate)
3 ms
Figure 10. Host-Initiated microNode Wake Sequence – SRDY Low (Synchronous)