User's Manual

microNode Integration Specification SPI Interface and Sequences
On-Ramp Wireless, Inc. 20 014-0033-00 Rev. H
The timing sequence shown in Figure 10 above is described below. NOTE: The timing shown in the
figure is not to scale.
 t0 The Host desires to wake the microNode and asserts MRQ high.
 t0

t1 After MRQ has gone High, the Host’s SPI system and other I/O can be enabled.
Asserting the MRQ has enabled the internal I/O power supply of the microNode
and the Host’s SPI can be enabled 4 ms after the rise of MRQ.
 t1

t2 After the initial assertion of MRQ, the microNode has to internally power up and
initialize its systems. When it is ready to communicate it will assert its SRDY line to
signal it is now ready for SPI interaction. From MRQ assertion until the microNode
is ready, takes about 80 ms.
 t3 The microNode is now ready to communicate with the Host.
4.5.2 Wake Sequence (Asynchronous)
In this scenario, the microNode is already awake due to a networking event (SRDY is already High)
and the Host wants to communicate with the microNode while it is awake. The Host asserts MRQ
to ensure that the microNode stays awake during its communication cycle.
NOTE: The timing shown in the figure is not to scale.
t
0
t
1
t
2
t
3
SRDY
SPI
System
MRQ
Hi-Z
(Driven as appropriate)
< 250 μs
Figure 11. Host-Initiated microNode Wake Sequence – SRDY High (Asynchronous)