User's Manual

microNode Integration Specification Messaging Protocol
On-Ramp Wireless, Inc. 28 014-0033-00 Rev. H
After a successful message request transfer, the Host waits a turn-around delay and then
initiates the transfer with a message header command. The payload immediately follows the
header and, if necessary, is zero padded to match the payload size indicated in the message
request.
After the payload, the Host waits a turn-around delay before proceeding with any other further
messages.
The Host interface SPI bus is a standard SPI bus (with MISO, MOSI, CS, and SCLK) with the
addition of three lines (MRQ, SRQ, and SRDY). These three additional lines are used to provide
the Host with the ability to wake up the Node over the SPI Bus as well as providing the Node
with the ability to prompt the Host to begin a SPI Bus transaction. The Node is also exceptional
in that it must be the only slave present on the SPI Bus, since MOSI, CS, and SCLK must be
undriven (tri-stated) any time that MRQ is low.
Before any message is communicated over the SPI Bus, the MRQ and SRDY lines must be high.
The Host guarantees this by pulling the MRQ line high and waiting for the Node to pull the SRDY
line high. The Host cannot proceed with SPI Bus communication until both of these lines are
high. Once MRQ and SRDY are high, the Host, being SPI Bus master, can continue with a normal
SPI Bus transaction.
When the Node wishes to communicate with the Host, it pulls the SRQ line high. The Host must
have the ability to detect this and start a SPI Bus transaction (by first pulling the MRQ high and
waiting for SRDY to go high). A standard SPI Bus transaction is described and illustrated in Figure
18.
Message exchanges between Host and Node are shown below in Figure 16.