User's Manual
Table Of Contents
- Contents
- 1 Overview
- 2 DC and AC Characteristics
- 3 Electrical Interface
- 4 SPI Interface and Sequences
- 5 Power States
- 6 Messaging Protocol
- 7 microNode Provisioning
- 8 Antenna Diversity
- 9 Regulatory Considerations
- 10 Manufacturing Considerations
- 11 Errata
- Appendix A Abbreviations and Terms
- Appendix B PCB Land Pattern and Vias
- Appendix C REACH AND RoHS Compliance
- Appendix D On-Ramp Wireless RMA Process
- Appendix E microNode Mechanical Drawing
microNode Integration Specification Messaging Protocol
On-Ramp Wireless, Inc. 30 014-0033-00 Rev. H
bubbles indicate a predefined turn-around delay which provides ISR processing time and avoids
race conditions between Host and Node.
6.3 Host Interface SPI Bus State Machine
This section illustrates the sequence of messages that can take place on the Host interface SPI
bus. The design and implementation of the actual state machine on the Host software is up to
the Host software designer. This diagram is provided to demonstrate the message sequence
over the SPI Bus. Note the usage of the turn-around delay, which is required in between each
step of message exchange. This delay is required by the Node and is currently defined as having
a time of 200 µs.
ARBITRATION
NIL
VALIDATION
IDLE
MMSG_REQ
SMSG_REQ
MMSG_PAYLOAD
SMSG_PAYLOAD
A
A
B
B
Turn-around
Delay
A
Turn-around
Delay
Turn-around
Delay
Turn-around
Delay
Turn-around
Delay
B
BOOT
Exchange of Arbitration
Message
Exchange of
Validation Message
Any
Non-Validation
Exchange of MHDR Message Exchange of SHDR Message
Exchange of MMSG
Message
Any
Other SPI Bus
Traffic
Any
Other SPI Bus
Traffic
Exchange of SMSG
Message
Host (Master) Has
Message to Send
SRQ Asserted by
Slave (Node)
Non-Arbitration
Response
Unexpected
SMSG_RSP
Figure 17. Host Interface SPI Bus State Machine