User's Manual

microNode Integration Specification Messaging Protocol
On-Ramp Wireless, Inc. 31 014-0033-00 Rev. H
6.4 SPI Bus Timing Example
This section provides an example illustration of an exchange of messages first from master
(Host) to slave (Node) and then from slave (Node) to master (Host). Each step in the timing
sequence is described below:
SRQ
MRQ
SRDY
CS
SCLK
MISO
MOSI
6
9
5
10
11
1
2
3
4
7
8
Figure 18. SPI Timing Example
Note that MRQ state transitions must respect the timing requirements shown in Chapter 4.
The following items pertain to the numbered bubbles above:
1. Host has a message that it desires to send to Node. The first thing that it does is drive MRQ
and CS high.
2. The Host then waits for the Node to drive SRDY high. No SPI bus transaction with the Node
can occur before this.
3. After SRDY is high, the Host can start with the SPI data transaction. This is accomplished by
driving the Node CS line low and then having the Host toggle the SCLK, and MOSI lines and
having the Node toggle the MISO line according to the data to be transferred. The SPI Host
interface specifies that first a MMsg pair is exchanged.
4. A MHdr pair is exchanged. Note that the payload of the message is appended to the MHdr.
5. The Host detects that the transaction is complete and that it does not wish to send more
messages to the Node at this time. It drives the MRQ line low. Since MRQ is low, CS, SCLK
and MOSI are tri-stated.