User's Manual
Table Of Contents
- Contents
- 1 Overview
- 2 DC and AC Characteristics
- 3 Electrical Interface
- 4 SPI Interface and Sequences
- 5 Power States
- 6 Messaging Protocol
- 7 microNode Provisioning
- 8 Antenna Diversity
- 9 Regulatory Considerations
- 10 Manufacturing Considerations
- 11 Errata
- Appendix A Abbreviations and Terms
- Appendix B PCB Land Pattern and Vias
- Appendix C REACH AND RoHS Compliance
- Appendix D On-Ramp Wireless RMA Process
- Appendix E microNode Mechanical Drawing
microNode Integration Specification Messaging Protocol
On-Ramp Wireless, Inc. 33 014-0033-00 Rev. H
MOSI) are read on the SCLK rising edge and are set or cleared on the SCLK falling edge, and is
commonly referred to as CPOL=0, CPHA=0.
This illustration shows that the bit streams for MISO and MOSI are:
MISO: 0110100111111111
MOSI: 1010100100000100
These bits indicate:
MISO: from slave to master (01)
length of message=2 (10)
opcode=MMsgACK (1001)
buffer size=255 (11111111)
MOSI: from master to slave (10)
length of message=2 (10)
opcode =MMsgREQ (1001)
payload size=4 (00000100)
An MMsg pair or SMsg pair is immediately followed by the corresponding MHdr pair or SHdr
pair. This is illustrated below:
SCLK
MISO
MOSI
. . .
0
1
1
0
1
0
1
0
0
0
1
0
1
0
1
0
1
0
0
0
. . .
. . .
0
1
0
1
0
0
0
0
Figure 20. Host Message on SPI – MHdr Pair
For purpose of brevity, this timing diagram shows only a portion of the data exchange. The
complete bit streams for MISO and MOSI are as follows:
MISO: 01101010000000010000000000000000000000000000000000000000000000000000
000000000000
MOSI: 10101010000000010000100000000000000101010100000011110000111100001010
010110100101
These bits indicate:
MISO: from slave to master (01)
length of message=2 (10)