Intel® 21143 PCI/CardBus 10/ 100Mb/s Ethernet LAN Controller Design Guide July 2002 Order Number: 278588-001
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
Contents Contents 1.0 Functional Overview ........................................................................................................................ 5 1.1 1.2 1.3 1.4 21143 Overview .................................................................................................................... 5 Network Interface.................................................................................................................. 5 MII-Based PHY Block Diagram.................................
Contents 9 AUI 10BASE2 Network Connection............................................................................................ 17 10 21143 External Component Connections ................................................................................... 20 11 LED Time-Stretcher Circuit......................................................................................................... 22 Tables 1 2 3 4 5 6 7 8 9 10 11 12 Signal gep<0>/aui_bnc Description .......................................
Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller This design guide provides a description of how to implement 100BASE-TX and 10BASE-T network connections using the 21143 PCI/CardBus 10/100 Mb/s Ethernet LAN Controller (referred to as the 21143). While this document will not provide specific recommendations for physical layer devices, it will provide design recommendations and layout recommendations.
Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller The 21143 implements the 100BASE-T MII layer and the 100/10 Mb/s Ethernet MAC layer. The 21143 provides a dual network interface for both a 100BASE-T and a 10 Mb/s Ethernet. At the 100BASE-T port, the 21143 supports the industry-standard MII for any 100BASE-T implementation. The 21143 is fully compliant with the MII specifications (as defined in IEEE 802.3).
Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller SYM-based PHY devices are provided by GEC Plessey*, Quality Semiconductor*, and Micro Linear*. Figure 2. SYM-Based PHY Design SYM Port of 21143 SYM-Based PHY Devices Magnetics Module 100 Mb/s Network The SYM-based PHY design includes the following components: • The SYM-based PHY devices, which have a direct interface to the SYM port of the 21143 with an interface to the 100 Mb/s magnetics module.
Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller Table 4. MII Signals Signal Pin Number mii_clsn 118 mii_crs 117 mii_dv 129 mii_mdc 134 mii_mdio 135 mii_rclk 128 mii_rx_err 127 mii_rxd <3:0> 133:130 mii_tclk 124 mii_txd<3:0> 119:122 mii_txen 123 Table 5 lists the active SYM signals when the 21143 SYM port is selected. Table 5.
Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller 3.0 Network Connection The network connections of the 21143 can be used in 10BASE-T, AUI, MII, or SYM configurations. Different methods are used to connect each port to the actual cable connector. 3.1 10BASE-T Twisted-Pair Network Port Figure 3, Figure 4, and Figure 5 show the network connection design options for 10BASE-T type implementations.
Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller Figure 3. 10BASE-T Network Connection with Buffers 21143 74ACT244 tp_td+ 6 8 tp_td++ 7 6 61.9 Ω 12 301 Ω 3 14 Transmit Path TP Filters and Chokes 78Z041 (SMD) 806 Ω tp_td- 5 4 tp_td-- 4 2 61.9 Ω 16 301Ω 1 18 RJ45 8 1 6 2 9 3 11 6 5 GND tp_rd- 9 14 49.9 Ω Receive Path 49.9 Ω tp_rd- 10 16 0.1 µF 0.01 µF GND GND GND LJ-05141.
Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller Figure 4 shows the 10BASE-T network connection without buffers. The required components for this configuration are as follows: • • • • Terminating and decoupling components Transformer module (ratio of 1: 2 for swing compensation) Filter transformer and common-mode chokes RJ45 connector Figure 4.
Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller Figure 5 shows the minimum component requirement for the 10BASE-T network connection. This implementation uses a filter transformer module with a 1: 2 transformer on the transmit path to compensate for the voltage swing. The required components for this configuration are as follows: • Terminating and decoupling components • Filter, transformer, and common-mode chokes • RJ45 connector Figure 5.
Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller Table 6. Internal vs. External Design Features Design Features • Can be designed with an MII or any custom connector. Internal optional daughtercard • User opens cabinet to install 100 Mb/s daughtercard. • User connects module to external MII/SYM connector; user does not have to open cabinet for installation. External MII/SYM module 3.2.
Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller 3.2.3 100-Ready External Module Design Figure 7 shows a block diagram of a 100-Ready design using an external module. Figure 7. 10BASE-T 100-Ready External Module Block Diagram MII or MII or 10/100 Custom Custom PHY Layer Connector Connector MII/SYM 21143 10BASE-T RJ45 Connector Optional AUI Coaxial Transceivers AUI Coaxial Connector RJ45 Connector PCI Bus LJ-05188.AI4 3.2.
Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller Table 7. MII/SYM Pinout (Sheet 2 of 2) Pin Number 3.3 MII Interface Function SYM Interface Function 122 mii_txd<0> sym_txd<0> 123 mii_txen sym_txd<4> 124 mii_tclk sym_tclk 127 mii_rx_err sel10_100 128 mii_rclk mii_rclk 129 mii_dv N.C. 130 mii_rxd<0> sym_rxd<0> 131 mii_rxd<1> sym_rxd<1> 132 mii_rxd<2> sym_rxd<2> 133 mii_rxd<3> sym_rxd<3> 134 mii_mdc N.C. 135 mii_mdio N.C.
Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller Figure 8. AUI 10BASE5 Network and Pin Connections Isolation Transformer ST7032 10 7 21143 aui_rd+ 139 Receive Path 0.01 µ F 40.2 Ω GND 13 0.01 µ F 40.2 Ω 12 18 Ω 16 aui_cd- 138 47 Ω GND aui_td- 143 4 XFRM_CD+ 40.2 Ω GND Transmit Path 8 XFMR_RD- 9 aui_cd+ 137 aui_td+ 142 XFMR_RD+ 40.2 Ω aui_rd- 140 Collision Path AUI Connector 5 XFRM_CD- 1 XFMR_TD+ 2 XFMR_TD- 22 pF 511 Ω 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 40.
Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller Figure 9 shows the AUI 10BASE2 network connection. In this configuration, the AUI is not externally exposed. The required components for this configuration are as follows: • • • • Isolation transformer Terminating and decoupling components DC-to-DC converter Coaxial transceiver and BNC connector Figure 9. AUI 10BASE2 Network Connection Isolation Transformer ST7032 10 7 21143 aui_rd+ 139 0.
Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller 3.4 Media-Specific Components Table 8 lists the media-specific interface components for 10BASE-T access. Table 10 lists the media-specific interface components for 10BASE2 and 10BASE5 access. Table 8.
Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller 4.0 21143 Requirements This section provides information about the external component connections for the 21143, and describes the following requirements: • Unused JTAG port requirements • Current reference and capacitor input • Crystal connection or crystal oscillator connection for the serial clock connection 4.1 Unused JTAG Port Requirements Table 10 describes the 21143 signal pin requirements if you are not using the JTAG port. Table 10.
Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller Figure 10. 21143 External Component Connections Intel® 21143 Ethernet Controller Crystal Connection Crystal Oscillator Connection xtal1 106 xtal2 105 10 kΩ xtal1 xtal2 iref 82 pF 100 Ω 106 20-MHz Input Clock 107 No Connection 120 pF 20-MHz Crystal GND 108 Current Reference Connection 2.4 kΩ GND vcap_h 110 0.022 µF GND B0033-01 4.
Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller 5.0 Signal Routing and Placement The Ethernet circuitry should be kept free of interference from unrelated signal traces. Routing for other signals must be kept away from the space surrounding the grouped Ethernet components. Place the Ethernet circuitry at the perimeter of the board, as close as possible to the network connector. The onchip crystal oscillator requires an external crystal and discrete components.
Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller Intel also recommends that the connector’s shield of the adapter should be connected to the PC chassis. 5.1.1 3.3 V Power Supply The 21143 operates with a power supply of 3.3 V. At least eight decoupling capacitors are recommended and should contain the following values: • • • • 5.2 Three each at 0.1 µF Three each at 0.
Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller 6.0 Design Considerations This section provides information to aid the user in designing Ethernet and Fast Ethernet capabilities onto a motherboard. In addition, it also includes design considerations for FCC compliance. 6.1 Designing the Ethernet Corner on Motherboards This subsection provides a list of routing suggestions and a list of component placement suggestions.
Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller • Engineering Electromagnetic Capability, by V. Prasad Kodali 6.2.2 Suggestions for Routing For routing information, consider the following suggestions: • Never route any etch (power or ground) across a partition or void because the signal loses its return-path integrity and contaminates the isolated plane. • Avoid placing oscillators, phase-locked loops, and other clock-type devices near I/O connectors.
