Intel® 41210 Serial to Parallel PCI Bridge Design Guide May 2005 Order Number: 278801-004
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Contents Contents 1 About This Document ................................................................................................................... 7 1.1 2 Introduction.................................................................................................................................... 9 2.1 2.2 2.3 2.4 2.5 2.6 2.7 3 6.5 General Routing Guidelines................................................................................................25 Crosstalk .........................
Contents 8.6.1 8.6.2 8.6.3 8.6.4 8.6.5 9 Embedded PCI-X 133 MHz ................................................................................... 39 Embedded PCI-X 100 MHz ................................................................................... 40 PCI-X 66 MHz Embedded Topology...................................................................... 41 PCI 66 MHz Embedded Topology ......................................................................... 42 PCI 33 MHz Embedded Mode Topology .....
Contents 22 23 24 25 26 27 PCI 33 MHz Embedded Mode Routing Topology.......................................................................43 PCI Analog Voltage Filter Circuit ................................................................................................50 PCI Express Analog Voltage Filter Circuit ..................................................................................51 Bandgap Analog Voltage Filter Circuit.......................................................................
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1 About This Document This document provides layout information and guidelines for designing platform or add-in board applications with the Intel® 41210 Serial to Parallel PCI Bridge (also called the 41210 Bridge). It is recommended that this document be used as a guideline. Intel recommends employing best-known design practices with board level simulation, signal integrity testing and validation for a robust design.
About This Document Table 1. Terminology and Definitions (Sheet 2 of 2) Term Definition Printed circuit board. Layer 1: copper Prepreg Layer 2: GND Core PCB Layer 3: VCC15 Prepreg Layer 4: copper Example manufacturing process consists of the following steps: • Consists of alternating layers of core and prepreg stacked • The finished PCB is heated and cured.
Introduction 2 The Intel®41210 Serial to Parallel PCI Bridge integrates two PCI Express-to-PCI bridges. Each bridge follows the PCI-to-PCI Bridge programming model. The PCI Express port is compliant to the PCI Express Specification, Revision 1.0. The two PCI bus interfaces are fully compliant to the PCI Local Bus Specification, Revision 2.3. 2.1 PCI Express Interface Features • • • • • • • 2.2 PCI Express Specification, Revision 1.0b compliant.
Introduction • Tunable inbound read prefetch algorithm for PCI MRM/MRL commands • Local initialization via SMBus • Secondary side initialization via Type 0 configuration cycles. 2.3 Power Management • Support for PCI Express Active State Power Management (ASPM) L0s link state • Support for PCI PM 1.1 compatible D0, D3hot and D3cold device power states • Support for PME# event propagation on behalf of PCI devices 2.4 SMBus Interface • Compatible with System Management Bus Specification, Revision 2.
Introduction Figure 1. 41210 Bridge Microcontroller Block Diagram SMBus 2.0 Microcontroller Intelfi 41210 Bridge Configuration Register Data Configuration Register Address Space B2707-01 2.4.2 Microcontroller Connections to the 41210 Bridge The following diagram shows the SMB interface from the 41210 Bridge to the microcontroller. Figure 2. 41210 Bridge Microcontroller Connections 3.
Introduction 2.5 JTAG • Compliant with IEEE Standard Test Access Port and Boundary Scan Architecture 1149.1a 2.6 Related Documents • • • • • • • Intel® 41210 Serial to Parallel PCI Bridge Design Specification (EDS), Revision 1.0. PCI Express Specification, Revision 1.0, from www.pci-sig.com. PCI Express Design Guide, Revision 0.5 PCI Local Bus Specification, Revision 2.3, from www.pci-sig.com. PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a, from www.pci-sig.com.
Introduction 2.7 Intel®41210 Serial to Parallel PCI Bridge Applications This section provides a block diagram for a typical the 41210 Bridge application. This application shows a PCI-E adapter card with two Dual 2Gb Fibre Channel controllers. Each of the PCI-X bus segments is connected to the Dual 2Gb Fibre Channel chip running at 133MHz. The two Dual FC chips provides the four 2Gb/s outputs. Figure 4.
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3 Package Information 3.1 Package Specification The 41210 Bridge is in a 567-ball FCBGA package, 31mm X 31mm in size, with a 1.27mm ball pitch. Figure 5. Top View - 41210 Bridge 567-Ball FCBGA Package Dimensions Handling Exclusion Area 0.550 in. Die Area 21.00 mm 0.550 in. 17.00 mm 31.00 mm 17.00 mm 21.00 mm 31.
Package Information Figure 6. Bottom View - 41210 Bridge 567-Ball FCBGA Package Dimensions AD AC AB AA Y W V 4X 0.635 U T 31.00 – 0.100 R -A- P N M L K J H 4X 15.500 G F E 23X 1.270 D C B + + A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 23X 1.270 8X 14.605 (0.895) 29.2100 31.00 – 0.100 0.
Package Information Figure 7. Side View - 41210 Bridge 567-Ball FCBGA Package Dimensions Detail J Scale 5:1 H 0.74 – 0.025 0.100 – 0.025 FC BGA Substrate Die Solder Bumps Underfill Epoxy Detail H Scale 5:1 Die 1.170 – 0.085 0.600 – 0.100 J 1.940 – 0.
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4 Power Plane Layout This chapter provides details on the decoupling and voltage planes needed to bias the 41210 Bridge package. 4.1 41210 Bridge Decoupling Guidelines Table 2 lists the decoupling guidelines for the 41210 Bridge. Figure 8 and Figure 9 provide the decoupling capacitors around the 41210 Bridge ball grid pins. Figure 8.
Power Plane Layout Figure 9. Decoupling Placement for PCI/PCI-X 1.5V and 3.3V Voltage Planes Capacitor Legend 0603-0.
Power Plane Layout Table 2. 4.2 41210 Bridge Decoupling Guidelines Voltage Plane Voltage 41210 Pins C (uF) Package ESR (mΩ) ESL (nH) # of Caps Location PCI/PCI-X Voltage 3.3V VCC33 0.1 0603 50300 1.03.0 5 Beneath 41210 Bridge BGA PCI/PCI-X Voltage 3.3V VCC33 1.0 0603 50300 1.03.0 2 As close as design rules will allow to 41210 Bridge BGA PCI/PCI-X Voltage 3.3V VCC33 10 1206 50300 1.03.0 3 As close as design rules will allow to 41210 Bridge BGA Core Voltage 1.
Power Plane Layout Note: Linear voltage regulators are recommended when using 1.5 Volt power supplies. Figure 10.
41210 Bridge Reset and Power Timing Considerations 5 This chapter describes the 41210 Bridge reset timing considerations. 5.1 A_RST#,B_RST# and PERST# Timing Requirements The PCI-X Specification requires that there is a 100ms delay from valid power (PERST#) to reset deassertion (A_RST#/B_RST#). 41210 Bridge will keep A_RST#/B_RST# asserted for a minimum of 320ms after PERST# is deasserted. 5.
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General Routing Guidelines 6 This chapter provides some basic routing guidelines for layout and design of a printed circuit board using the 41210 Bridge. The high-speed clocking required when designing with the 41210 Bridge requires special attention to signal integrity. In fact, it is highly recommended that the board design be simulated to determine optimum layout for signal integrity. The information in this chapter provides guidelines to aid the designer with board layout.
General Routing Guidelines Figure 11. Crosstalk Effects on Trace Distance and Height Reduce Crosstalk: P - Maximize P H aggressor victim - Minimize H Reference Plane A9259-01 • Avoid slots in the ground plane. Slots increases mutual inductance thus increasing crosstalk. • Make sure that ground plane surrounding connector pin fields are not completely cleared out.
General Routing Guidelines 6.4 Power Distribution and Decoupling Have ample decoupling to ground, for the power planes, to minimize the effects of the switching currents. Three types of decoupling are: the bulk, the high-frequency ceramic, and the inter-plane capacitors. • Bulk capacitance consist of electrolytic or tantalum capacitors. These capacitors supply large reservoirs of charge, but they are useful only at lower frequencies due to lead inductance effects.
General Routing Guidelines Note: 6.5.1 Using stripline transmission lines may give better results than microstrip. This is due to the difficulty of precisely controlling the dielectric constant of the solder mask, and the difficulty in limiting the plated thickness of microstrip conductors, which can substantially increase cross-talk. Differential Impedance The PCI Express standard defines a 100 Ω differential impedance.
7 Board Layout Guidelines This chapter provides details on adapter card stackup suggestions. It is highly recommended that signal integrity simulations be run to verify each 41210 Bridge PCB layout especially if it deviates from the recommendations listed in these design guidelines. 7.1 Adapter Card Topology The 41210 Bridge will be implemented on PCI-E adapter cards with an eight layer stackup PCB. The specified impedance range for all adapter card implementations will be 60Ω +/-15%.
Board Layout Guidelines NOTE: Each interface will set the trace spacing based on its signal integrity of differential impedance requirements. For the purposes of the building the transmission line models, it is assumed the artwork is very accurate and therefore a constant. Thus, all the variability in the trace spacing is the result of the tolerances of the trace width. Figure 15.
8 PCI-X Layout Guidelines This chapter describes several factors to be considered with a 41210 Bridge PCI/PCI-X design. These include the PCI IDSEL, PCI RCOMP, PCI Interrupts and PCI arbitration. 8.1 Interrupts PCI Express provides interrupt messages that emulate the legacy wired mechanism. This allows IO devices to signal PCI-style interrupts using a pair of ASSERT and DEASSERT messages This message pairing preserves the level-sensitive semantics of the PCI interrupts on PCI Express.
PCI-X Layout Guidelines Note: 8.1.1 PCI Express Assert_INTx/Deassert_INTx messages are not inhibited by the BME bit. Interrupt Routing for Devices Behind a Bridge Given the legacy interrupt sharing scheme shown in Table 4, to get the best legacy interrupt performance (by reducing interrupt sharing), adapter boards have to select the appropriate A_INTX#, B_INTX# (where X is A, B, C or D) input pin to use on each PCI bus segment.
PCI-X Layout Guidelines • Priority group for a master (i.e., whether a master is in low priority group or high priority group). • Bus parking on last PCI agent or the bridge. By default the arbiter parks the bus on the bridge and drives the A/D, C/BE# and PAR lines to a known value while the bus is idle. 8.2.1 PCI Resistor Compensation Figure 16 provides the recommended resistor compensation pin termination for the PCI A and PCI B buses. Figure 16. PCI RCOMP RCOMP 100 Ω – 1% B2718 -01 8.
PCI-X Layout Guidelines Table 6.
PCI-X Layout Guidelines B_CBE#[7:4], B_DEVSEL#, B_FRAME#, B_INTA#, B_INTB#, B_INTC#, B_INTD#, B_IRDY#, B_PERR#, B_PAR, B_GNT#[5:0], B_REQ#[5:0], B_LOCK#, B_PAR64, B_REQ64#, B_SERR#, B_STOP#, and B_TRDY#. 8.4 PCI Clock Layout Guidelines The PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b compliant, allows a maximum of 0.5 ns clock skew timing for each of the PCI-X frequencies: 66 MHz, 100 MHz and 133 MHz.
PCI-X Layout Guidelines Figure 17. PCI Clock Distribution and Matching Requirements 22 9 X0 PCI Device 1 X1 PCI Device 2 X2 PCI Device 3 A_CLKIN A_CLKO0 41210 Bridge A_CLKO1 A_CLKO2 A_CLKO3 22 d 22 9 9 A_CLKO4 A_CLKO6 22 9 22 9 X3 PCI Device 4 22 9 X4 PCI Device 5 PCI Bus a Intel® Notes: – PCI Clock Lengths X0, X1, X2, X3 and X4 should be matched within 0.1 inch of each other. – Minimum separation between two different CLKs, "d".
PCI-X Layout Guidelines Table 8.
PCI-X Layout Guidelines 8.5 PCI-X Topology Layout Guidelines The PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b compliant, recommends the following guidelines for the number of loads for your PCI-X designs. Any deviation from these maximum values requires close attention to layout with regard to loading and trace lengths. Table 9. 8.
PCI-X Layout Guidelines 8.6.1 Embedded PCI-X 133 MHz This section lists the routing recommendations for PCI-X 133 MHz without a slot. Figure 18 shows the block diagram of this topology and Table 10 describes the routing recommendations. Figure 18. Embedded PCI-X 133 MHz Topology TL_EM1 EM1 TL_EM2 TL1 EM2 B2719 -01 Table 10.
PCI-X Layout Guidelines 8.6.2 Embedded PCI-X 100 MHz This section lists the embedded routing recommendations for PCI-X 100 MHz. Figure 19 shows the block diagram of this topology and Table 11 describes the routing recommendations. Figure 19. Embedded PCI-X 100 MHz Topology EM1 TL_EM1 TL1 TL_EM3 EM3 TL_EM2 EM2 B2720 -01 Table 11.
PCI-X Layout Guidelines 8.6.3 PCI-X 66 MHz Embedded Topology Figure 20 and Table 12 provide routing details for a topology with an embedded PCI-X 66 MHz application. PCI-X 66 MHz Embedded Routing Topology TL_EM7 TL_EM8 TL4 TL_EM6 TL3 TL_EM4 TL2 EM7 TL_EM2 TL1 EM5 TL_EM3 EM3 TL_EM1 EM1 TL_EM5 Figure 20. EM2 EM4 EM6 EM8 B2721 -01 Table 12.
PCI-X Layout Guidelines 8.6.4 PCI 66 MHz Embedded Topology Figure 21 and Table 13 provide routing details for a topology with an embedded PCI 66 MHz design. Figure 21. PCI 66 MHz Embedded Topology TL_EM4 TL2 TL_EM2 TL1 TL_EM3 EM3 TL_EM1 EM1 EM2 EM4 B2722 -01 Table 13.
PCI-X Layout Guidelines 8.6.5 PCI 33 MHz Embedded Mode Topology Figure 22 and Table 14 provide routing details for a topology with an embedded PCI 33 MHz design. Figure 22. PCI 33 MHz Embedded Mode Routing Topology TL_EM9 TL_EM10 TL5 TL_EM8 TL4 TL_EM6 TL3 TL_EM4 TL2 EM9 TL_EM7 TL_EM5 EM7 TL_EM2 TL1 EM5 TL_EM3 EM3 TL_EM1 EM1 EM2 EM4 EM6 EM8 EM10 B2723 -01 Table 14.
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PCI Express Layout 9 This section provides an overview of the PCI-Express stackup recommended based on Intel presimulation results. For additional information, refer to the Intel® 41210 Serial to Parallel PCI Bridge Developer’s Manual or the PCI Express Specification, Revision 1.0a from the www.pcisig.com website. 9.1 General recommendations PCI Express is a serial differential low-voltage point-to-point interconnect.
PCI Express Layout 9.2 PCI-Express Layout Guidelines The layout guidelines for PCI-Express were developed for an adapter card topologies. The models and assumptions used in development of these guidelines were as follows: • • • • • • • • • • • Add-In Card Stackup: 60 Ω single-ended impedance Target Differential Impedance: 100 Ω +/- 20%. Driver Model: 41210 Bridge PCI-E IBIS Receiver Model: 41210 Bridge PCI-E IBIS.
PCI Express Layout Table 15. Adapter Card Routing Recommendations (Sheet 2 of 2) Receive Trace Length (Card edge finger to 41210 Bridge receiver pin 1.0” min - 6.0” max Length Matching Requirements: Total allowable intra-pair length mis-match must not exceed 25 mils. Each routing segment should be matched as close as possible. Total skew across all lanes must be less than 20 ns.
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10 Circuit Implementations This chapter describes 41210 Bridge circuit implementations. 10.1 41210 Bridge Analog Voltage Filters The Intel® 41210 Serial to Parallel PCI Bridge requires several external analog voltage filter circuits to be placed on the system board, three for the PCI interface, one for the PCI Express interface, and one for the bandgap voltage.
Circuit Implementations 10.1.1 PCI Analog Voltage Filters The following filter circuit is recommended for the PCI interface. Three separate, identical versions of this circuit should be placed on the system board, one for each VCCAPCI[2:0] pin on the Intel® 41210 Serial to Parallel PCI Bridge. Figure 23.
Circuit Implementations Figure 24. PCI Express Analog Voltage Filter Circuit Board Trace: Trace Width > 25 mils Trace Spacing < 10 mils Trace Length < 600 mils Breakout Trace: Trace Width > 6 mils Trace Spacing < 6 mils Trace Length < 600 mils Board Route Breakout Traces Traces VCC L VCCAPE R C Intelfi 41210 Bridge VSSAPE B2725 -01 Note: . • • • • • • 10.1.3 Place C as close as possible to package pin. R must be placed between VCC15 and L. Route VCCAPE and VSSAPE as differential traces.
Circuit Implementations Figure 25. Bandgap Analog Voltage Filter Circuit Board Trace: Trace Width > 25 mils Trace Spacing < 10 mils Trace Length < 600 mils Breakout Trace: Trace Width > 6 mils Trace Spacing < 6 mils Trace Length < 600 mils Board Route Breakout Traces Traces 2.5 V L VCCBGPE R C VSS Intelfi 41210 Bridge VSSBGPE Note: Ground VSSBGPE at capacitor B2726 -01 Note: . • • • • • • • 52 Place C as close as possible to package pin. R must be placed between the 2.5V supply and L.
Circuit Implementations 10.2 Intel® 41210 Serial to Parallel PCI Bridge Reference and Compensation Pins There are three compensation pins on Intel® 41210 Serial to Parallel PCI Bridge. PE_RCOMP[1:0] are two separate pins that provide voltage compensation for the PCI Express interface on the Intel® 41210 Serial to Parallel PCI Bridge. The nominal compensation voltage is 0.5V. An external 24.9Ω ±1% pullup resistor should be used to connect to VCC15.
Circuit Implementations 10.2.1 SM Bus The SMBus interface does not have configuration registers. The SMBus address is set by the states of pins SMBUS[5] and SMBUS [3:1] when PERST# is asserted as described in Table 17. Table 17. SMBUs Address Configuration Bit Value 7 1 6 1 5 SMBUS[5] 4 0 3 SMBUS[3] 2 SMBUS[2] 1 SMBUS[1] Refer to Section 2.4 for details on how to use the SMBus to initialize 41210 Bridge registers with a microcontroller.
41210 Bridge Customer Reference Boards 11 This chapter describes the 41210 Bridge Customer Reference Board (CRB). 11.1 Board Stack-up The proposed layout of the PCB is eight layers with the following stackup: • • • • • • • • Signal #1 (Top/Component Side) Ground Plane: GND Signal #2 Power Plane Power Plane Signal #3 Ground Plane Signal #4 (Bottom) The permittivity constant Er = 4.
41210 Bridge Customer Reference Boards Table 18. CRB Board Stackup Layer Type Thickness (mils) Copper Weight 1 Signal 2.00 1/2 + plating Prepreg 4.50 2 Plane: GND 1.20 Core 4.80 3 Signal 1.20 Prepreg 14.00 4 Plane: PWR 1.20 Core 3.8 Plane: PWR 1.20 Prepreg 14.00 Signal 1.20 Core 4.80 Plane: Power 1.20 5 6 7 8 Est. Total Thickness 11.2 Prepreg 4.50 Signal 2.
41210 Bridge Customer Reference Boards 11.4 Board Outline Figure 27 provides the mechanical outline of the 41210 Bridge CRB. Figure 27.
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12 Design Guide Checklist This checklist highlights design considerations that should be reviewed prior to manufacturing an adapter card that implements the 41210 Bridge product. The items contained within this checklist attempt to address important connections to these devices and any critical supporting circuitry. This is not a complete list and does not guarantee that a design will function properly. Table 19.
Design Guide Checklist Table 20. PCI/PCI-X Interface Signals Signals Recommendations Reason/Impact X_AD[63:32] X_CBE[7:4]# X_DEVSEL# X_FRAME# X_IRDY# X_TRDY# 41210 Bridge has internal pullup resistors on these signals. X_STOP# X_PERR# X_SERR# No external pullup resistors required on system board. X_REQ[5:0]# X_AD[31:0] and X_CBE#[3:0] signals do not require pullups according to the PCI Specification.
Design Guide Checklist Table 20. PCI/PCI-X Interface Signals Signals Recommendations Reason/Impact Controls frequency of the PCI segment when running in conventional PCI mode (33 MHz or 66 MHz): 0 = 33 MHz PCI 1 = 66 MHz PCI A_M66EN B_M66EN • Pull-up using a 8.2KΩ resistor when the PCI bus is to operate at 66 MHz and not already pulled up by system board. This signal is grounded for 33 MHz operation. Sampled on the rising edge of PERST#. • Connect M66EN to a 0.01 µF capacitor located with-in 0.
Design Guide Checklist Table 21. Miscellaneous Signals Signals RSTIN# Recommendations Reason/Impact Used for debug purposes. Connect to VCC33 through an 8.2KΩ pullup resistor for normal operation. A_STRAP0, A_STRAP1, A_STRAP2, A_STRAP6, B_STRAP0, B_STRAP1, B_STRAP2, B_STRAP6 These signals REQUIRE external pull-downs to GND on the board 8.2KΩ unless otherwise stated. RESERVED [8:1] Input pin to configure 41210 to retry configuration accesses on it's PCI Express interface.
Design Guide Checklist Table 23. Power and Ground Signals Signal Recommendations Reason/Impact 100Ω ±1% (1/4 W) pulldown resistor to ground. Analog compensation pin for PCI. 0.75V nominal. RCOMP The trace impedance of this signal should be < 0.1Ω. Connect to 1.5V power supply. Note: Linear voltage regulators are recommended when using 1.5 Volt power supplies. Decoupling: VCC15 5 0.1uF caps beneath package (backside of board) 1.5V ±5% core voltage. 2 1.
Design Guide Checklist Table 24. JTAG Signals Signal 64 Recommendations Reason/Impact TCK If not used for JTAG, leave as No Connect Internal pull-up TDI If not used for JTAG, leave as No Connect Internal pull-up TDO If not used for JTAG, leave as No Connect Internal pull-up TMS If not used for JTAG, leave as No Connect Internal pull-up TRST# Connect to ground via a 1KΩ pulldown resistor. If TAP interface is not used this should be tied to ground.
