R Voltage Regulator-Down (VRD) 10.
R INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
R Contents 1 Introduction ......................................................................................................................... 7 1.1 2 Processor Voltage Requirements ....................................................................................... 9 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 3 Over-Voltage Protection (OVP) (PROPOSED) ................................................... 25 Over-Current Protection (OCP) (PROPOSED)..................................................
R Figures Figure 1. Intel® Pentium® 4 processor Extreme Edition Supporting Hyper-Threading Technology Vcc Load Line at Processor Socket Represented as Deviation From VID. 10 Figure 2: VRD Phase Orientation ..................................................................................... 11 Figure 3. Power-on Sequence Block Diagram ................................................................. 15 Figure 4. Power Sequence Timing Diagram..................................................................
R Revision History Revision Number -001 Description • Initial Release.
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R 1 Introduction This document defines DC-to-DC converters to meet the power requirements of desktop computer systems using Intel® Pentium® 4 processor Extreme Edition supporting HyperThreading Technology1 in socket 478. Requirements vary according to the needs of different computer systems and processors that a specific voltage regulator is expected to support. The voltage regulator-down (VRD) designation in this document refers to a voltage regulator embedded on a motherboard, for a single processor.
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R 2 Processor Voltage Requirements 2.1 Voltage and Current (REQUIRED) A six-bit VID code supplied by the processor to the VRD determines a reference output voltage, as described in Section 3.2. The load lines in Section 2.2 show the relationship between Vcc and Icc for the processor, and the tolerances between Vcc-minimum and Vcc-maximum. Intel performs exhaustive testing against multiple software applications and software test vectors to identify valid processor Vcc operating ranges.
R Figure 1. Intel® Pentium® 4 processor Extreme Edition Supporting Hyper-Threading Technology Vcc Load Line at Processor Socket Represented as Deviation From VID. 0A 15 A 30 A 45 A 60 A 75 A 90 A 0.00 V Vcc (Deviation From VID) -0.02 V -0.04 V -0.06 V -0.08 V -0.10 V -0.12 V -0.14 V -0.16 V -0.18 V Icc Vcc Max Table 2. Vcc Typ Vcc Min Intel® Pentium® 4 processor Extreme Edition Supporting Hyper-Threading Technology Vcc Load Line at Processor Socket Represented as Deviation From VID.
R Figure 2: VRD Phase Orientation PHASES CAVITY West SOCKET Layout with north phase placement 2.3 Reference Node North East South CAVITY SOCKET Layout with east phase placement TOB: Voltage Tolerance Band (REQUIRED) Processor load line specifications must be guaranteed across component process variation, system temperature extremes, and age degradation limits.
R Peak ripple must not exceed +/-5mV at the VRD measurement nodes. Ripple is typically suppressed by increasing the value of the output inductance or by increasing the value/quantity of ceramic capacitors in the high frequency filter (see 2.9).
R 2.3.2.1 Inductor RDC Current Sense TOB Calculations Inductor sensing is the best general approach to satisfying the tolerance band requirements. TOB can be directly controlled by selecting output inductors and integrating capacitors of sufficient tolerance. Inductor thermal drift will require thermal compensation to keep the load line linear (see 2.4). Capacitor thermal drift must also be considered in the tolerance and Intel recommends COG capacitors for their thermal stability.
R 2.3.2.3 FET RDS-ON Current Sense TOB Calculations Current can be determined by sensing the voltage across the VRD switching FET’s drain to source ‘on’ resistance. While this provides a direct method of voltage to current conversion, the standard FET RDS-ON tolerance of ~20% is not acceptable to satisfy the Pentium 4 processor Extreme Edition supporting Hyper-Threading Technology tolerance band requirements. If RDSON sensing is to be applied, FET thermal compensation is required (see section 2.
R 2.5 Electrical & Thermal Current Support (EXPECTED) System boards supporting Pentium 4 processor Extreme Edition supporting Hyper-Threading Technology should have voltage regulator designs compliant to the FMB parameters defined in Table 1.
R Figure 4. Power Sequence Timing Diagram VccVID 1ms min 10 ms max VIDPWRGD VID[5:0] VID Invalid Vcc VID Valid VID Invalid 0 ms min 10 ms max Vcc_PWRGD NOTES: 1. VccVID comes up at the application of system power to the VccVID VRD. 2. VccVID VRD generates VID_PWRGD, to latch the processor’s VID outputs and enable Vcc VRD, after the VccVID supply is valid. 3. Vcc_PWRGD is generated by the Vcc VRD and may be used elsewhere in the system. 2.
R Figure 5. Example Socket Vcc Overshoot Waveform Maximum Voltage Rule: VOS = 1.570 Example Overshoot Waveform VID = 1.550 VOS-MAX = 50 mV 1.580 VID + VOS-MAX = 1.600 V Voltage 1.570 VOS < VID + VOS-MAX 1.560 Maximum voltage criteria 1.550 satisfied 1.540 1.530 Settling Time Rule: 1.520 Initial VID crossing: 0.5 µs Final VID crossing: 16.5 µs 1.510 TOS = 16.5 µs - 0.5 µs = 16 µs 1.500 TOS = Final VID crossing–Initial VID crossing 1.490 0.0E+00 5.0E-06 1.0E-05 1.
R 2.9 Desktop VRD Output Filter (REQUIRED) Processor voltage regulators include an output filter to minimize transient noise on the Vcc rail. Design analysis determined that the most cost efficient filter solution, for satisfying load line requirements, incorporates 680 µF aluminum-poly capacitors with 5mOhm average ESR. High frequency noise and ripple suppression is best minimized by 22 µF multi-layer ceramic capacitors (MLCC’s).
R 3 Control Inputs 3.1 Output Enable (REQUIRED) The VRD should accept an input signal to enable the output. When disabled, the VRD output should be in a high-impedance state and should not source current. Once the VRD is operating after power-up, it should respond to a de-asserted Output Enable by turning off its output within 500 ms.
R Table 5. VID Specifications Design Parameter Pull-Up Voltage Range Pull-Up Resistor 1 2 VIH VIL Specification Minimum Maximum Units 3.135 3.465 Volts 950 1050 Ohms 0.8 2 Processor leakage current, for pull-up to > 2.5V) 100 Volts 0.4 Volts 200 Microamperes NOTES: 1. Range includes tolerances. Pull-up resistors should not be integrated into the PWM controller (values may be adjusted on the system board for signal integrity). 2.
R Table 6. Voltage Identification (VID) Processor Pins (0 = low, 1 = high) 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0.8375 0.8500 0.8625 0.8750 0.8875 0.9000 0.9125 0.9250 0.9375 0.9500 0.9625 0.9750 0.9875 1.0000 1.0125 1.0250 1.0375 1.0500 1.0625 1.0750 1.0875 OFF1 OFF1 1.1000 1.1125 1.1250 1.1375 1.1500 1.1625 1.1750 1.1875 1.
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R 4 Input Voltage and Current 4.1 Input Voltages (EXPECTED) The main power source for the VRD is 12 volts ±15%. This voltage is supplied by an AC DC power supply through a cable to the motherboard. For input voltages outside the normal operating range, the VRD should either operate properly or shut down. 4.
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R 5 Output Protection These are features built into the VRD to prevent damage to itself, the processor, or other system components. 5.1 Over-Voltage Protection (OVP) (PROPOSED) An OVP circuit should monitor the output for an over-voltage condition. If the output is more than 200mV above the maximum VID level, the VRD should shut off the Vcc supply to the processor. 5.
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R 6 Output Indicators 6.1 Processor Power Good Output (Vcc_PWRGD) (PROPOSED) The VRD should provide a power-good signal, which remains in the low state until a maximum of 10 milliseconds after the output voltage reaches the range specified in Section 2.2. The signal should then remain asserted when the VRD is operating, except for fault or shutdown conditions. Vcc_PWRGD must not be de-asserted during the Dynamic VID operation. Table 7. Power Good Specifications Design Parameter 6.
R Figure 6. Example VRD Thermal Monitor Circuit Design Vtt Vcc(5) R3 1kΩ Vcc(5) R1 1kΩ 680Ω + - LM393 R2 499Ω Rpu 130Ω PROCHOT# Q1 3904 130Ω 7.5kΩ Rtc 6.8k 0.1uF THMSTR Note: Where R2 = R1/R3 * Rtc. Thermister is NTHS0603N02N6801JR or equivalent. Where Rtc represents the thermister resistance at maximum allowable temperature.
R PROCHOT# is an open-drain, active-low i/o buffer terminated to the system Vtt (FSB termination voltage). To maintain reliable signaling between thermal monitor circuit, processor, and chipset, the bipolar transistor must be selected to operate with a collector bias established using a single, 130 Ω pull-up resistor. Use of additional termination or pull-up resistors may lead to signal integrity or logic threshold failures.
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R 7 VccVID Voltage 7.1 VccVID Voltage (PROPOSED) This section is included for reference: Intel does not recommend integration with the processor Vcc PWM controller. The VccVID output powers the processor VID outputs. This rail must come up and assert an active-high VID_PWRGD output according to the timing specified in Figure 7 and Table 9. There is no enable function for the VccVID regulator controller Figure 7. VID PWRGD Timing VccVID 90% Vt td1 90% VID PWRGD 10% Vol td2 tr Table 9.
