Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

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Intel® 64 and IA-32 Architectures

Software Developer’s Manual

Volume 2B:

Instruction Set Reference, N-Z

NOTE: The Intel 64 and IA-32 Architectures Software Developer's Manual

consists of five volumes: Basic Architecture, Order Number 253665;

Instruction Set Reference A-M, Order Number 253666; Instruction Set

Reference N-Z, Order Number 253667; System Programming Guide,

Part 1, Order Number 253668; System Programming Guide, Part 2,

Order Number 253669. Refer to all five volumes when evaluating your

design needs.

Order Number: 253667-021

September 2006

Summary of content (612 pages)

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Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B: Instruction Set Reference, N-Z NOTE: The Intel 64 and IA-32 Architectures Software Developer's Manual consists of five volumes: Basic Architecture, Order Number 253665; Instruction Set Reference A-M, Order Number 253666; Instruction Set Reference N-Z, Order Number 253667; System Programming Guide, Part 1, Order Number 253668; System Programming Guide, Part 2, Order Number 253669.
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
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CHAPTER 4 INSTRUCTION SET REFERENCE, N-Z 4.1 INSTRUCTIONS (N-Z) Chapter 4 continues an alphabetical discussion of Intel® 64 and IA-32 instructions (N-Z). See also: Chapter 3, “Instruction Set Reference, A-M,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A. Vol.
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INSTRUCTION SET REFERENCE, N-Z NEG—Two's Complement Negation Opcode F6 /3 Instruction NEG r/m8 64-Bit Mode Valid Compat/ Leg Mode Valid REX + F6 /3 NEG r/m8* Valid N.E. F7 /3 NEG r/m16 Valid Valid F7 /3 NEG r/m32 Valid Valid REX.W + F7 /3 NEG r/m64 Valid N.E. Description Two's complement negate r/m8. Two's complement negate r/m8. Two's complement negate r/m16. Two's complement negate r/m32. Two's complement negate r/m64.
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INSTRUCTION SET REFERENCE, N-Z Protected Mode Exceptions #GP(0) If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, N-Z NOP—No Operation Opcode 90 0F 1F /0 0F 1F /0 Instructio n NOP NOP r/m16 NOP r/m32 64-Bit Mode Valid Valid Compat/ Leg Mode Valid Valid Valid Description One byte no-operation instruction. Multi-byte no-operation instruction. Valid Multi-byte no-operation instruction. Description This instruction performs no operation. It is a one-byte or multi-byte NOP that takes up space in the instruction stream but does not impact machine context, except for the EIP register.
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INSTRUCTION SET REFERENCE, N-Z Table 4-1. Recommended Multi-Byte Sequence of NOP Instruction (Contd.) Length Assembly Byte Sequence 7 bytes NOP DWORD ptr [EAX + 00000000H] 0F 1F 80 00 00 00 00H 8 bytes NOP DWORD ptr [EAX + EAX*1 + 00000000H] 0F 1F 84 00 00 00 00 00H 9 bytes 66 NOP DWORD ptr [EAX + EAX*1 + 00000000H] 66 0F 1F 84 00 00 00 00 00H Flags Affected None. Exceptions (All Operating Modes) None. Vol.
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INSTRUCTION SET REFERENCE, N-Z NOT—One's Complement Negation Instructio 64-Bit Compat/ Opcode n Mode Leg Mode Description F6 /2 NOT r/m8 Valid Valid Reverse each bit of r/m8. REX + F6 /2 NOT r/m8* Valid N.E. Reverse each bit of r/m8. F7 /2 NOT r/m16 Valid Valid Reverse each bit of r/m16. F7 /2 NOT r/m32 Valid Valid Reverse each bit of r/m32. REX.W + F7 NOT r/m64 Valid N.E. Reverse each bit of r/m64.
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INSTRUCTION SET REFERENCE, N-Z #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
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INSTRUCTION SET REFERENCE, N-Z OR—Logical Inclusive OR Opcode 0C ib 0D iw 0D id REX.W + 0D id Instruction OR AL, imm8 OR AX, imm16 OR EAX, imm32 OR RAX, imm32 64-Bit Mode Valid Valid Valid Valid Compat/ Leg Mode Valid Valid Valid N.E. 80 /1 ib REX + 80 /1 ib 81 /1 iw 81 /1 id REX.W + 81 /1 id OR r/m8, imm8 OR r/m8*, imm8 OR r/m16, imm16 OR r/m32, imm32 OR r/m64, imm32 Valid Valid Valid Valid Valid Valid N.E. Valid Valid N.E.
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INSTRUCTION SET REFERENCE, N-Z set to 0 if both corresponding bits of the first and second operands are 0; otherwise, each bit is set to 1. This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically. In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits.
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INSTRUCTION SET REFERENCE, N-Z #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same as for protected mode exceptions. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, N-Z ORPD—Bitwise Logical OR of Double-Precision Floating-Point Values Opcode 66 0F 56 /r Instruction ORPD xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Bitwise OR of xmm2/m128 and xmm1. Description Performs a bitwise logical OR of the two packed double-precision floating-point values from the source operand (second operand) and the destination operand (first operand), and stores the result in the destination operand.
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INSTRUCTION SET REFERENCE, N-Z Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault.
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INSTRUCTION SET REFERENCE, N-Z ORPS—Bitwise Logical OR of Single-Precision Floating-Point Values Opcode 0F 56 /r Instruction ORPS xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Bitwise OR of xmm2/m128 and xmm1. Description Performs a bitwise logical OR of the four packed single-precision floating-point values from the source operand (second operand) and the destination operand (first operand), and stores the result in the destination operand.
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INSTRUCTION SET REFERENCE, N-Z Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault.
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INSTRUCTION SET REFERENCE, N-Z OUT—Output to Port Opcode* E6 ib Instruction OUT imm8, AL 64-Bit Mode Valid Compat/ Leg Mode Valid E7 ib OUT imm8, AX Valid Valid E7 ib OUT imm8, EAX Valid Valid EE OUT DX, AL Valid Valid EF OUT DX, AX Valid Valid EF OUT DX, EAX Valid Valid Description Output byte in AL to I/O port address imm8. Output word in AX to I/O port address imm8. Output doubleword in EAX to I/O port address imm8. Output byte in AL to I/O port address in DX.
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INSTRUCTION SET REFERENCE, N-Z executed until the EWBE# pin is sampled active.) Only the Pentium processor family has the EWBE# pin.
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INSTRUCTION SET REFERENCE, N-Z OUTS/OUTSB/OUTSW/OUTSD—Output String to Port Opcode* 6E Instruction OUTS DX, m8 64-Bit Mode Valid Compat/ Leg Mode Valid 6F OUTS DX, m16 Valid Valid 6F OUTS DX, m32 Valid Valid 6E OUTSB Valid Valid 6F OUTSW Valid Valid 6F OUTSD Valid Valid Description Output byte from memory location specified in DS:(E)SI or RSI to I/O port specified in DX**. Output word from memory location specified in DS:(E)SI or RSI to I/O port specified in DX**.
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INSTRUCTION SET REFERENCE, N-Z At the assembly-code level, two forms of this instruction are allowed: the “explicitoperands” form and the “no-operands” form. The explicit-operands form (specified with the OUTS mnemonic) allows the source and destination operands to be specified explicitly. Here, the source operand should be a symbol that indicates the size of the I/O port and the source address, and the destination operand must be DX.
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INSTRUCTION SET REFERENCE, N-Z Operation IF ((PE = 1) and ((CPL > IOPL) or (VM = 1))) THEN (* Protected mode with CPL > IOPL or virtual-8086 mode *) IF (Any I/O Permission Bit for I/O port being accessed = 1) THEN (* I/O operation is not allowed *) #GP(0); ELSE (* I/O operation is allowed *) DEST ← SRC; (* Writes to I/O port *) FI; ELSE (Real Mode or Protected Mode or 64-Bit Mode with CPL ≤ IOPL *) DEST ← SRC; (* Writes to I/O port *) FI; Byte transfer: IF 64-bit mode Then IF 64-Bit Address Size THEN IF DF
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INSTRUCTION SET REFERENCE, N-Z ELSE (* 32-Bit Address Size *) IF DF = 0 THEN ESI ← ESI + 2; ELSE ESI ← ESI – 2; FI; FI; ELSE IF DF = 0 THEN (E)SI ← (E)SI + 2; ELSE (E)SI ← (E)SI – 2; FI; FI; Doubleword transfer: IF 64-bit mode Then IF 64-Bit Address Size THEN IF DF = 0 THEN RSI ← RSI RSI + 4; ELSE RSI ← RSI or – 4; FI; ELSE (* 32-Bit Address Size *) IF DF = 0 THEN ESI ← ESI + 4; ELSE ESI ← ESI – 4; FI; FI; ELSE IF DF = 0 THEN (E)SI ← (E)SI + 4; ELSE (E)SI ← (E)SI – 4; FI; FI; Flags Affected None.
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INSTRUCTION SET REFERENCE, N-Z If a memory operand effective address is outside the limit of the CS, DS, ES, FS, or GS segment. If the segment register contains a NULL segment selector. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
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INSTRUCTION SET REFERENCE, N-Z PABSB/PABSW/PABSD — Packed Absolute Value 64-Bit Mode Valid Compat/ Leg Mode Valid PABSB xmm1, xmm2/m128 Valid Valid 0F 38 1D /r PABSW mm1, mm2/m64 Valid Valid 66 0F 38 1D /r PABSW xmm1, xmm2/m128 Valid Valid 0F 38 1E /r PABSD mm1, mm2/m64 Valid Valid 66 0F 38 1E /r PABSD xmm1, xmm2/m128 Valid Valid Opcode 0F 38 1C /r Instruction PABSB mm1, mm2/m64 66 0F 38 1C /r Description Compute the absolute value of bytes in mm2/m64 and store UNSIGNED result in mm
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INSTRUCTION SET REFERENCE, N-Z PABSB with 128 bit operands: Unsigned DEST[7..0] <- ABS(SRC[7..0]) Repeat operation for 2nd through 15th bytes Unsigned DEST[127..120] <- ABS(SRC[127..120]) PABSW with 64 bit operands: Unsigned DEST[15..0] <- ABS(SRC[15..0]) Repeat operation for 2nd through 3rd 16-bit words Unsigned DEST[63..48] <- ABS(SRC[63..48]) PABSW with 128 bit operands: Unsigned DEST[15..0] <- ABS(SRC[15..0]) Repeat operation for 2nd through 7th 16-bit words Unsigned DEST[127..112] <- ABS(SRC[127..
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INSTRUCTION SET REFERENCE, N-Z If CPUID.SSSE3(ECX bit 9) = 0. #NM If TS bit in CR0 is set. #MF (64-bit operations only) If there is a pending x87 FPU exception. #AC(0) (64-bit operations only) If alignment checking is enabled and unaligned memory reference is made while the current privilege level is 3. Real Mode Exceptions #GP(0): If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.
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INSTRUCTION SET REFERENCE, N-Z #PF(fault-code) If a page fault occurs. #AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol.
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INSTRUCTION SET REFERENCE, N-Z PACKSSWB/PACKSSDW—Pack with Signed Saturation 64-Bit Mode Valid Compat/ Leg Mode Valid PACKSSWB xmm1, xmm2/m128 Valid Valid 0F 6B /r PACKSSDW mm1, mm2/m64 Valid Valid 66 0F 6B /r PACKSSDW xmm1, xmm2/m128 Valid Valid Opcode 0F 63 /r Instruction PACKSSWB mm1, mm2/m64 66 0F 63 /r Description Converts 4 packed signed word integers from mm1 and from mm2/m64 into 8 packed signed byte integers in mm1 using signed saturation.
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INSTRUCTION SET REFERENCE, N-Z nation operand. If a signed word integer value is beyond the range of a signed byte integer (that is, greater than 7FH for a positive integer or greater than 80H for a negative integer), the saturated signed byte integer value of 7FH or 80H, respectively, is stored in the destination.
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INSTRUCTION SET REFERENCE, N-Z DEST[55:48] ← SaturateSignedWordToSignedByte (DEST[111:96]); DEST[63:56] ← SaturateSignedWordToSignedByte (DEST[127:112]); DEST[71:64] ← SaturateSignedWordToSignedByte (SRC[15:0]); DEST[79:72] ← SaturateSignedWordToSignedByte (SRC[31:16]); DEST[87:80] ← SaturateSignedWordToSignedByte (SRC[47:32]); DEST[95:88] ← SaturateSignedWordToSignedByte (SRC[63:48]); DEST[103:96] ← SaturateSignedWordToSignedByte (SRC[79:64]); DEST[111:104] ← SaturateSignedWordToSignedByte (SRC[95:80]); D
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INSTRUCTION SET REFERENCE, N-Z #AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP(0) (128-bit operations only) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside of the effective address space from 0 to FFFFH. #UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. #NM If CR0.
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INSTRUCTION SET REFERENCE, N-Z PACKUSWB—Pack with Unsigned Saturation Opcode 0F 67 /r Instruction PACKUSWB mm, mm/m64 66 0F 67 /r PACKUSWB xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Description Converts 4 signed word integers from mm and 4 signed word integers from mm/m64 into 8 unsigned byte integers in mm using unsigned saturation.
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INSTRUCTION SET REFERENCE, N-Z PACKUSWB instruction with 128-bit operands: DEST[7:0] ← SaturateSignedWordToUnsignedByte (DEST[15:0]); DEST[15:8] ← SaturateSignedWordToUnsignedByte (DEST[31:16]); DEST[23:16] ← SaturateSignedWordToUnsignedByte (DEST[47:32]); DEST[31:24] ← SaturateSignedWordToUnsignedByte (DEST[63:48]); DEST[39:32] ← SaturateSignedWordToUnsignedByte (DEST[79:64]); DEST[47:40] ← SaturateSignedWordToUnsignedByte (DEST[95:80]); DEST[55:48] ← SaturateSignedWordToUnsignedByte (DEST[111:96]); DEST[
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INSTRUCTION SET REFERENCE, N-Z Real-Address Mode Exceptions #GP(0) (128-bit operations only) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside of the effective address space from 0 to FFFFH. #UD If CR0.EM[bit 2] = 1. 128-bit operations will generate #UD only if CR4.OSFXSR[bit 9] = 0.
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INSTRUCTION SET REFERENCE, N-Z PADDB/PADDW/PADDD—Add Packed Integers Opcode 0F FC /r 66 0F FC /r 0F FD /r 66 0F FD /r 0F FE /r 66 0F FE /r Instruction PADDB mm, mm/m64 PADDB xmm1, xmm2/m128 PADDW mm, mm/m64 PADDW xmm1, xmm2/m128 PADDD mm, mm/m64 PADDD xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Description Add packed byte integers from mm/m64 and mm. Add packed byte integers from xmm2/m128 and xmm1.
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INSTRUCTION SET REFERENCE, N-Z undetected overflow conditions, software must control the ranges of values operated on. In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).
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INSTRUCTION SET REFERENCE, N-Z Flags Affected None. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. (128-bit operations only) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) If a memory operand effective address is outside the SS segment limit. #UD If CR0.EM[bit 2] = 1. 128-bit operations will generate #UD only if CR4.OSFXSR[bit 9] = 0.
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INSTRUCTION SET REFERENCE, N-Z Compatibility Mode Exceptions Same as for protected mode exceptions. 64-Bit Mode Exceptions #SS(0) #GP(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. (128-bit operations only) If memory operand is not aligned on a 16-byte boundary, regardless of segment. #UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. (128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.
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INSTRUCTION SET REFERENCE, N-Z PADDQ—Add Packed Quadword Integers Opcode 0F D4 /r 66 0F D4 /r Instruction PADDQ mm1, mm2/m64 PADDQ xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Description Add quadword integer mm2/m64 to mm1. Add packed quadword integers xmm2/m128 to xmm1. Description Adds the first operand (destination operand) to the second operand (source operand) and stores the result in the destination operand.
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INSTRUCTION SET REFERENCE, N-Z Flags Affected None. Numeric Exceptions None. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. (128-bit operations only) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) #UD If a memory operand effective address is outside the SS segment limit. If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0.
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INSTRUCTION SET REFERENCE, N-Z Compatibility Mode Exceptions Same as for protected mode exceptions. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. (128-bit operations only) If memory operand is not aligned on a 16-byte boundary, regardless of segment. #UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #NM If CR0.
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INSTRUCTION SET REFERENCE, N-Z PADDSB/PADDSW—Add Packed Signed Integers with Signed Saturation 64-Bit Mode Valid Compat/ Leg Mode Valid PADDSB xmm1, xmm2/m128 Valid Valid 0F ED /r PADDSW mm, mm/m64 Valid Valid 66 0F ED /r PADDSW xmm1, xmm2/m128 Valid Valid Opcode 0F EC /r Instruction PADDSB mm, mm/m64 66 0F EC /r Description Add packed signed byte integers from mm/m64 and mm and saturate the results. Add packed signed byte integers from xmm2/m128 and xmm1 saturate the results.
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INSTRUCTION SET REFERENCE, N-Z Operation PADDSB instruction with 64-bit operands: DEST[7:0] ← SaturateToSignedByte(DEST[7:0] + SRC (7:0]); (* Repeat add operation for 2nd through 7th bytes *) DEST[63:56] ← SaturateToSignedByte(DEST[63:56] + SRC[63:56] ); PADDSB instruction with 128-bit operands: DEST[7:0] ←SaturateToSignedByte (DEST[7:0] + SRC[7:0]); (* Repeat add operation for 2nd through 14th bytes *) DEST[127:120] ← SaturateToSignedByte (DEST[111:120] + SRC[127:120]); PADDSW instruction with 64-bit oper
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INSTRUCTION SET REFERENCE, N-Z #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs. #AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP(0) (128-bit operations only) If a memory operand is not aligned on a 16-byte boundary, regardless of segment.
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INSTRUCTION SET REFERENCE, N-Z #PF(fault-code) If a page fault occurs. #AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol.
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INSTRUCTION SET REFERENCE, N-Z PADDUSB/PADDUSW—Add Packed Unsigned Integers with Unsigned Saturation 64-Bit Mode Valid Compat/ Leg Mode Valid PADDUSB xmm1, xmm2/m128 Valid Valid 0F DD /r PADDUSW mm, mm/m64 Valid Valid 66 0F DD /r PADDUSW xmm1, xmm2/m128 Valid Valid Opcode 0F DC /r Instruction PADDUSB mm, mm/m64 66 0F DC /r Description Add packed unsigned byte integers from mm/m64 and mm and saturate the results. Add packed unsigned byte integers from xmm2/m128 and xmm1 saturate the results.
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INSTRUCTION SET REFERENCE, N-Z Operation PADDUSB instruction with 64-bit operands: DEST[7:0] ← SaturateToUnsignedByte(DEST[7:0] + SRC (7:0] ); (* Repeat add operation for 2nd through 7th bytes *) DEST[63:56] ← SaturateToUnsignedByte(DEST[63:56] + SRC[63:56] PADDUSB instruction with 128-bit operands: DEST[7:0] ← SaturateToUnsignedByte (DEST[7:0] + SRC[7:0]); (* Repeat add operation for 2nd through 14th bytes *) DEST[127:120] ← SaturateToUnSignedByte (DEST[127:120] + SRC[127:120]); PADDUSW instruction with 6
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INSTRUCTION SET REFERENCE, N-Z #UD If CR0.EM[bit 2] = 1. 128-bit operations will generate #UD only if CR4.OSFXSR[bit 9] = 0. Execution of 128-bit instructions on a non-SSE2 capable processor (one that is MMX technology capable) will result in the instruction operating on the mm registers, not #UD. #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, N-Z #UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. (128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0. #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs. #AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol.
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INSTRUCTION SET REFERENCE, N-Z PALIGNR — Packed Align Right Opcode 0F 3A 0F Instruction PALIGNR mm1, mm2/m64, imm8 66 0F 3A 0F PALIGNR xmm1, xmm2/m128, imm8 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Description Concatenate destination and source operands, extract bytealigned result shifted to the right by constant into mm1.
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INSTRUCTION SET REFERENCE, N-Z Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS or GS segments. (128-bit operations only) If not aligned on 16-byte boundary, regardless of segment. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #UD If CR0.EM = 1. (128-bit operations only) If CR4.OSFXSR(bit 9) = 0. If CPUID.SSSE3(ECX bit 9) = 0. #NM If TS bit in CR0 is set.
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INSTRUCTION SET REFERENCE, N-Z #GP(0) If the memory address is in a non-canonical form. (128-bit operations only) If memory operand is not aligned on a 16-byte boundary, regardless of segment. #UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSSE3[bit 9] = 0. #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, N-Z PAND—Logical AND Opcode 0F DB /r Instruction PAND mm, mm/m64 66 0F DB /r PAND xmm1, xmm2/m128 64Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Description Bitwise AND mm/m64 and mm. Bitwise AND of xmm2/m128 and xmm1. Description Performs a bitwise logical AND operation on the source operand (second operand) and the destination operand (first operand) and stores the result in the destination operand.
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INSTRUCTION SET REFERENCE, N-Z #SS(0) #UD If a memory operand effective address is outside the SS segment limit. If CR0.EM[bit 2] = 1. 128-bit operations will generate #UD only if CR4.OSFXSR[bit 9] = 0. Execution of 128-bit instructions on a non-SSE2 capable processor (one that is MMX technology capable) will result in the instruction operating on the mm registers, not #UD. #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception.
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INSTRUCTION SET REFERENCE, N-Z (128-bit operations only) If memory operand is not aligned on a 16-byte boundary, regardless of segment. #UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. (128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0. #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, N-Z PANDN—Logical AND NOT Opcode 0F DF /r Instruction PANDN mm, mm/m64 64-Bit Mode Valid Compat/ Leg Mode Valid 66 0F DF /r PANDN xmm1, xmm2/m128 Valid Valid Description Bitwise AND NOT of mm/m64 and mm. Bitwise AND NOT of xmm2/m128 and xmm1. Description Performs a bitwise logical NOT of the destination operand (first operand), then performs a bitwise logical AND of the source operand (second operand) and the inverted destination operand.
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INSTRUCTION SET REFERENCE, N-Z Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. (128-bit operations only) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) If a memory operand effective address is outside the SS segment limit. #UD If CR0.EM[bit 2] = 1. 128-bit operations will generate #UD only if CR4.OSFXSR[bit 9] = 0.
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INSTRUCTION SET REFERENCE, N-Z 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. (128-bit operations only) If memory operand is not aligned on a 16-byte boundary, regardless of segment. #UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. (128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0. #NM If CR0.TS[bit 3] = 1.
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INSTRUCTION SET REFERENCE, N-Z PAUSE—Spin Loop Hint Opcode F3 90 Instruction PAUSE 64-Bit Mode Valid Compat/ Leg Mode Valid Description Gives hint to processor that improves performance of spin-wait loops. Description Improves the performance of spin-wait loops. When executing a “spin-wait loop,” a Pentium 4 or Intel Xeon processor suffers a severe performance penalty when exiting the loop because it detects a possible memory order violation.
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INSTRUCTION SET REFERENCE, N-Z PAVGB/PAVGW—Average Packed Integers 64-Bit Mode Valid Compat/ Leg Mode Valid PAVGB xmm1, xmm2/m128 Valid Valid 0F E3 /r PAVGW mm1, mm2/m64 Valid Valid 66 0F E3 /r PAVGW xmm1, xmm2/m128 Valid Valid Opcode 0F E0 /r Instruction PAVGB mm1, mm2/m64 66 0F E0, /r Description Average packed unsigned byte integers from mm2/m64 and mm1 with rounding. Average packed unsigned byte integers from xmm2/m128 and xmm1 with rounding.
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INSTRUCTION SET REFERENCE, N-Z PAVGB instruction with 128-bit operands: SRC[7:0) ← (SRC[7:0) + DEST[7:0) + 1) >> 1; (* Temp sum before shifting is 9 bits *) (* Repeat operation performed for bytes 2 through 14 *) SRC[63:56) ← (SRC[63:56) + DEST[63:56) + 1) >> 1; PAVGW instruction with 128-bit operands: SRC[15:0) ← (SRC[15:0) + DEST[15:0) + 1) >> 1; (* Temp sum before shifting is 17 bits *) (* Repeat operation performed for words 2 through 6 *) SRC[127:48) ← (SRC[127:112) + DEST[127:112) + 1) >> 1; Intel C
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INSTRUCTION SET REFERENCE, N-Z Real-Address Mode Exceptions #GP(0) (128-bit operations only) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside of the effective address space from 0 to FFFFH. #UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. (128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0. #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception.
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INSTRUCTION SET REFERENCE, N-Z PCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for Equal 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid PCMPEQW mm, mm/m64 PCMPEQW xmm1, xmm2/m128 Valid Valid Valid Valid 0F 76 /r PCMPEQD mm, mm/m64 Valid Valid 66 0F 76 /r PCMPEQD xmm1, xmm2/m128 Valid Valid Opcode 0F 74 /r 66 0F 74 /r 0F 75 /r 66 0F 75 /r Instruction PCMPEQB mm, mm/m64 PCMPEQB xmm1, xmm2/m128 Description Compare packed bytes in mm/m64 and mm for equality.
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INSTRUCTION SET REFERENCE, N-Z IF DEST[63:56] = SRC[63:56] THEN DEST[63:56] ← FFH; ELSE DEST[63:56] ← 0; FI; PCMPEQB instruction with 128-bit operands: IF DEST[7:0] = SRC[7:0] THEN DEST[7:0) ← FFH; ELSE DEST[7:0] ← 0; FI; (* Continue comparison of 2nd through 15th bytes in DEST and SRC *) IF DEST[63:56] = SRC[63:56] THEN DEST[63:56] ← FFH; ELSE DEST[63:56] ← 0; FI; PCMPEQW instruction with 64-bit operands: IF DEST[15:0] = SRC[15:0] THEN DEST[15:0] ← FFFFH; ELSE DEST[15:0] ← 0; FI; (* Continue comparison of
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INSTRUCTION SET REFERENCE, N-Z THEN DEST[63:32] ← FFFFFFFFH; ELSE DEST[63:32] ← 0; FI; Intel C/C++ Compiler Intrinsic Equivalents PCMPEQB __m64 _mm_cmpeq_pi8 (__m64 m1, __m64 m2) PCMPEQW __m64 _mm_cmpeq_pi16 (__m64 m1, __m64 m2) PCMPEQD __m64 _mm_cmpeq_pi32 (__m64 m1, __m64 m2) PCMPEQB __m128i _mm_cmpeq_epi8 ( __m128i a, __m128i b) PCMPEQW __m128i _mm_cmpeq_epi16 ( __m128i a, __m128i b) PCMPEQD __m128i _mm_cmpeq_epi32 ( __m128i a, __m128i b) Flags Affected None.
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INSTRUCTION SET REFERENCE, N-Z #UD If CR0.EM[bit 2] = 1. 128-bit operations will generate #UD only if CR4.OSFXSR[bit 9] = 0. Execution of 128-bit instructions on a non-SSE2 capable processor (one that is MMX technology capable) will result in the instruction operating on the mm registers, not #UD. #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault.
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INSTRUCTION SET REFERENCE, N-Z PCMPGTB/PCMPGTW/PCMPGTD—Compare Packed Signed Integers for Greater Than 64-Bit Mode Valid Compat/ Leg Mode Valid PCMPGTB xmm1, xmm2/m128 Valid Valid 0F 65 /r PCMPGTW mm, mm/m64 Valid Valid 66 0F 65 /r PCMPGTW xmm1, xmm2/m128 Valid Valid 0F 66 /r PCMPGTD mm, mm/m64 Valid Valid 66 0F 66 /r PCMPGTD xmm1, xmm2/m128 Valid Valid Opcode 0F 64 /r Instruction PCMPGTB mm, mm/m64 66 0F 64 /r Description Compare packed signed byte integers in mm and mm/m64 for gre
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INSTRUCTION SET REFERENCE, N-Z Operation PCMPGTB instruction with 64-bit operands: IF DEST[7:0] > SRC[7:0] THEN DEST[7:0) ← FFH; ELSE DEST[7:0] ← 0; FI; (* Continue comparison of 2nd through 7th bytes in DEST and SRC *) IF DEST[63:56] > SRC[63:56] THEN DEST[63:56] ← FFH; ELSE DEST[63:56] ← 0; FI; PCMPGTB instruction with 128-bit operands: IF DEST[7:0] > SRC[7:0] THEN DEST[7:0) ← FFH; ELSE DEST[7:0] ← 0; FI; (* Continue comparison of 2nd through 15th bytes in DEST and SRC *) IF DEST[63:56] > SRC[63:56] THEN
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INSTRUCTION SET REFERENCE, N-Z PCMPGTD instruction with 128-bit operands: IF DEST[31:0] > SRC[31:0] THEN DEST[31:0] ← FFFFFFFFH; ELSE DEST[31:0] ← 0; FI; (* Continue comparison of 2nd and 3rd doublewords in DEST and SRC *) IF DEST[63:32] > SRC[63:32] THEN DEST[63:32] ← FFFFFFFFH; ELSE DEST[63:32] ← 0; FI; Intel C/C++ Compiler Intrinsic Equivalents PCMPGTB __m64 _mm_cmpgt_pi8 (__m64 m1, __m64 m2) PCMPGTW __m64 _mm_pcmpgt_pi16 (__m64 m1, __m64 m2) DCMPGTD __m64 _mm_pcmpgt_pi32 (__m64 m1, __m64 m2) PCMPGTB _
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INSTRUCTION SET REFERENCE, N-Z #AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP(0) (128-bit operations only) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside of the effective address space from 0 to FFFFH. #UD If CR0.EM[bit 2] = 1. 128-bit operations will generate #UD only if CR4.OSFXSR[bit 9] = 0.
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INSTRUCTION SET REFERENCE, N-Z #AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol.
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INSTRUCTION SET REFERENCE, N-Z PEXTRW—Extract Word 64-Bit Mode Valid Compat/ Leg Mode Valid PEXTRW r64, mm, imm8 Valid N.E. 66 0F C5 /r ib PEXTRW r32, xmm, imm8 Valid Valid REX.W + 66 0F C5 /r ib PEXTRW r64, xmm, imm8 Valid N.E. Opcode 0F C5 /r ib Instruction PEXTRW r32, mm, imm8 REX.W + 0F C5 /r ib Description Extract the word specified by imm8 from mm and move it to r32, bits 15-0. Zero-extend the result. Extract the word specified by imm8 from mm and move it to r64, bits 15-0.
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INSTRUCTION SET REFERENCE, N-Z { SEL ← COUNT AND 7H; TEMP ← (SRC >> (SEL ∗ 16)) AND FFFFH; r64[15:0] ← TEMP[15:0]; r64[63:16] ← ZERO_FILL; } ELSE FOR (PEXTRW instruction with 64-bit source operand) { SEL ← COUNT AND 3H; TEMP ← (SRC >> (SEL ∗ 16)) AND FFFFH; r32[15:0] ← TEMP[15:0]; r32[31:16] ← ZERO_FILL; }; FOR (PEXTRW instruction with 128-bit source operand) { SEL ← COUNT AND 7H; TEMP ← (SRC >> (SEL ∗ 16)) AND FFFFH; r32[15:0] ← TEMP[15:0]; r32[31:16] ← ZERO_FILL; }; FI; Intel C/C++ Compiler Intrinsic
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INSTRUCTION SET REFERENCE, N-Z Real-Address Mode Exceptions #GP(0) If any part of the operand lies outside of the effective address space from 0 to FFFFH. #UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. (128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0. #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault.
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INSTRUCTION SET REFERENCE, N-Z PHADDW/PHADDD — Packed Horizontal Add Opcode 0F 38 01 /r 66 0F 38 01 /r 0F 38 02 /r 66 0F 38 02 /r Instruction PHADDW mm1, mm2/m64 PHADDW xmm1, xmm2/m128 PHADDD mm1, mm2/m64 PHADDD xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Valid Valid Valid Valid Description Add 16-bit signed integers horizontally, pack to MM1. Add 16-bit signed integers horizontally, pack to XMM1. Add 32-bit signed integers horizontally, pack to MM1.
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INSTRUCTION SET REFERENCE, N-Z PHADDD with 64-bit operands : mm1[31-0] = mm1[63-32] + mm1[31-0]; mm1[63-32] = mm2/m64[63-32] + mm2/m64[31-0]; PHADDD with 128-bit operands: xmm1[31-0] = xmm1[63-32] + xmm1[31-0]; xmm1[63-32] = xmm1[127-96] + xmm1[95-64]; xmm1[95-64] = xmm2/m128[63-32] + xmm2/m128[31-0]; xmm1[127-96] = xmm2/m128[127-96] + xmm2/m128[95-64]; Intel C/C++ Compiler Intrinsic Equivalents PHADDW __m64 _mm_hadd_pi16 (__m64 a, __m64 b) PHADDW __m128i _mm_hadd_epi16 (__m128i a, __m128i b) PHADDD
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INSTRUCTION SET REFERENCE, N-Z #UD If CR0.EM = 1. (128-bit operations only) If CR4.OSFXSR(bit 9) = 0. If CPUID.SSSE3(ECX bit 9) = 0. #NM If TS bit in CR0 is set. #MF (64-bit operations only) If there is a pending x87 FPU exception. Virtual 8086 Mode Exceptions Same exceptions as in Real Address Mode. #PF(fault-code) If a page fault occurs. #AC(0) (64-bit operations only). If alignment checking is enabled and unaligned memory reference is made.
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INSTRUCTION SET REFERENCE, N-Z PHADDSW — Packed Horizontal Add and Saturate Opcode 0F 38 03 /r Instruction PHADDSW mm1, mm2/m64 66 0F 38 03 /r PHADDSW xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Description Add 16-bit signed integers horizontally, pack saturated integers to MM1. Add 16-bit signed integers horizontally, pack saturated integers to XMM1.
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INSTRUCTION SET REFERENCE, N-Z Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS or GS segments. (128-bit operations only) If not aligned on 16-byte boundary, regardless of segment. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #UD If CR0.EM = 1. (128-bit operations only) If CR4.OSFXSR(bit 9) = 0. If CPUID.SSSE3(ECX bit 9) = 0. #NM If TS bit in CR0 is set.
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INSTRUCTION SET REFERENCE, N-Z #GP(0) If the memory address is in a non-canonical form. (128-bit operations only) If memory operand is not aligned on a 16-byte boundary, regardless of segment. #UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSSE3[bit 9] = 0. #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, N-Z PHSUBW/PHSUBD — Packed Horizontal Subtract 64-Bit Mode Valid Compat/ Leg Mode Valid PHSUBW xmm1, xmm2/m128 PHSUBD mm1, mm2/m64 Valid Valid Valid Valid PHSUBD xmm1, xmm2/m128 Valid Valid Opcode 0F 38 05 /r Instruction PHSUBW mm1, mm2/m64 66 0F 38 05 /r 0F 38 06 /r 66 0F 38 06 /r Description Subtract 16-bit signed integers horizontally, pack to MM1. Subtract 16-bit signed integers horizontally, pack to XMM1.
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INSTRUCTION SET REFERENCE, N-Z xmm1[79-64] = xmm2/m128[15-0] - xmm2/m128[31-16]; xmm1[95-80] = xmm2/m128[47-32] - xmm2/m128[63-48]; xmm1[111-96] = xmm2/m128[79-64] - xmm2/m128[95-80]; xmm1[127-112] = xmm2/m128[111-96] - xmm2/m128[127-112]; PHSUBD with 64-bit operands: mm1[31-0] = mm1[31-0] - mm1[63-32]; mm1[63-32] = mm2/m64[31-0] - mm2/m64[63-32]; PHSUBD with 128-bit operands: xmm1[31-0] = xmm1[31-0] - xmm1[63-32]; xmm1[63-32] = xmm1[95-64] - xmm1[127-96]; xmm1[95-64] = xmm2/m128[31-0] - xmm2/m128[63-32];
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INSTRUCTION SET REFERENCE, N-Z Real Mode Exceptions #GP(0): If any part of the operand lies outside of the effective address space from 0 to 0FFFFH. (128-bit operations only) If not aligned on 16-byte boundary, regardless of segment. #UD: If CR0.EM = 1. (128-bit operations only) If CR4.OSFXSR(bit 9) = 0. If CPUID.SSSE3(ECX bit 9) = 0. #NM If TS bit in CR0 is set. #MF (64-bit operations only) If there is a pending x87 FPU exception.
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INSTRUCTION SET REFERENCE, N-Z PHSUBSW — Packed Horizontal Subtract and Saturate Opcode 0F 38 07 /r Instruction PHSUBSW mm1, mm2/m64 66 0F 38 07 /r PHSUBSW xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Description Subtract 16-bit signed integer horizontally, pack saturated integers to MM1.
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INSTRUCTION SET REFERENCE, N-Z Intel C/C++ Compiler Intrinsic Equivalent PHSUBSW __m64 _mm_hsubs_pi16 (__m64 a, __m64 b) PHSUBSW __m128i _mm_hsubs_epi16 (__m128i a, __m128i b) Protected Mode Exceptions #GP(0) if a memory operand effective address is outside the CS, DS, ES, FS or GS segments. If not aligned on 16-byte boundary, regardless of segment (128-bit operations only). #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, N-Z Compatibility Mode Exceptions Same as for protected mode exceptions. 64-Bit Mode Exceptions #SS(0) #GP(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. (128-bit operations only) If memory operand is not aligned on a 16-byte boundary, regardless of segment. #UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSSE3[bit 9] = 0. #NM If CR0.TS[bit 3] = 1.
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INSTRUCTION SET REFERENCE, N-Z PINSRW—Insert Word 64-Bit Mode Valid Compat/ Leg Mode Valid PINSRW mm, r64/m16, imm8 Valid N.E. 66 0F C4 /r ib PINSRW xmm, r32/m16, imm8 Valid Valid REX.W + 66 0F C4 /r ib PINSRW xmm, r64/m16, imm8 Valid N.E. Opcode 0F C4 /r ib Instruction PINSRW mm, r32/m16, imm8 REX.
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INSTRUCTION SET REFERENCE, N-Z DEST ← (DEST AND NOT MASK) OR (((SRC << (SEL ∗ 16)) AND MASK); PINSRW instruction with 128-bit source operand: SEL ← COUNT AND 7H; CASE (Determine word position) OF SEL ← 0: MASK ← 0000000000000000000000000000FFFFH; SEL ← 1: MASK ← 000000000000000000000000FFFF0000H; SEL ← 2: MASK ← 00000000000000000000FFFF00000000H; SEL ← 3: MASK ← 0000000000000000FFFF000000000000H; SEL ← 4: MASK ← 000000000000FFFF0000000000000000H; SEL ← 5: MASK ← 00000000FFFF00000000000000000000H; SEL ← 6:
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INSTRUCTION SET REFERENCE, N-Z Real-Address Mode Exceptions #GP(0) If any part of the operand lies outside of the effective address space from 0 to FFFFH. #UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. (128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0. #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault.
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INSTRUCTION SET REFERENCE, N-Z PMADDUBSW — Multiply and Add Packed Signed and Unsigned Bytes Opcode 0F 38 04 /r Instruction PMADDUBSW mm1, mm2/m64 66 0F 38 04 /r PMADDUBSW xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Description Multiply signed and unsigned bytes, add horizontal pair of signed words, pack saturated signed-words to MM1. Multiply signed and unsigned bytes, add horizontal pair of signed words, pack saturated signed-words to XMM1.
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INSTRUCTION SET REFERENCE, N-Z Intel C/C++ Compiler Intrinsic Equivalents PMADDUBSW __m64 _mm_maddubs_pi16 (__m64 a, __m64 b) PMADDUBSW __m128i _mm_maddubs_epi16 (__m128i a, __m128i b) Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS or GS segments. (128-bit operations only) If not aligned on 16-byte boundary, regardless of segment. #SS(0) If a memory operand effective address is outside the SS segment limit.
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INSTRUCTION SET REFERENCE, N-Z Compatibility Mode Exceptions Same as for protected mode exceptions. 64-Bit Mode Exceptions #SS(0) #GP(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. (128-bit operations only) If memory operand is not aligned on a 16-byte boundary, regardless of segment. #UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSSE3[bit 9] = 0. #NM If CR0.TS[bit 3] = 1.
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INSTRUCTION SET REFERENCE, N-Z PMADDWD—Multiply and Add Packed Integers Opcode 0F F5 /r Instruction PMADDWD mm, mm/m64 66 0F F5 /r PMADDWD xmm1, xmm2/m128 64Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Description Multiply the packed words in mm by the packed words in mm/m64, add adjacent doubleword results, and store in mm. Multiply the packed word integers in xmm1 by the packed word integers in xmm2/m128, add adjacent doubleword results, and store in xmm1.
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INSTRUCTION SET REFERENCE, N-Z SRC DEST TEMP X3 ∗ Y3 DEST X3 Y3 X2 Y2 X2 ∗ Y2 X1 X0 Y1 Y0 X1 ∗ Y1 X0 ∗ Y0 (X3∗Y3) + (X2∗Y2) (X1∗Y1) + (X0∗Y0) Figure 4-2.
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INSTRUCTION SET REFERENCE, N-Z #UD If CR0.EM[bit 2] = 1. 128-bit operations will generate #UD only if CR4.OSFXSR[bit 9] = 0. Execution of 128-bit instructions on a non-SSE2 capable processor (one that is MMX technology capable) will result in the instruction operating on the mm registers, not #UD. #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, N-Z #UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. (128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0. #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs. #AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 4-94 Vol.
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INSTRUCTION SET REFERENCE, N-Z PMAXSW—Maximum of Packed Signed Word Integers Opcode 0F EE /r Instruction PMAXSW mm1, mm2/m64 66 0F EE /r PMAXSW xmm1, xmm2/m128 64Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Description Compare signed word integers in mm2/m64 and mm1 and return maximum values. Compare signed word integers in xmm2/m128 and xmm1 and return maximum values.
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INSTRUCTION SET REFERENCE, N-Z IF DEST[127:112] > SRC[127:112]) THEN DEST[127:112] ← DEST[127:112]; ELSE DEST[127:112] ← SRC[127:112]; FI; Intel C/C++ Compiler Intrinsic Equivalent PMAXSW __m64 _mm_max_pi16(__m64 a, __m64 b) PMAXSW __m128i _mm_max_epi16 ( __m128i a, __m128i b) Flags Affected None. Numeric Exceptions None. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
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INSTRUCTION SET REFERENCE, N-Z #UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. (128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0. #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault. #AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made.
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INSTRUCTION SET REFERENCE, N-Z PMAXUB—Maximum of Packed Unsigned Byte Integers Opcode 0F DE /r Instruction PMAXUB mm1, mm2/m64 66 0F DE /r PMAXUB xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Description Compare unsigned byte integers in mm2/m64 and mm1 and returns maximum values. Compare unsigned byte integers in xmm2/m128 and xmm1 and returns maximum values.
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INSTRUCTION SET REFERENCE, N-Z DEST[127:120] ← DEST[127:120]; ELSE DEST[127:120] ← SRC[127:120]; FI; Intel C/C++ Compiler Intrinsic Equivalent PMAXUB __m64 _mm_max_pu8(__m64 a, __m64 b) PMAXUB __m128i _mm_max_epu8 ( __m128i a, __m128i b) Flags Affected None. Numeric Exceptions None. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
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INSTRUCTION SET REFERENCE, N-Z #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault. #AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same as for protected mode exceptions.
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INSTRUCTION SET REFERENCE, N-Z PMINSW—Minimum of Packed Signed Word Integers Opcode 0F EA /r Instruction PMINSW mm1, mm2/m64 66 0F EA /r PMINSW xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Description Compare signed word integers in mm2/m64 and mm1 and return minimum values. Compare signed word integers in xmm2/m128 and xmm1 and return minimum values.
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INSTRUCTION SET REFERENCE, N-Z (* Repeat operation for 2nd through 7th words in source and destination operands *) IF DEST[127:112] < SRC/m64[127:112] THEN DEST[127:112] ← DEST[127:112]; ELSE DEST[127:112] ← SRC[127:112]; FI; Intel C/C++ Compiler Intrinsic Equivalent PMINSW __m64 _mm_min_pi16 (__m64 a, __m64 b) PMINSW __m128i _mm_min_epi16 ( __m128i a, __m128i b) Flags Affected None. Numeric Exceptions None.
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INSTRUCTION SET REFERENCE, N-Z #UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. (128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0. #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault. #AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made.
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INSTRUCTION SET REFERENCE, N-Z PMINUB—Minimum of Packed Unsigned Byte Integers Opcode 0F DA /r Instruction PMINUB mm1, mm2/m64 66 0F DA /r PMINUB xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Description Compare unsigned byte integers in mm2/m64 and mm1 and returns minimum values. Compare unsigned byte integers in xmm2/m128 and xmm1 and returns minimum values.
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INSTRUCTION SET REFERENCE, N-Z ELSE DEST[127:120] ← SRC[127:120]; FI; Intel C/C++ Compiler Intrinsic Equivalent PMINUB __m64 _m_min_pu8 (__m64 a, __m64 b) PMINUB __m128i _mm_min_epu8 ( __m128i a, __m128i b) Flags Affected None. Numeric Exceptions None. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. (128-bit operations only) If a memory operand is not aligned on a 16-byte boundary, regardless of segment.
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INSTRUCTION SET REFERENCE, N-Z #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault. #AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same as for protected mode exceptions.
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INSTRUCTION SET REFERENCE, N-Z PMOVMSKB—Move Byte Mask Opcode 0F D7 /r REX.W + 0F D7 /r 66 0F D7 /r REX.W + 66 0F D7 /r Instruction PMOVMSKB r32, mm PMOVMSKB r64, mm PMOVMSKB r32, xmm PMOVMSKB r64, xmm 64-Bit Mode Valid Compat/ Leg Mode Valid Valid N.E. Valid Valid Valid N.E. Description Move a byte mask of mm to r32. Move a byte mask of mm to the lower 32-bits of r64 and zero-fill the upper 32-bits. Move a byte mask of xmm to r32.
PAGE 110
INSTRUCTION SET REFERENCE, N-Z PMOVMSKB instruction with 64-bit source operand and r64: r64[0] ← SRC[7]; r64[1] ← SRC[15]; (* Repeat operation for bytes 2 through 6 *) r64[7] ← SRC[63]; r64[63:8] ← ZERO_FILL; PMOVMSKB instruction with 128-bit source operand and r64: r64[0] ← SRC[7]; r64[1] ← SRC[15]; (* Repeat operation for bytes 2 through 14 *) r64[15] ← SRC[127]; r64[63:16] ← ZERO_FILL; Intel C/C++ Compiler Intrinsic Equivalent PMOVMSKB int_mm_movemask_pi8(__m64 a) PMOVMSKB int _mm_movemask_epi8 ( __
PAGE 111
INSTRUCTION SET REFERENCE, N-Z Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. Vol.
PAGE 112
INSTRUCTION SET REFERENCE, N-Z PMULHRSW — Packed Multiply High with Round and Scale Opcode 0F 38 0B /r Instruction PMULHRSW mm1, mm2/m64 66 0F 38 0B /r PMULHRSW xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Description Multiply 16-bit signed words, scale and round signed doublewords, pack high 16 bits to MM1. Multiply 16-bit signed words, scale and round signed doublewords, pack high 16 bits to XMM1.
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INSTRUCTION SET REFERENCE, N-Z temp5[31:0] = INT32 ((DEST[95:80] * SRC[95:80]) >>14) + 1; temp6[31:0] = INT32 ((DEST[111:96] * SRC[111:96]) >>14) + 1; temp7[31:0] = INT32 ((DEST[127:112] * SRC[127:112) >>14) + 1; DEST[15:0] = temp0[16:1]; DEST[31:15] = temp1[16:1]; DEST[47:32] = temp2[16:1]; DEST[63:48] = temp3[16:1]; DEST[79:64] = temp4[16:1]; DEST[95:80] = temp5[16:1]; DEST[111:96] = temp6[16:1]; DEST[127:112] = temp7[16:1]; Intel C/C++ Compiler Intrinsic Equivalents PMULHRSW __m64 _mm_mulhrs_pi16 (__m
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INSTRUCTION SET REFERENCE, N-Z #NM If TS bit in CR0 is set. #MF (64-bit operations only) If there is a pending x87 FPU exception. Virtual 8086 Mode Exceptions Same exceptions as in Real Address Mode. #PF(fault-code) If a page fault occurs. #AC(0) (64-bit operations only) If alignment checking is enabled and unaligned memory reference is made. Compatibility Mode Exceptions Same as for protected mode exceptions.
PAGE 115
INSTRUCTION SET REFERENCE, N-Z PMULHUW—Multiply Packed Unsigned Integers and Store High Result Opcode 0F E4 /r Instruction PMULHUW mm1, mm2/m64 66 0F E4 /r PMULHUW xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Description Multiply the packed unsigned word integers in mm1 register and mm2/m64, and store the high 16 bits of the results in mm1. Multiply the packed unsigned word integers in xmm1 and xmm2/m128, and store the high 16 bits of the results in xmm1.
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INSTRUCTION SET REFERENCE, N-Z TEMP2[31:0] ← TEMP3[31:0] ← DEST[15:0] ← DEST[31:16] ← DEST[47:32] ← DEST[63:48] ← DEST[47:32] ∗ SRC[47:32]; DEST[63:48] ∗ SRC[63:48]; TEMP0[31:16]; TEMP1[31:16]; TEMP2[31:16]; TEMP3[31:16]; PMULHUW instruction with 128-bit operands: TEMP0[31:0] ← DEST[15:0] ∗ SRC[15:0]; (* Unsigned multiplication *) TEMP1[31:0] ← DEST[31:16] ∗ SRC[31:16]; TEMP2[31:0] ← DEST[47:32] ∗ SRC[47:32]; TEMP3[31:0] ← DEST[63:48] ∗ SRC[63:48]; TEMP4[31:0] ← DEST[79:64] ∗ SRC[79:64]; TEMP5[31:0] ← DE
PAGE 117
INSTRUCTION SET REFERENCE, N-Z #UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. (128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0. #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs. #AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
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INSTRUCTION SET REFERENCE, N-Z #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs. #AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 4-116 Vol.
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INSTRUCTION SET REFERENCE, N-Z PMULHW—Multiply Packed Signed Integers and Store High Result Opcode 0F E5 /r Instruction PMULHW mm, mm/m64 66 0F E5 /r PMULHW xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Description Multiply the packed signed word integers in mm1 register and mm2/m64, and store the high 16 bits of the results in mm1. Multiply the packed signed word integers in xmm1 and xmm2/m128, and store the high 16 bits of the results in xmm1.
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INSTRUCTION SET REFERENCE, N-Z TEMP7[31:0] ← DEST[127:112] ∗ SRC[127:112]; DEST[15:0] ← TEMP0[31:16]; DEST[31:16] ← TEMP1[31:16]; DEST[47:32] ← TEMP2[31:16]; DEST[63:48] ← TEMP3[31:16]; DEST[79:64] ← TEMP4[31:16]; DEST[95:80] ← TEMP5[31:16]; DEST[111:96] ← TEMP6[31:16]; DEST[127:112] ← TEMP7[31:16]; Intel C/C++ Compiler Intrinsic Equivalent PMULHW __m64 _mm_mulhi_pi16 (__m64 m1, __m64 m2) PMULHW __m128i _mm_mulhi_epi16 ( __m128i a, __m128i b) Flags Affected None. Numeric Exceptions None.
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INSTRUCTION SET REFERENCE, N-Z Real-Address Mode Exceptions #GP(0) (128-bit operations only) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside of the effective address space from 0 to FFFFH. #UD If CR0.EM[bit 2] = 1. 128-bit operations will generate #UD only if CR4.OSFXSR[bit 9] = 0.
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INSTRUCTION SET REFERENCE, N-Z PMULLW—Multiply Packed Signed Integers and Store Low Result Opcode 0F D5 /r Instruction PMULLW mm, mm/m64 66 0F D5 /r PMULLW xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Description Multiply the packed signed word integers in mm1 register and mm2/m64, and store the low 16 bits of the results in mm1. Multiply the packed signed word integers in xmm1 and xmm2/m128, and store the low 16 bits of the results in xmm1.
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INSTRUCTION SET REFERENCE, N-Z DEST[15:0] ← DEST[31:16] ← DEST[47:32] ← DEST[63:48] ← TEMP0[15:0]; TEMP1[15:0]; TEMP2[15:0]; TEMP3[15:0]; PMULLW instruction with 64-bit operands: TEMP0[31:0] ← DEST[15:0] ∗ SRC[15:0]; (* Signed multiplication *) TEMP1[31:0] ← DEST[31:16] ∗ SRC[31:16]; TEMP2[31:0] ← DEST[47:32] ∗ SRC[47:32]; TEMP3[31:0] ← DEST[63:48] ∗ SRC[63:48]; TEMP4[31:0] ← DEST[79:64] ∗ SRC[79:64]; TEMP5[31:0] ← DEST[95:80] ∗ SRC[95:80]; TEMP6[31:0] ← DEST[111:96] ∗ SRC[111:96]; TEMP7[31:0] ← DEST[127
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INSTRUCTION SET REFERENCE, N-Z #UD If CR0.EM[bit 2] = 1. 128-bit operations will generate #UD only if CR4.OSFXSR[bit 9] = 0. Execution of 128-bit instructions on a non-SSE2 capable processor (one that is MMX technology capable) will result in the instruction operating on the mm registers, not #UD. #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, N-Z #UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. (128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0. #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs. #AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol.
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INSTRUCTION SET REFERENCE, N-Z PMULUDQ—Multiply Packed Unsigned Doubleword Integers Opcode 0F F4 /r Instruction PMULUDQ mm1, mm2/m64 66 OF F4 /r PMULUDQ xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Description Multiply unsigned doubleword integer in mm1 by unsigned doubleword integer in mm2/m64, and store the quadword result in mm1.
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INSTRUCTION SET REFERENCE, N-Z Intel C/C++ Compiler Intrinsic Equivalent PMULUDQ __m64 _mm_mul_su32 (__m64 a, __m64 b) PMULUDQ __m128i _mm_mul_epu32 ( __m128i a, __m128i b) Flags Affected None. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. (128-bit operations only) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) If a memory operand effective address is outside the SS segment limit.
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INSTRUCTION SET REFERENCE, N-Z #AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same as for protected mode exceptions. 64-Bit Mode Exceptions #SS(0) #GP(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. (128-bit operations only) If memory operand is not aligned on a 16-byte boundary, regardless of segment. #UD If CR0.EM[bit 2] = 1.
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INSTRUCTION SET REFERENCE, N-Z POP—Pop a Value from the Stack Opcode 8F /0 Instructio n POP r/m16 64-Bit Mode Valid Compat/ Leg Mode Valid 8F /0 POP r/m32 N.E. Valid 8F /0 POP r/m64 Valid N.E. 58+ rw POP r16 Valid Valid 58+ rd POP r32 N.E. Valid 58+ rd POP r64 Valid N.E. 1F POP DS Invalid Valid 07 POP ES Invalid Valid 17 POP SS Invalid Valid 0F A1 POP FS Valid Valid 0F A1 POP FS N.E. Valid 0F A1 POP FS Valid N.E. 0F A9 POP GS Valid Valid 0F A9 POP GS N.
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INSTRUCTION SET REFERENCE, N-Z The address-size attribute of the stack segment determines the stack pointer size (16, 32, 64 bits) and the operand-size attribute of the current code segment determines the amount the stack pointer is incremented (2, 4, 8 bytes). For example, if the address- and operand-size attributes are 32, the 32-bit ESP register (stack pointer) is incremented by 4; if they are 16, the 16-bit SP register is incremented by 2.
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INSTRUCTION SET REFERENCE, N-Z In 64-bit mode, using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). When in 64-bit mode, POPs using 32-bit operands are not encodable and POPs to DS, ES, SS are not valid. See the summary chart at the beginning of this section for encoding data and limits.
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INSTRUCTION SET REFERENCE, N-Z 64-BIT_MODE IF FS, or GS is loaded with non-NULL selector; THEN IF segment selector index is outside descriptor table limits OR segment is not a data or readable code segment OR ((segment is a data or nonconforming code segment) AND (both RPL and CPL > DPL)) THEN #GP(selector); IF segment not marked present THEN #NP(selector); ELSE SegmentRegister ← segment selector; SegmentRegister ← segment descriptor; FI; FI; IF FS, or GS is loaded with a NULL selector; THEN SegmentRegiste
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INSTRUCTION SET REFERENCE, N-Z IF DS, ES, FS, or GS is loaded with non-NULL selector; THEN IF segment selector index is outside descriptor table limits or segment is not a data or readable code segment or ((segment is a data or nonconforming code segment) and (both RPL and CPL > DPL)) THEN #GP(selector); FI; IF segment not marked present THEN #NP(selector); ELSE SegmentRegister ← segment selector; SegmentRegister ← segment descriptor; FI; FI; IF DS, ES, FS, or GS is loaded with a NULL selector THEN Segment
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INSTRUCTION SET REFERENCE, N-Z If the DS, ES, FS, or GS register is being loaded and the segment pointed to is not a data or readable code segment. If the DS, ES, FS, or GS register is being loaded and the segment pointed to is a data or nonconforming code segment, but both the RPL and the CPL are greater than the DPL. #SS(0) If the current top of stack is not within the stack segment. If a memory operand effective address is outside the SS segment limit.
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INSTRUCTION SET REFERENCE, N-Z #PF(fault-code) If a page fault occurs. #NP If the FS or GS register is being loaded and the segment pointed to is marked not present. Vol.
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INSTRUCTION SET REFERENCE, N-Z POPA/POPAD—Pop All General-Purpose Registers Opcode 61 61 Instruction POPA POPAD 64-Bit Mode Invalid Invalid Compat/ Leg Mode Valid Valid Description Pop DI, SI, BP, BX, DX, CX, and AX. Pop EDI, ESI, EBP, EBX, EDX, ECX, and EAX. Description Pops doublewords (POPAD) or words (POPA) from the stack into the general-purpose registers.
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INSTRUCTION SET REFERENCE, N-Z ELSE (* OperandSize = 16, instruction = POPA *) DI ← Pop(); SI ← Pop(); BP ← Pop(); Increment ESP by 2; (* Skip next 2 bytes of stack *) BX ← Pop(); DX ← Pop(); CX ← Pop(); AX ← Pop(); FI; FI; Flags Affected None. Protected Mode Exceptions #SS(0) If the starting or ending stack address is not within the stack segment. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, N-Z POPF/POPFD/POPFQ—Pop Stack into EFLAGS Register Opcode 9D Instruction POPF 64-Bit Mode Valid Compat/ Leg Mode Valid 9D REX.W + 9D POPFD POPFQ N.E. Valid Valid N.E. Description Pop top of stack into lower 16 bits of EFLAGS. Pop top of stack into EFLAGS. Pop top of stack and zero-extend into RFLAGS.
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INSTRUCTION SET REFERENCE, N-Z bits from the stack, loads the lower 32 bits into RFLAGS, and zero extends the upper bits of RFLAGS. See Chapter 3 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for more information about the EFLAGS registers.
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INSTRUCTION SET REFERENCE, N-Z RFLAGS ← Pop(); (* 64-bit pop *) (* All non-reserved bits except IOPL, RF, VIP, and VIF can be modified; IOPL, RF, VM, and all reserved bits are unaffected; VIP and VIF are cleared. *) FI; ELSE (* OperandSize = 16 *) EFLAGS[15:0] ← Pop(); (* 16-bit pop *) (* All non-reserved bits except IOPL can be modified; IOPL and all reserved bits are unaffected.
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INSTRUCTION SET REFERENCE, N-Z Virtual-8086 Mode Exceptions #GP(0) If the I/O privilege level is less than 3. If an attempt is made to execute the POPF/POPFD instruction with an operand-size override prefix. #SS(0) If the top of stack is not within the stack segment. #PF(fault-code) If a page fault occurs. #AC(0) If an unaligned memory reference is made while alignment checking is enabled. Compatibility Mode Exceptions Same as for protected mode exceptions.
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INSTRUCTION SET REFERENCE, N-Z POR—Bitwise Logical OR Opcode 0F EB /r 66 0F EB /r Instruction POR mm, mm/m64 POR xmm1, xmm2/m128 64-Bit Mode Valid Valid Compat/ Leg Mode Valid Valid Description Bitwise OR of mm/m64 and mm. Bitwise OR of xmm2/m128 and xmm1. Description Performs a bitwise logical OR operation on the source operand (second operand) and the destination operand (first operand) and stores the result in the destination operand.
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INSTRUCTION SET REFERENCE, N-Z #UD If CR0.EM[bit 2] = 1. 128-bit operations will generate #UD only if CR4.OSFXSR[bit 9] = 0. Execution of 128-bit instructions on a non-SSE2 capable processor (one that is MMX technology capable) will result in the instruction operating on the mm registers, not #UD. #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, N-Z #UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. (128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0. #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs. #AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 4-142 Vol.
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INSTRUCTION SET REFERENCE, N-Z PREFETCHh—Prefetch Data Into Caches Opcode 0F 18 /1 0F 18 /2 0F 18 /3 0F 18 /0 Instruction PREFETCHT0 m8 64-Bit Mode Valid Compat/ Leg Mode Valid PREFETCHT1 m8 Valid Valid PREFETCHT2 m8 Valid Valid PREFETCHNTA m8 Valid Valid Description Move data from m8 closer to the processor using T0 hint. Move data from m8 closer to the processor using T1 hint. Move data from m8 closer to the processor using T2 hint. Move data from m8 closer to the processor using NTA hint.
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INSTRUCTION SET REFERENCE, N-Z The PREFETCHh instruction is merely a hint and does not affect program behavior. If executed, this instruction moves data closer to the processor in anticipation of future use. The implementation of prefetch locality hints is implementation-dependent, and can be overloaded or ignored by a processor implementation. The amount of data prefetched is also processor implementation-dependent. It will, however, be a minimum of 32 bytes.
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INSTRUCTION SET REFERENCE, N-Z PSADBW—Compute Sum of Absolute Differences Opcode 0F F6 /r Instruction PSADBW mm1, mm2/m64 66 0F F6 /r PSADBW xmm1, xmm2/m128 64Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Description Computes the absolute differences of the packed unsigned byte integers from mm2 /m64 and mm1; differences are then summed to produce an unsigned word integer result.
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INSTRUCTION SET REFERENCE, N-Z SRC X7 X6 X5 X4 X3 X2 X1 X0 DEST Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 TEMP ABS(X7:Y7) ABS(X6:Y6) ABS(X5:Y5) ABS(X4:Y4) ABS(X3:Y3) ABS(X2:Y2) ABS(X1:Y1) ABS(X0:Y0) DEST 00H 00H 00H 00H 00H 00H SUM(TEMP7...TEMP0) Figure 4-5.
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INSTRUCTION SET REFERENCE, N-Z Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. (128-bit operations only) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) If a memory operand effective address is outside the SS segment limit. #UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. (128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0. #NM If CR0.TS[bit 3] = 1.
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INSTRUCTION SET REFERENCE, N-Z #GP(0) If the memory address is in a non-canonical form. (128-bit operations only) If memory operand is not aligned on a 16-byte boundary, regardless of segment. #UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. (128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0. #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, N-Z PSHUFB — Packed Shuffle Bytes Opcode 0F 38 00 /r Instruction PSHUFB mm1, mm2/m64 66 0F 38 00 /r PSHUFB xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Description Shuffle bytes in mm1 according to contents of mm2/m64. Shuffle bytes in xmm1 according to contents of xmm2/m128.
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INSTRUCTION SET REFERENCE, N-Z endif } 00 + + ))+ + + + + + 00 + + + + + + ))+ + 00 + + + + ))+ + + + Figure 4-6.
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INSTRUCTION SET REFERENCE, N-Z Real Mode Exceptions #GP(0) If any part of the operand lies outside of the effective address space from 0 to 0FFFFH. (128-bit operations only) If not aligned on 16-byte boundary, regardless of segment. #UD If CR0.EM = 1. (128-bit operations only) If CR4.OSFXSR(bit 9) = 0. If CPUID.SSSE3(ECX bit 9) = 0. #NM If TS bit in CR0 is set. #MF (64-bit operations only) If there is a pending x87 FPU exception. Virtual 8086 Mode Exceptions Same exceptions as in Real Address Mode.
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INSTRUCTION SET REFERENCE, N-Z PSHUFD—Shuffle Packed Doublewords Opcode 66 0F 70 /r ib 64-Bit Mode Valid Instruction PSHUFD xmm1, xmm2/m128, imm8 Compat/ Leg Mode Valid Description Shuffle the doublewords in xmm2/m128 based on the encoding in imm8 and store the result in xmm1. Description Copies doublewords from source operand (second operand) and inserts them in the destination operand (first operand) at the locations selected with the order operand (third operand).
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INSTRUCTION SET REFERENCE, N-Z Operation DEST[31:0] ← (SRC >> (ORDER[1:0] ∗ 32))[31:0]; DEST[63:32] ← (SRC >> (ORDER[3:2] ∗ 32))[31:0]; DEST[95:64] ← (SRC >> (ORDER[5:4] ∗ 32))[31:0]; DEST[127:96] ← (SRC >> (ORDER[7:6] ∗ 32))[31:0]; Intel C/C++ Compiler Intrinsic Equivalent PSHUFD __m128i _mm_shuffle_epi32(__m128i a, int n) Flags Affected None. Numeric Exceptions None. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
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INSTRUCTION SET REFERENCE, N-Z Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault. Compatibility Mode Exceptions Same as for protected mode exceptions. 64-Bit Mode Exceptions #SS(0) #GP(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.
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INSTRUCTION SET REFERENCE, N-Z PSHUFHW—Shuffle Packed High Words Opcode F3 0F 70 /r ib Instruction PSHUFHW xmm1, xmm2/ m128, imm8 64-Bit Mode Valid Compat/ Leg Mode Valid Description Shuffle the high words in xmm2/m128 based on the encoding in imm8 and store the result in xmm1.
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INSTRUCTION SET REFERENCE, N-Z Numeric Exceptions None. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) #UD If a memory operand effective address is outside the SS segment limit. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #NM If CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, N-Z #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #NM If CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs. Vol.
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INSTRUCTION SET REFERENCE, N-Z PSHUFLW—Shuffle Packed Low Words Opcode F2 0F 70 /r ib Instruction PSHUFLW xmm1, xmm2/m128, imm8 64-Bit Mode Valid Compat/ Leg Mode Valid Description Shuffle the low words in xmm2/m128 based on the encoding in imm8 and store the result in xmm1.
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INSTRUCTION SET REFERENCE, N-Z Numeric Exceptions None. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) If a memory operand effective address is outside the SS segment limit. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #NM If CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, N-Z #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #NM If CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs. 4-160 Vol.
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INSTRUCTION SET REFERENCE, N-Z PSHUFW—Shuffle Packed Words Opcode 0F 70 /r ib Instruction PSHUFW mm1, mm2/m64, imm8 64-Bit Mode Valid Compat/ Leg Mode Valid Description Shuffle the words in mm2/m64 based on the encoding in imm8 and store the result in mm1. Description Copies words from the source operand (second operand) and inserts them in the destination operand (first operand) at word locations selected with the order operand (third operand).
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INSTRUCTION SET REFERENCE, N-Z Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #UD If CR0.EM[bit 2] = 1. #NM If CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
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INSTRUCTION SET REFERENCE, N-Z PSIGNB/PSIGNW/PSIGND — Packed SIGN Opcode 0F 38 08 /r Instruction PSIGNB mm1, mm2/m64 66 0F 38 08 /r PSIGNB xmm1, xmm2/m128 PSIGNW mm1, mm2/m64 PSIGNW xmm1, xmm2/m128 PSIGND mm1, mm2/m64 0F 38 09 /r 66 0F 38 09 /r 0F 38 0A /r 66 0F 38 0A /r PSIGND xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Description Negate packed byte integers in mm1 if the corresponding sign in mm2/m64 is less tha
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INSTRUCTION SET REFERENCE, N-Z DEST[7...0] <- 0 else if(SRC[7..0] > 0 ) DEST[7...0] <- DEST[7...0] Repeat operation for 2nd through 7th bytes if (SRC[63..56] < 0 ) DEST[63...56] <- Neg(DEST[63...56]) else if(SRC[63.. 56] == 0 ) DEST[63...56] <- 0 else if(SRC[63.. 56] > 0 ) DEST[63...56] <- DEST[63...56] PSIGNB with 128 bit operands: if (SRC[7..0] < 0 ) DEST[7...0] <- Neg(DEST[7...0]) else if(SRC[7..0] == 0 ) DEST[7...0] <- 0 else if(SRC[7..0] > 0 ) DEST[7...0] <- DEST[7...
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INSTRUCTION SET REFERENCE, N-Z DEST[15...0] <- Neg(DEST[15...0]) else if(SRC[15..0] == 0 ) DEST[15...0] <- 0 else if(SRC[15..0] > 0 ) DEST[15...0] <- DEST[15...0] Repeat operation for 2nd through 7th words if (SRC[127..112] < 0 ) DEST[127...112] <- Neg(DEST[127...112]) else if(SRC[127.. 112] == 0 ) DEST[127...112] <- 0 else if(SRC[127.. 112] > 0 ) DEST[127...112] <- DEST[127...112] PSIGND with 64 bit operands: if (SRC[31..0] < 0 ) DEST[31...0] <- Neg(DEST[31...0]) else if(SRC[31..0] == 0 ) DEST[31...
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INSTRUCTION SET REFERENCE, N-Z PSIGNB __m128i _mm_sign_epi8 (__m128i a, __m128i b) PSIGNW __m64 _mm_sign_pi16 (__m64 a, __m64 b) PSIGNW __m128i _mm_sign_epi16 (__m128i a, __m128i b) PSIGND __m64 _mm_sign_pi32 (__m64 a, __m64 b) PSIGND __m128i _mm_sign_epi32 (__m128i a, __m128i b) Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS or GS segments. (128-bit operations only) If not aligned on 16-byte boundary, regardless of segment.
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INSTRUCTION SET REFERENCE, N-Z Compatibility Mode Exceptions Same as for protected mode exceptions. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. (128-bit operations only) If memory operand is not aligned on a 16-byte boundary, regardless of segment. #UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSSE3[bit 9] = 0. #NM If CR0.
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INSTRUCTION SET REFERENCE, N-Z PSLLDQ—Shift Double Quadword Left Logical Opcode 66 0F 73 /7 ib Instruction PSLLDQ xmm1, imm8 64-Bit Mode Valid Compat/ Leg Mode Valid Description Shift xmm1 left by imm8 bytes while shifting in 0s. Description Shifts the destination operand (first operand) to the left by the number of bytes specified in the count operand (second operand). The empty low-order bytes are cleared (set to all 0s).
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INSTRUCTION SET REFERENCE, N-Z Virtual-8086 Mode Exceptions Same exceptions as in Protected Mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. Vol.
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INSTRUCTION SET REFERENCE, N-Z PSLLW/PSLLD/PSLLQ—Shift Packed Data Left Logical Opcode 0F F1 /r 66 0F F1 /r Instruction PSLLW mm, mm/m64 PSLLW xmm1, xmm2/m128 64Bit Mode Valid Compat/ Leg Mode Valid Valid Valid 0F 71 /6 ib PSLLW xmm1, imm8 Valid Valid 66 0F 71 /6 ib PSLLW xmm1, imm8 Valid Valid 0F F2 /r PSLLD mm, mm/m64 Valid Valid 66 0F F2 /r PSLLD xmm1, xmm2/m128 Valid Valid 0F 72 /6 ib PSLLD mm, imm8 Valid Valid 66 0F 72 /6 ib PSLLD xmm1, imm8 Valid Valid 0F F3 /r PSLLQ m
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INSTRUCTION SET REFERENCE, N-Z The destination operand may be an MMX technology register or an XMM register; the count operand can be either an MMX technology register or an 64-bit memory location, an XMM register or a 128-bit memory location, or an 8-bit immediate. Note that only the first 64-bits of a 128-bit count operand are checked to compute the count. Pre-Shift DEST X3 X2 X3 << COUNT X2 << COUNT X1 X0 Shift Left with Zero Extension Post-Shift DEST X1 << COUNT X0 << COUNT Figure 4-8.
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INSTRUCTION SET REFERENCE, N-Z THEN DEST[64:0] ← 0000000000000000H; ELSE DEST ← ZeroExtend(DEST << COUNT); FI; PSLLW instruction with 128-bit operand: COUNT ← COUNT_SOURCE[63:0]; IF (COUNT > 15) THEN DEST[128:0] ← 00000000000000000000000000000000H; ELSE DEST[15:0] ← ZeroExtend(DEST[15:0] << COUNT); (* Repeat shift operation for 2nd through 7th words *) DEST[127:112] ← ZeroExtend(DEST[127:112] << COUNT); FI; PSLLD instruction with 128-bit operand: COUNT ← COUNT_SOURCE[63:0]; IF (COUNT > 31) THEN DEST[128:0]
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INSTRUCTION SET REFERENCE, N-Z PSLLD __m64 _mm_slli_pi32(__m64 m, int count) PSLLD __m64 _mm_sll_pi32(__m64 m, __m64 count) PSLLD __m128i _mm_slli_epi32(__m128i m, int count) PSLLD __m128i _mm_sll_epi32(__m128i m, __m128i count) PSLLQ __m64 _mm_slli_si64(__m64 m, int count) PSLLQ __m64 _mm_sll_si64(__m64 m, __m64 count) PSLLQ __m128i _mm_slli_si64(__m128i m, int count) PSLLQ __m128i _mm_sll_si64(__m128i m, __m128i count) Flags Affected None. Numeric Exceptions None.
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INSTRUCTION SET REFERENCE, N-Z #UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. (128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0. #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault. #AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made.
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INSTRUCTION SET REFERENCE, N-Z PSRAW/PSRAD—Shift Packed Data Right Arithmetic 64-Bit Mode Valid Compat/ Leg Mode Valid PSRAW xmm1, xmm2/m128 Valid Valid PSRAW mm, imm8 PSRAW xmm1, imm8 PSRAD mm, mm/m64 Valid Valid Valid Valid Valid Valid Opcode 0F E1 /r Instruction PSRAW mm, mm/m64 66 0F E1 /r 0F 71 /4 ib 66 0F 71 /4 ib 0F E2 /r 66 0F E2 /r PSRAD xmm1, xmm2/m128 Valid Valid 0F 72 /4 ib PSRAD mm, imm8 Valid Valid 66 0F 72 /4 ib PSRAD xmm1, imm8 Valid Valid Description Shift words
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INSTRUCTION SET REFERENCE, N-Z Pre-Shift DEST X3 X2 X3 >> COUNT X2 >> COUNT X1 X0 Shift Right with Sign Extension Post-Shift DEST X1 >> COUNT X0 >> COUNT Figure 4-9. PSRAW and PSRAD Instruction Operation Using a 64-bit Operand The destination operand may be an MMX technology register or an XMM register; the count operand can be either an MMX technology register or an 64-bit memory location, an XMM register or a 128-bit memory location, or an 8-bit immediate.
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INSTRUCTION SET REFERENCE, N-Z IF (COUNT > 15) THEN COUNT ← 16; FI; DEST[15:0] ← SignExtend(DEST[15:0] >> COUNT); (* Repeat shift operation for 2nd through 7th words *) DEST[127:112] ← SignExtend(DEST[127:112] >> COUNT); PSRAD instruction with 128-bit operand: COUNT ← COUNT_SOURCE[63:0]; IF (COUNT > 31) THEN COUNT ← 32; FI; DEST[31:0] ← SignExtend(DEST[31:0] >> COUNT); (* Repeat shift operation for 2nd and 3rd doublewords *) DEST[127:96] ← SignExtend(DEST[127:96] >>COUNT); Intel C/C++ Compiler Intrinsic E
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INSTRUCTION SET REFERENCE, N-Z #SS(0) #UD If a memory operand effective address is outside the SS segment limit. If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. (128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0. #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, N-Z #UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. (128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0. #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs. #AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol.
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INSTRUCTION SET REFERENCE, N-Z PSRLDQ—Shift Double Quadword Right Logical Opcode 66 0F 73 /3 ib Instruction PSRLDQ xmm1, imm8 64-Bit Mode Valid Compat/ Leg Mode Valid Description Shift xmm1 right by imm8 while shifting in 0s. Description Shifts the destination operand (first operand) to the right by the number of bytes specified in the count operand (second operand). The empty high-order bytes are cleared (set to all 0s).
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INSTRUCTION SET REFERENCE, N-Z Virtual-8086 Mode Exceptions Same exceptions as in Protected Mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. Numeric Exceptions None. Vol.
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INSTRUCTION SET REFERENCE, N-Z PSRLW/PSRLD/PSRLQ—Shift Packed Data Right Logical 64-Bit Mode Valid Compat/ Leg Mode Valid Opcode 0F D1 /r Instruction PSRLW mm, mm/m64 66 0F D1 /r PSRLW xmm1, xmm2/m128 Valid Valid 0F 71 /2 ib PSRLW mm, imm8 PSRLW xmm1, imm8 PSRLD mm, mm/m64 Valid Valid Valid Valid Valid Valid 66 0F 71 /2 ib 0F D2 /r 66 0F D2 /r PSRLD xmm1, xmm2/m128 Valid Valid 0F 72 /2 ib PSRLD mm, imm8 PSRLD xmm1, imm8 PSRLQ mm, mm/m64 PSRLQ xmm1, xmm2/m128 Valid Valid Valid Vali
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INSTRUCTION SET REFERENCE, N-Z The destination operand may be an MMX technology register or an XMM register; the count operand can be either an MMX technology register or an 64-bit memory location, an XMM register or a 128-bit memory location, or an 8-bit immediate. Note that only the first 64-bits of a 128-bit count operand are checked to compute the count. Pre-Shift DEST X3 X2 X3 >> COUNT X2 >> COUNT X1 X0 Shift Right with Zero Extension Post-Shift DEST X1 >> COUNT X0 >> COUNT Figure 4-10.
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INSTRUCTION SET REFERENCE, N-Z THEN DEST[64:0] ← 0000000000000000H ELSE DEST ← ZeroExtend(DEST >> COUNT); FI; PSRLW instruction with 128-bit operand: COUNT ← COUNT_SOURCE[63:0]; IF (COUNT > 15) THEN DEST[128:0] ← 00000000000000000000000000000000H ELSE DEST[15:0] ← ZeroExtend(DEST[15:0] >> COUNT); (* Repeat shift operation for 2nd through 7th words *) DEST[127:112] ← ZeroExtend(DEST[127:112] >> COUNT); FI; PSRLD instruction with 128-bit operand: COUNT ← COUNT_SOURCE[63:0]; IF (COUNT > 31) THEN DEST[128:0] ←
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INSTRUCTION SET REFERENCE, N-Z PSRLD __m64 _mm_srli_pi32 (__m64 m, int count) PSRLD __m64 _mm_srl_pi32 (__m64 m, __m64 count) PSRLD __m128i _mm_srli_epi32 (__m128i m, int count) PSRLD __m128i _mm_srl_epi32 (__m128i m, __m128i count) PSRLQ __m64 _mm_srli_si64 (__m64 m, int count) PSRLQ __m64 _mm_srl_si64 (__m64 m, __m64 count) PSRLQ __m128i _mm_srli_epi64 (__m128i m, int count) PSRLQ __m128i _mm_srl_epi64 (__m128i m, __m128i count) Flags Affected None. Numeric Exceptions None.
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INSTRUCTION SET REFERENCE, N-Z #UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. (128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0. #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault. #AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made.
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INSTRUCTION SET REFERENCE, N-Z PSUBB/PSUBW/PSUBD—Subtract Packed Integers 64-Bit Mode Valid Compat/ Leg Mode Valid Opcode 0F F8 /r Instruction PSUBB mm, mm/m64 66 0F F8 /r PSUBB xmm1, xmm2/m128 Valid Valid 0F F9 /r PSUBW mm, mm/m64 Valid Valid 66 0F F9 /r PSUBW xmm1, xmm2/m128 Valid Valid 0F FA /r PSUBD mm, mm/m64 Valid Valid 66 0F FA /r PSUBD xmm1, xmm2/m128 Valid Valid Description Subtract packed byte integers in mm/m64 from packed byte integers in mm.
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INSTRUCTION SET REFERENCE, N-Z The PSUBD instruction subtracts packed doubleword integers. When an individual result is too large or too small to be represented in a doubleword, the result is wrapped around and the low 32 bits are written to the destination element. Note that the PSUBB, PSUBW, and PSUBD instructions can operate on either unsigned or signed (two's complement notation) packed integers; however, it does not set bits in the EFLAGS register to indicate overflow and/or a carry.
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INSTRUCTION SET REFERENCE, N-Z Intel C/C++ Compiler Intrinsic Equivalents PSUBB __m64 _mm_sub_pi8(__m64 m1, __m64 m2) PSUBW __m64 _mm_sub_pi16(__m64 m1, __m64 m2) PSUBD __m64 _mm_sub_pi32(__m64 m1, __m64 m2) PSUBB __m128i _mm_sub_epi8 ( __m128i a, __m128i b) PSUBW __m128i _mm_sub_epi16 ( __m128i a, __m128i b) PSUBD __m128i _mm_sub_epi32 ( __m128i a, __m128i b) Flags Affected None. Numeric Exceptions None.
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INSTRUCTION SET REFERENCE, N-Z #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault. #AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same as for protected mode exceptions.
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INSTRUCTION SET REFERENCE, N-Z PSUBQ—Subtract Packed Quadword Integers Opcode 0F FB /r Instruction PSUBQ mm1, mm2/m64 66 0F FB /r PSUBQ xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Description Subtract quadword integer in mm1 from mm2 /m64. Subtract packed quadword integers in xmm1 from xmm2 /m128. Description Subtracts the second operand (source operand) from the first operand (destination operand) and stores the result in the destination operand.
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INSTRUCTION SET REFERENCE, N-Z Flags Affected None. Numeric Exceptions None. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. (128-bit operations only) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) #UD If a memory operand effective address is outside the SS segment limit. If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0.
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INSTRUCTION SET REFERENCE, N-Z Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. (128-bit operations only) If memory operand is not aligned on a 16-byte boundary, regardless of segment. #UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #NM If CR0.TS[bit 3] = 1.
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INSTRUCTION SET REFERENCE, N-Z PSUBSB/PSUBSW—Subtract Packed Signed Integers with Signed Saturation 64-Bit Mode Valid Compat/ Leg Mode Valid PSUBSB xmm1, xmm2/m128 Valid Valid 0F E9 /r PSUBSW mm, mm/m64 Valid Valid 66 0F E9 /r PSUBSW xmm1, xmm2/m128 Valid Valid Opcode 0F E8 /r Instruction PSUBSB mm, mm/m64 66 0F E8 /r Description Subtract signed packed bytes in mm/m64 from signed packed bytes in mm and saturate results.
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INSTRUCTION SET REFERENCE, N-Z In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).
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INSTRUCTION SET REFERENCE, N-Z #SS(0) #UD If a memory operand effective address is outside the SS segment limit. If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. (128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0. #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, N-Z #UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. (128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0. #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs. #AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol.
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INSTRUCTION SET REFERENCE, N-Z PSUBUSB/PSUBUSW—Subtract Packed Unsigned Integers with Unsigned Saturation 64-Bit Mode Valid Compat/ Leg Mode Valid PSUBUSB xmm1, xmm2/m128 Valid Valid 0F D9 /r PSUBUSW mm, mm/m64 Valid Valid 66 0F D9 /r PSUBUSW xmm1, xmm2/m128 Valid Valid Opcode 0F D8 /r Instruction PSUBUSB mm, mm/m64 66 0F D8 /r Description Subtract unsigned packed bytes in mm/m64 from unsigned packed bytes in mm and saturate result.
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INSTRUCTION SET REFERENCE, N-Z Operation PSUBUSB instruction with 64-bit operands: DEST[7:0] ← SaturateToUnsignedByte (DEST[7:0] − SRC (7:0] ); (* Repeat add operation for 2nd through 7th bytes *) DEST[63:56] ← SaturateToUnsignedByte (DEST[63:56] − SRC[63:56]; PSUBUSB instruction with 128-bit operands: DEST[7:0] ← SaturateToUnsignedByte (DEST[7:0] − SRC[7:0]); (* Repeat add operation for 2nd through 14th bytes *) DEST[127:120] ← SaturateToUnSignedByte (DEST[127:120] − SRC[127:120]); PSUBUSW instruction wit
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INSTRUCTION SET REFERENCE, N-Z #UD If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. (128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0. #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs. #AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
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INSTRUCTION SET REFERENCE, N-Z #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs. #AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol.
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INSTRUCTION SET REFERENCE, N-Z PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High Data 64-Bit Mode Valid Compat/ Leg Mode Valid PUNPCKHBW xmm1, xmm2/m128 Valid Valid 0F 69 /r PUNPCKHWD mm, mm/m64 Valid Valid 66 0F 69 /r PUNPCKHWD xmm1, xmm2/m128 Valid Valid 0F 6A /r PUNPCKHDQ mm, mm/m64 Valid Valid 66 0F 6A /r PUNPCKHDQ xmm1, xmm2/m128 Valid Valid 66 0F 6D /r PUNPCKHQDQ xmm1, xmm2/m128 Valid Valid Opcode 0F 68 /r Instruction PUNPCKHBW mm, mm/m64 66 0F 68 /r Description Unpack
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INSTRUCTION SET REFERENCE, N-Z The source operand can be an MMX technology register or a 64-bit memory location, or it can be an XMM register or a 128-bit memory location. The destination operand can be an MMX technology register or an XMM register. When the source data comes from a 64-bit memory operand, the full 64-bit operand is accessed from memory, but the instruction uses only the high-order 32 bits.
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INSTRUCTION SET REFERENCE, N-Z PUNPCKHDQ instruction with 64-bit operands: DEST[31:0] ← DEST[63:32]; DEST[63:32] ← SRC[63:32]; PUNPCKHBW instruction with 128-bit operands: DEST[7:0] ← DEST[71:64]; DEST[15:8] ← SRC[71:64]; DEST[23:16] ← DEST[79:72]; DEST[31:24] ← SRC[79:72]; DEST[39:32] ← DEST[87:80]; DEST[47:40] ← SRC[87:80]; DEST[55:48] ← DEST[95:88]; DEST[63:56] ← SRC[95:88]; DEST[71:64] ← DEST[103:96]; DEST[79:72] ← SRC[103:96]; DEST[87:80] ← DEST[111:104]; DEST[95:88] ← SRC[111:104]; DEST[103:96] ← DES
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INSTRUCTION SET REFERENCE, N-Z PUNPCKHWD __m64 _mm_unpackhi_pi16(__m64 m1,__m64 m2) PUNPCKHWD __m128i _mm_unpackhi_epi16(__m128i m1,__m128i m2) PUNPCKHDQ __m64 _mm_unpackhi_pi32(__m64 m1, __m64 m2) PUNPCKHDQ __m128i _mm_unpackhi_epi32(__m128i m1, __m128i m2) PUNPCKHQDQ __m128i _mm_unpackhi_epi64 ( __m128i a, __m128i b) Flags Affected None. Numeric Exceptions None. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
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INSTRUCTION SET REFERENCE, N-Z Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault. #AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form.
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INSTRUCTION SET REFERENCE, N-Z PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ— Unpack Low Data 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid PUNPCKLWD mm, mm/m32 PUNPCKLWD xmm1, xmm2/m128 Valid Valid Valid Valid Valid Valid 66 0F 62 /r PUNPCKLDQ mm, mm/m32 PUNPCKLDQ xmm1, xmm2/m128 Valid Valid 66 0F 6C /r PUNPCKLQDQ xmm1, xmm2/m128 Valid Valid Opcode 0F 60 /r 66 0F 60 /r 0F 61 /r 66 0F 61 /r 0F 62 /r Instruction PUNPCKLBW mm, mm/m32 PUNPCKLBW xmm1, xmm2/m128 Description Interleave low
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INSTRUCTION SET REFERENCE, N-Z The source operand can be an MMX technology register or a 32-bit memory location, or it can be an XMM register or a 128-bit memory location. The destination operand can be an MMX technology register or an XMM register. When the source data comes from a 128-bit memory operand, an implementation may fetch only the appropriate 64 bits; however, alignment to a 16-byte boundary and normal segment checking will still be enforced.
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INSTRUCTION SET REFERENCE, N-Z PUNPCKLBW instruction with 128-bit operands: DEST[7:0] ← DEST[7:0]; DEST[15:8] ← SRC[7:0]; DEST[23:16] ← DEST[15:8]; DEST[31:24] ← SRC[15:8]; DEST[39:32] ← DEST[23:16]; DEST[47:40] ← SRC[23:16]; DEST[55:48] ← DEST[31:24]; DEST[63:56] ← SRC[31:24]; DEST[71:64] ← DEST[39:32]; DEST[79:72] ← SRC[39:32]; DEST[87:80] ← DEST[47:40]; DEST[95:88] ← SRC[47:40]; DEST[103:96] ← DEST[55:48]; DEST[111:104] ← SRC[55:48]; DEST[119:112] ← DEST[63:56]; DEST[127:120] ← SRC[63:56]; PUNPCKLWD ins
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INSTRUCTION SET REFERENCE, N-Z PUNPCKLDQ __m64 _mm_unpacklo_pi32 (__m64 m1, __m64 m2) PUNPCKLDQ __m128i _mm_unpacklo_epi32 (__m128i m1, __m128i m2) PUNPCKLQDQ __m128i _mm_unpacklo_epi64 (__m128i m1, __m128i m2) Flags Affected None. Numeric Exceptions None. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. (128-bit operations only) If a memory operand is not aligned on a 16-byte boundary, regardless of segment.
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INSTRUCTION SET REFERENCE, N-Z Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault. #AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form.
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INSTRUCTION SET REFERENCE, N-Z PUSH—Push Word, Doubleword or Quadword Onto the Stack Opcode* FF /6 FF /6 FF /6 Instruction PUSH r/m16 PUSH r/m32 PUSH r/m64 64-Bit Mode Valid N.E. Valid Compat/ Leg Mode Valid Valid N.E. 50+rw 50+rd 50+rd PUSH r16 PUSH r32 PUSH r64 Valid N.E. Valid Valid Valid N.E.
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INSTRUCTION SET REFERENCE, N-Z Description Decrements the stack pointer and then stores the source operand on the top of the stack. The address-size attribute of the stack segment determines the stack pointer size (16, 32 or 64 bits). The operand-size attribute of the current code segment determines the amount the stack pointer is decremented (2, 4 or 8 bytes). In non-64-bit modes: if the address-size and operand-size attributes are 32, the 32-bit ESP register (stack pointer) is decremented by 4.
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INSTRUCTION SET REFERENCE, N-Z Operation IF StackAddrSize = 64 THEN IF OperandSize = 64 THEN RSP ← (RSP − 8); IF (SRC is FS or GS) THEN TEMP = ZeroExtend64(SRC); ELSE IF (SRC is IMMEDIATE) TEMP = SignExtend64(SRC); FI; ELSE TEMP = SRC; FI RSP ← TEMP; (* Push quadword *) ELSE (* OperandSize = 16; 66H used *) RSP ← (RSP − 2); RSP ← SRC; (* Push word *) FI; ELSE IF StackAddrSize = 32 THEN IF OperandSize = 32 THEN ESP ← (ESP − 4); IF (SRC is FS or GS) THEN TEMP = ZeroExtend32(SRC); ELSE IF (SRC is IMMEDIATE) T
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INSTRUCTION SET REFERENCE, N-Z SP ← (SP − 4); SS:SP ← SRC; (* Push doubleword *) FI; FI; FI; Flags Affected None. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, N-Z 64-Bit Mode Exceptions #GP(0) If the memory address is in a non-canonical form. #SS(U) If the stack address is in a non-canonical form. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 4-216 Vol.
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INSTRUCTION SET REFERENCE, N-Z PUSHA/PUSHAD—Push All General-Purpose Registers Opcode 60 Instruction PUSHA 64-Bit Mode Invalid Compat/ Leg Mode Valid 60 PUSHAD Invalid Valid Description Push AX, CX, DX, BX, original SP, BP, SI, and DI. Push EAX, ECX, EDX, EBX, original ESP, EBP, ESI, and EDI. Description Pushes the contents of the general-purpose registers onto the stack.
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INSTRUCTION SET REFERENCE, N-Z Push(ECX); Push(EDX); Push(EBX); Push(Temp); Push(EBP); Push(ESI); Push(EDI); ELSE (* OperandSize = 16, PUSHA instruction *) Temp ← (SP); Push(AX); Push(CX); Push(DX); Push(BX); Push(Temp); Push(BP); Push(SI); Push(DI); FI; Flags Affected None. Protected Mode Exceptions #SS(0) If the starting or ending stack address is outside the stack segment limit. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, N-Z Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #UD If in 64-bit mode. Vol.
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INSTRUCTION SET REFERENCE, N-Z PUSHF/PUSHFD—Push EFLAGS Register onto the Stack Opcode 9C 9C 9C Instruction PUSHF PUSHFD PUSHFQ 64-Bit Mode Valid N.E. Valid Compat/ Leg Mode Valid Valid N.E. Description Push lower 16 bits of EFLAGS. Push EFLAGS. Push RFLAGS.
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INSTRUCTION SET REFERENCE, N-Z Operation IF (PE = 0) or (PE = 1 and ((VM = 0) or (VM = 1 and IOPL = 3))) (* Real-Address Mode, Protected mode, or Virtual-8086 mode with IOPL equal to 3 *) THEN IF OperandSize = 32 THEN push (EFLAGS AND 00FCFFFFH); (* VM and RF EFLAG bits are cleared in image stored on the stack *) ELSE push (EFLAGS); (* Lower 16 bits only *) FI; ELSE IF 64-bit MODE (* In 64-bit Mode *) IF OperandSize = 64 THEN push (RFLAGS AND 00000000_00FCFFFFH); (* VM and RF RFLAG bits are cleared in imag
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INSTRUCTION SET REFERENCE, N-Z #AC(0) If an unaligned memory reference is made while alignment checking is enabled. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #GP(0) If the memory address is in a non-canonical form. #SS(U) If the stack address is in a non-canonical form. #PF(fault-code) If a page fault occurs. #AC(0) If an unaligned memory reference is made while the current privilege level is 3 and alignment checking is enabled. 4-222 Vol.
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INSTRUCTION SET REFERENCE, N-Z PXOR—Logical Exclusive OR Opcode 0F EF /r Instruction PXOR mm, mm/m64 64-Bit Mode Valid Compat/ Leg Mode Valid 66 0F EF /r PXOR xmm1, xmm2/m128 Valid Valid Description Bitwise XOR of mm/m64 and mm. Bitwise XOR of xmm2/m128 and xmm1. Description Performs a bitwise logical exclusive-OR (XOR) operation on the source operand (second operand) and the destination operand (first operand) and stores the result in the destination operand.
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INSTRUCTION SET REFERENCE, N-Z #SS(0) #UD If a memory operand effective address is outside the SS segment limit. If CR0.EM[bit 2] = 1. (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. (128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0. #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, N-Z (128-bit operations only) If CR4.OSFXSR[bit 9] = 0. (128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0. #NM If CR0.TS[bit 3] = 1. #MF (64-bit operations only) If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs. #AC(0) (64-bit operations only) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol.
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INSTRUCTION SET REFERENCE, N-Z RCL/RCR/ROL/ROR-—Rotate Compat/ Leg Mode Valid N.E. Valid Opcode** D0 /2 REX + D0 /2 D2 /2 Instruction RCL r/m8, 1 RCL r/m8*, 1 RCL r/m8, CL 64-Bit Mode Valid Valid Valid REX + D2 /2 RCL r/m8*, CL Valid N.E. C0 /2 ib Valid Valid Valid N.E. D1 /2 RCL r/m8, imm8 RCL r/m8*, imm8 RCL r/m16, 1 Valid Valid D3 /2 RCL r/m16, CL Valid Valid C1 /2 ib Valid Valid D1 /2 RCL r/m16, imm8 RCL r/m32, 1 Valid Valid REX.W + D1 /2 RCL r/m64, 1 Valid N.E.
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INSTRUCTION SET REFERENCE, N-Z 64-Bit Mode Valid Compat/ Leg Mode Valid Opcode** C0 /3 ib Instruction RCR r/m8, imm8 REX + C0 /3 ib Valid N.E. D1 /3 RCR r/m8*, imm8 RCR r/m16, 1 Valid Valid D3 /3 RCR r/m16, CL Valid Valid C1 /3 ib Valid Valid D1 /3 RCR r/m16, imm8 RCR r/m32, 1 Valid Valid REX.W + D1 /3 RCR r/m64, 1 Valid N.E. D3 /3 RCR r/m32, CL Valid Valid REX.W + D3 /3 RCR r/m64, CL Valid N.E.
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INSTRUCTION SET REFERENCE, N-Z Compat/ Leg Mode Valid Opcode** D3 /0 Instruction ROL r/m32, CL 64-Bit Mode Valid REX.W + D3 /0 ROL r/m64, CL Valid N.E. C1 /0 ib ROL r/m32, imm8 ROL r/m64, imm8 ROR r/m8, 1 ROR r/m8*, 1 ROR r/m8, CL ROR r/m8*, CL ROR r/m8, imm8 ROR r/m8*, imm8 ROR r/m16, 1 ROR r/m16, CL Valid Valid Valid N.E. Valid Valid Valid Valid Valid Valid N.E. Valid N.E. Valid Valid N.E. Valid Valid Valid Valid Valid Valid D1 /1 ROR r/m16, imm8 ROR r/m32, 1 Valid Valid REX.
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INSTRUCTION SET REFERENCE, N-Z Description Shifts (rotates) the bits of the first operand (destination operand) the number of bit positions specified in the second operand (count operand) and stores the result in the destination operand. The destination operand can be a register or a memory location; the count operand is an unsigned integer that can be an immediate or a value in the CL register.
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INSTRUCTION SET REFERENCE, N-Z SIZE ← 64: ESAC; tempCOUNT ← COUNT AND 3FH; (* RCL instruction operation *) WHILE (tempCOUNT ≠ 0) DO tempCF ← MSB(DEST); DEST ← (DEST ∗ 2) + CF; CF ← tempCF; tempCOUNT ← tempCOUNT – 1; OD; ELIHW; IF COUNT = 1 THEN OF ← MSB(DEST) XOR CF; ELSE OF is undefined; FI; (* RCR instruction operation *) IF COUNT = 1 THEN OF ← MSB(DEST) XOR CF; ELSE OF is undefined; FI; WHILE (tempCOUNT ≠ 0) DO tempCF ← LSB(SRC); DEST ← (DEST / 2) + (CF * 2SIZE); CF ← tempCF; tempCOUNT ← tempCOUNT – 1
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INSTRUCTION SET REFERENCE, N-Z tempCF ← MSB(DEST); DEST ← (DEST ∗ 2) + tempCF; tempCOUNT ← tempCOUNT – 1; OD; ELIHW; CF ← LSB(DEST); IF COUNT = 1 THEN OF ← MSB(DEST) XOR CF; ELSE OF is undefined; FI; FI; (* ROR instruction operation *) IF tempCOUNT > 0) (* Prevent updates to CF *) WHILE (tempCOUNT ≠ 0) DO tempCF ← LSB(SRC); DEST ← (DEST / 2) + (tempCF ∗ 2SIZE); tempCOUNT ← tempCOUNT – 1; OD; ELIHW; CF ← MSB(DEST); IF COUNT = 1 THEN OF ← MSB(DEST) XOR MSB − 1(DEST); ELSE OF is undefined; FI; FI; Flags Affe
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INSTRUCTION SET REFERENCE, N-Z #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
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INSTRUCTION SET REFERENCE, N-Z RCPPS—Compute Reciprocals of Packed Single-Precision FloatingPoint Values Opcode 0F 53 /r Instruction RCPPS xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Computes the approximate reciprocals of the packed single-precision floatingpoint values in xmm2/m128 and stores the results in xmm1.
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INSTRUCTION SET REFERENCE, N-Z SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0.
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INSTRUCTION SET REFERENCE, N-Z #NM #UD If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Vol.
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INSTRUCTION SET REFERENCE, N-Z RCPSS—Compute Reciprocal of Scalar Single-Precision Floating-Point Values Opcode F3 0F 53 /r Instruction RCPSS xmm1, xmm2/m32 64-Bit Mode Valid Compat/ Leg Mode Valid Description Computes the approximate reciprocal of the scalar single-precision floating-point value in xmm2/m32 and stores the result in xmm1.
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INSTRUCTION SET REFERENCE, N-Z SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0.
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INSTRUCTION SET REFERENCE, N-Z #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) 4-238 Vol. 2B If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
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INSTRUCTION SET REFERENCE, N-Z RDMSR—Read from Model Specific Register Opcode* 0F 32 Instruction RDMSR 64-Bit Mode Valid Compat/ Leg Mode Valid REX.W + 0F 32 RDMSR Valid N.E. Description Load MSR specified by ECX into EDX:EAX. Load MSR specified by RCX into RDX:RAX. NOTES: * See IA-32 Architecture Compatibility section below. Description Loads the contents of a 64-bit model specific register (MSR) specified in an index register into registers EDX:EAX.
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INSTRUCTION SET REFERENCE, N-Z Operation IF 64-Bit Mode and REX.W used THEN RAX[31:0] ← MSR(RCX)[31:0]; RAX[63:32] ← 0]; RDX[31:0] ← MSR(RCX)[63:32]; RDX[63:32] ← 0]; ELSE (* Non-64-bit modes, 64-bit mode default *) EDX-EAX ← MSR[ECX]; FI; Flags Affected None. Protected Mode Exceptions #GP(0) If the current privilege level is not 0. If the value in ECX specifies a reserved or unimplemented MSR address.
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INSTRUCTION SET REFERENCE, N-Z RDPMC—Read Performance-Monitoring Counters Opcode 0F 33 Instruction RDPMC 64-Bit Mode Valid Compat/ Leg Mode Valid Description Read performance-monitoring counter specified by ECX into EDX:EAX. Description Loads the 40-bit performance-monitoring counter specified in the ECX register into registers EDX:EAX. The EDX register is loaded with the high-order 8 bits of the counter and the EAX register is loaded with the low-order 32 bits.
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INSTRUCTION SET REFERENCE, N-Z The Pentium 4 and Intel Xeon processors also support “fast” (32-bit) and “slow” (40-bit) reads on the first 18 performance counters. Selected this option using ECX[bit 31]. If bit 31 is set, RDPMC reads only the low 32 bits of the selected performance counter. If bit 31 is clear, all 40 bits are read. A 32-bit result is returned in EAX and EDX is set to 0. A 32-bit read executes faster on Pentium 4 processors and Intel Xeon processors than a full 40-bit read.
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INSTRUCTION SET REFERENCE, N-Z EAX ← IA32_FIXED_CTR(ECX)[30:0]; EDX ← IA32_FIXED_CTR(ECX)[39:32]; ELSE IF (ECX[30:0] in valid range) EAX ← PMC(ECX[30:0])[31:0]; EDX ← PMC(ECX[30:0])[39:32]; ELSE (* ECX is not valid or CR4.PCE is 0 and CPL is 1, 2, or 3 and CR0.PE is 1 *) #GP(0); FI; (* P6 family processors and Pentium processor with MMX technology *) IF (ECX = 0 or 1) and ((CR4.PCE = 1) or (CPL = 0) or (CR0.PE = 0)) THEN EAX ← PMC(ECX)[31:0]; EDX ← PMC(ECX)[39:32]; ELSE (* ECX is not 0 or 1 or CR4.
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INSTRUCTION SET REFERENCE, N-Z THEN IF (ECX[30:0] = 18:25 EAX ← PMC(ECX[30:0])[31:0]; (* 32-bit read *) EDX ← 0; FI; ELSE (* Invalid PMC index in ECX[30:0], see Table 4-4. *) GP(0); FI; ELSE (* CR4.PCE = 0 and (CPL = 1, 2, or 3) and CR0.PE = 1 *) #GP(0); FI; Flags Affected None. Protected Mode Exceptions #GP(0) If the current privilege level is not 0 and the PCE flag in the CR4 register is clear. If an invalid performance counter index is specified (see Table 4-2).
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INSTRUCTION SET REFERENCE, N-Z 64-Bit Mode Exceptions #GP(0) If the current privilege level is not 0 and the PCE flag in the CR4 register is clear. If an invalid performance counter index is specified in ECX[30:0] (see Table 4-2). Vol.
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INSTRUCTION SET REFERENCE, N-Z RDTSC—Read Time-Stamp Counter Opcode 0F 31 Instruction RDTSC 64-Bit Mode Valid Compat/ Leg Mode Valid Description Read time-stamp counter into EDX:EAX. Description In legacy, compatibility and default 64-bit mode; loads the current value of the processor’s time-stamp counter into the EDX:EAX registers. The time-stamp counter is contained in a 64-bit MSR.
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INSTRUCTION SET REFERENCE, N-Z RDX[31:0] ← TimeStampCounter[63:32]; RDX[63:32] ← 0; ELSE EDX:EAX ← TimeStampCounter; FI; ELSE (* CR4.TSD = 1 and (CPL = 1, 2, or 3) and CR0.PE = 1 *) #GP(0); FI; Flags Affected None. Protected Mode Exceptions #GP(0) If the TSD flag in register CR4 is set and the CPL is greater than 0. Real-Address Mode Exceptions None. Virtual-8086 Mode Exceptions #GP(0) If the TSD flag in register CR4 is set. Compatibility Mode Exceptions Same exceptions as in Protected Mode.
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INSTRUCTION SET REFERENCE, N-Z REP/REPE/REPZ/REPNE/REPNZ—Repeat String Operation Prefix Opcode F3 6C Instruction REP INS m8, DX 64-Bit Mode Valid Compat/ Leg Mode Valid F3 6C REP INS m8, DX Valid N.E. F3 6D REP INS m16, DX Valid Valid F3 6D REP INS m32, DX Valid Valid F3 6D REP INS r/m32, DX Valid N.E. F3 A4 REP MOVS m8, m8 Valid Valid F3 REX.W A4 REP MOVS m8, m8 Valid N.E. F3 A5 Valid Valid Valid Valid Valid N.E. Valid Valid Valid N.E.
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INSTRUCTION SET REFERENCE, N-Z Opcode F3 AA Instruction REP STOS m8 64-Bit Mode Valid Compat/ Leg Mode Valid F3 REX.W AA F3 AB REP STOS m8 REP STOS m16 Valid Valid N.E. Valid F3 AB REP STOS m32 Valid Valid F3 REX.W AB REP STOS m64 Valid N.E. F3 A6 REPE CMPS m8, m8 REPE CMPS m8, m8 REPE CMPS m16, m16 REPE CMPS m32, m32 Valid Valid Valid N.E. Valid Valid Valid Valid Valid N.E. F3 AE REPE CMPS m64, m64 REPE SCAS m8 Valid Valid F3 REX.W AE REPE SCAS m8 Valid N.E.
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INSTRUCTION SET REFERENCE, N-Z Opcode F2 AE F2 REX.W AE F2 AF F2 AF F2 REX.W AF Instruction REPNE SCAS m8 REPNE SCAS m8 REPNE SCAS m16 REPNE SCAS m32 REPNE SCAS m64 64-Bit Mode Valid Valid Valid Valid Valid Compat/ Leg Mode Valid N.E. Valid Valid N.E. Description Find AL, starting at ES:[(E)DI]. Find AL, starting at [RDI]. Find AX, starting at ES:[(E)DI]. Find EAX, starting at ES:[(E)DI]. Find RAX, starting at [RDI].
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INSTRUCTION SET REFERENCE, N-Z be determined either by testing the count register with a JECXZ instruction or by testing the ZF flag (with a JZ, JNZ, or JNE instruction). When the REPE/REPZ and REPNE/REPNZ prefixes are used, the ZF flag does not require initialization because both the CMPS and SCAS instructions affect the ZF flag according to the results of the comparisons they make. A repeating string operation can be suspended by an exception or interrupt.
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INSTRUCTION SET REFERENCE, N-Z OD; THEN exit WHILE loop; FI; IF (Repeat prefix is REPZ or REPE) and (ZF = 0) or (Repeat prefix is REPNZ or REPNE) and (ZF = 1) THEN exit WHILE loop; FI; Flags Affected None; however, the CMPS and SCAS instructions do set the status flags in the EFLAGS register. Exceptions (All Operating Modes) None; however, exceptions can be generated by the instruction a repeat prefix is associated with. 64-Bit Mode Exceptions #GP(0) 4-252 Vol.
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INSTRUCTION SET REFERENCE, N-Z RET—Return from Procedure Opcode C3 CB C2 iw Instruction RET RET RET imm16 64-Bit Mode Valid Valid Valid Compat/ Leg Mode Valid Valid Valid CA iw RET imm16 Valid Valid Description Near return to calling procedure. Far return to calling procedure. Near return to calling procedure and pop imm16 bytes from stack. Far return to calling procedure and pop imm16 bytes from stack. Description Transfers program control to a return address located on the top of the stack.
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INSTRUCTION SET REFERENCE, N-Z The mechanics of an inter-privilege-level far return are similar to an intersegment return, except that the processor examines the privilege levels and access rights of the code and stack segments being returned to determine if the control transfer is allowed to be made. The DS, ES, FS, and GS segment registers are cleared by the RET instruction during an inter-privilege-level return if they refer to segments that are not allowed to be accessed at the new privilege level.
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INSTRUCTION SET REFERENCE, N-Z IF instruction has immediate operand THEN IF StackAddressSize = 32 THEN ESP ← ESP + SRC; (* Release parameters from stack *) ELSE IF StackAddressSize = 64 THEN RSP ← RSP + SRC; (* Release parameters from stack *) ELSE (* StackAddressSize = 16 *) SP ← SP + SRC; (* Release parameters from stack *) FI; FI; FI; FI; (* Real-address mode or virtual-8086 mode *) IF ((PE = 0) or (PE = 1 AND VM = 1)) and instruction = far return THEN IF OperandSize = 32 THEN IF top 12 bytes of stack n
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INSTRUCTION SET REFERENCE, N-Z IF OperandSize = 32 THEN IF second doubleword on stack is not within stack limits THEN #SS(0); FI; ELSE (* OperandSize = 16 *) IF second word on stack is not within stack limits THEN #SS(0); FI; FI; IF return code segment selector is NULL THEN #GP(0); FI; IF return code segment selector addresses descriptor beyond descriptor table limit THEN #GP(selector); FI; Obtain descriptor to which return code segment selector points from descriptor table; IF return code segment descript
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INSTRUCTION SET REFERENCE, N-Z FI; RETURN-OUTER-PRIVILEGE-LEVEL: IF top (16 + SRC) bytes of stack are not within stack limits (OperandSize = 32) or top (8 + SRC) bytes of stack are not within stack limits (OperandSize = 16) THEN #SS(0); FI; Read return segment selector; IF stack segment selector is NULL THEN #GP(0); FI; IF return stack segment selector index is not within its descriptor table limits THEN #GP(selector); FI; Read segment descriptor pointed to by return segment selector; IF stack segment sele
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INSTRUCTION SET REFERENCE, N-Z FI; FOR each of segment register (ES, FS, GS, and DS) DO IF segment register points to data or non-conforming code segment and CPL > segment descriptor DPL (* DPL in hidden part of segment register *) THEN SegmentSelector ← 0; (* Segment selector invalid *) FI; OD; For each of ES, FS, GS, and DS DO IF segment selector index is not within descriptor table limits or segment descriptor indicates the segment is not a data or readable code segment or if the segment is a data or no
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INSTRUCTION SET REFERENCE, N-Z THEN GP(0); FI; IF return code segment selector addresses descriptor beyond descriptor table limit THEN GP(selector); FI; IF return code segment selector addresses descriptor in non-canonical space THEN GP(selector); FI; Obtain descriptor to which return code segment selector points from descriptor table; IF return code segment descriptor is not a code segment THEN #GP(selector); FI; IF return code segment descriptor has L-bit = 1 and D-bit = 1 THEN #GP(selector); FI; IF retu
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INSTRUCTION SET REFERENCE, N-Z ELSE (* OperandSize = 64 *) RIP ← Pop(); CS ← Pop(); (* 64-bit pop, high-order 48 bits discarded *) ESP ← ESP + SRC; (* Release parameters from stack *) FI; FI; IA-32E-MODE-RETURN-OUTER-PRIVILEGE-LEVEL: IF top (16 + SRC) bytes of stack are not within stack limits (OperandSize = 32) or top (8 + SRC) bytes of stack are not within stack limits (OperandSize = 16) THEN #SS(0); FI; IF top (16 + SRC) bytes of stack are not in canonical address space (OperandSize = 32) or top (8 + SR
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INSTRUCTION SET REFERENCE, N-Z information also loaded *) CS(RPL) ← CPL; ESP ← ESP + SRC; (* Release parameters from called procedure’s stack *) tempESP ← Pop(); tempSS ← Pop(); (* 32-bit pop, high-order 16 bits discarded, segment descriptor information also loaded *) ESP ← tempESP; SS ← tempSS; ELSE IF OperandSize = 16 THEN EIP ← Pop(); EIP ← EIP AND 0000FFFFH; CS ← Pop(); (* 16-bit pop; segment descriptor information also loaded *) CS(RPL) ← CPL; ESP ← ESP + SRC; (* release parameters from called procedu
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INSTRUCTION SET REFERENCE, N-Z For each of ES, FS, GS, and DS DO IF segment selector index is not within descriptor table limits or segment descriptor indicates the segment is not a data or readable code segment or if the segment is a data or non-conforming code segment and the segment descriptor’s DPL < CPL or RPL of code segment’s segment selector THEN SegmentSelector ← 0; (* SegmentSelector invalid *) OD; ESP ESP + SRC; (* Release parameters from calling procedure’s stack *) Flags Affected None.
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INSTRUCTION SET REFERENCE, N-Z Real-Address Mode Exceptions #GP If the return instruction pointer is not within the return code segment limit #SS If the top bytes of stack are not within stack limits. Virtual-8086 Mode Exceptions #GP(0) If the return instruction pointer is not within the return code segment limit #SS(0) If the top bytes of stack are not within stack limits. #PF(fault-code) If a page fault occurs. #AC(0) If an unaligned memory access occurs when alignment checking is enabled.
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INSTRUCTION SET REFERENCE, N-Z If the stack segment descriptor DPL is not equal to the RPL of the return code segment selector. If the stack segment selector RPL is not equal to the RPL of the return code segment selector. #SS(0) If an attempt to pop a value off the stack violates the SS limit. If an attempt to pop a value off the stack causes a non-canonical address to be referenced. #NP(selector) If the return code or stack segment is not present. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, N-Z RSM—Resume from System Management Mode Opcode 0F AA Instruction RSM NonSMM Mode Invalid SMM Mode Valid Description Resume operation of interrupted program. Description Returns program control from system management mode (SMM) to the application program or operating-system procedure that was interrupted when the processor received an SMM interrupt. The processor’s state is restored from the dump created upon entering SMM.
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INSTRUCTION SET REFERENCE, N-Z Protected Mode Exceptions #UD If an attempt is made to execute this instruction when the processor is not in SMM. Real-Address Mode Exceptions Same exceptions as in Protected Mode. Virtual-8086 Mode Exceptions Same exceptions as in Protected Mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. 4-266 Vol.
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INSTRUCTION SET REFERENCE, N-Z RSQRTPS—Compute Reciprocals of Square Roots of Packed SinglePrecision Floating-Point Values Opcode 0F 52 /r Instruction RSQRTPS xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Computes the approximate reciprocals of the square roots of the packed single-precision floatingpoint values in xmm2/m128 and stores the results in xmm1.
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INSTRUCTION SET REFERENCE, N-Z SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0.
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INSTRUCTION SET REFERENCE, N-Z #NM #UD If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Vol.
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INSTRUCTION SET REFERENCE, N-Z RSQRTSS—Compute Reciprocal of Square Root of Scalar SinglePrecision Floating-Point Value Opcode F3 0F 52 /r Instruction RSQRTSS xmm1, xmm2/m32 64-Bit Mode Valid Compat/ Leg Mode Valid Description Computes the approximate reciprocal of the square root of the low singleprecision floating-point value in xmm2/m32 and stores the results in xmm1.
PAGE 273
INSTRUCTION SET REFERENCE, N-Z SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0.
PAGE 274
INSTRUCTION SET REFERENCE, N-Z #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) 4-272 Vol. 2B If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
PAGE 275
INSTRUCTION SET REFERENCE, N-Z SAHF—Store AH into Flags Opcode 9E Instruction SAHF 64-Bit Mode Invalid* Compat/ Leg Mode Valid Description Loads SF, ZF, AF, PF, and CF from AH into EFLAGS register. NOTE: * Valid in specific steppings. See Description section. Description Loads the SF, ZF, AF, PF, and CF flags of the EFLAGS register with values from the corresponding bits in the AH register (bits 7, 6, 4, 2, and 0, respectively).
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INSTRUCTION SET REFERENCE, N-Z Virtual-8086 Mode Exceptions None. Compatibility Mode Exceptions None. 64-Bit Mode Exceptions #UD 4-274 Vol. 2B If CPUID.80000001.ECX[0] = 0.
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INSTRUCTION SET REFERENCE, N-Z SAL/SAR/SHL/SHR—Shift Opcode*** D0 /4 REX + D0 /4 D2 /4 REX + D2 /4 C0 /4 ib Instruction SAL r/m8, 1 SAL r/m8**, 1 SAL r/m8, CL SAL r/m8**, CL SAL r/m8, imm8 64-Bit Mode Valid Valid Valid Valid Valid Compat/ Leg Mode Valid N.E. Valid N.E. Valid REX + C0 /4 ib SAL r/m8**, imm8 Valid N.E. D1 /4 D3 /4 SAL r/m16, 1 SAL r/m16, CL Valid Valid Valid Valid C1 /4 ib SAL r/m16, imm8 Valid Valid D1 /4 REX.
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INSTRUCTION SET REFERENCE, N-Z Opcode D3 /7 Instruction SAR r/m16, CL 64-Bit Mode Valid Compat/ Leg Mode Valid C1 /7 ib SAR r/m16, imm8 Valid Valid D1 /7 SAR r/m32, 1 Valid Valid REX.W + D1 /7 SAR r/m64, 1 Valid N.E. D3 /7 SAR r/m32, CL Valid Valid REX.W + D3 /7 SAR r/m64, CL Valid N.E. C1 /7 ib SAR r/m32, imm8 Valid Valid REX.W + C1 /7 ib SAR r/m64, imm8 Valid N.E.
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INSTRUCTION SET REFERENCE, N-Z Opcode D0 /5 Instruction SHR r/m8,1 64-Bit Mode Valid Compat/ Leg Mode Valid REX + D0 /5 SHR r/m8**, 1 Valid N.E. D2 /5 SHR r/m8, CL Valid Valid REX + D2 /5 SHR r/m8**, CL Valid N.E. C0 /5 ib SHR r/m8, imm8 Valid Valid REX + C0 /5 ib Valid N.E. D1 /5 SHR r/m8**, imm8 SHR r/m16, 1 Valid Valid D3 /5 SHR r/m16, CL Valid Valid C1 /5 ib SHR r/m16, imm8 Valid Valid D1 /5 SHR r/m32, 1 Valid Valid REX.W + D1 /5 SHR r/m64, 1 Valid N.E.
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INSTRUCTION SET REFERENCE, N-Z the end of the shift operation, the CF flag contains the last bit shifted out of the destination operand. The destination operand can be a register or a memory location. The count operand can be an immediate value or the CL register. The count is masked to 5 bits (or 6 bits if in 64-bit mode and REX.W is used). The count range is limited to 0 to 31 (or 63 if 64-bit mode and REX.W is used). A special opcode encoding is provided for a count of 1.
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INSTRUCTION SET REFERENCE, N-Z 64-bits and sets the mask width for CL to 6 bits. See the summary chart at the beginning of this section for encoding data and limits. IA-32 Architecture Compatibility The 8086 does not mask the shift count. However, all other IA-32 processors (starting with the Intel 286 processor) do mask the shift count to 5 bits, resulting in a maximum count of 31.
PAGE 282
INSTRUCTION SET REFERENCE, N-Z THEN IF instruction is SAL or SHL THEN OF ← MSB(DEST) XOR CF; ELSE IF instruction is SAR THEN OF ← 0; ELSE (* Instruction is SHR *) OF ← MSB(tempDEST); FI; FI; ELSE IF (COUNT AND countMASK) = 0 THEN All flags unchanged; ELSE (* COUNT not 1 or 0 *) OF ← undefined; FI; FI; Flags Affected The CF flag contains the value of the last bit shifted out of the destination operand; it is undefined for SHL and SHR instructions where the count is greater than or equal to the size (in bit
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INSTRUCTION SET REFERENCE, N-Z Real-Address Mode Exceptions #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, N-Z SBB—Integer Subtraction with Borrow Opcode 1C ib Instruction SBB AL, imm8 64-Bit Mode Valid Compat/ Leg Mode Valid 1D iw SBB AX, imm16 Valid Valid 1D id SBB EAX, imm32 Valid Valid REX.W + 1D id SBB RAX, imm32 Valid N.E. 80 /3 ib SBB r/m8, imm8 Valid Valid REX + 80 /3 ib SBB r/m8*, imm8 Valid N.E. 81 /3 iw SBB r/m16, imm16 SBB r/m32, imm32 SBB r/m64, imm32 Valid Valid Valid Valid Valid N.E.
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INSTRUCTION SET REFERENCE, N-Z Opcode REX.W + 19 /r Instruction SBB r/m64, r64 64-Bit Mode Valid Compat/ Leg Mode N.E. 1A /r SBB r8, r/m8 Valid Valid REX + 1A /r SBB r8*, r/m8* Valid N.E. 1B /r SBB r16, r/m16 Valid Valid 1B /r SBB r32, r/m32 Valid Valid REX.W + 1B /r SBB r64, r/m64 Valid N.E. Description Subtract with borrow r64 from r/m64. Subtract with borrow r/m8 from r8. Subtract with borrow r/m8 from r8. Subtract with borrow r/m16 from r16. Subtract with borrow r/m32 from r32.
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INSTRUCTION SET REFERENCE, N-Z Operation DEST ← (DEST – (SRC + CF)); Flags Affected The OF, SF, ZF, AF, PF, and CF flags are set according to the result. Protected Mode Exceptions #GP(0) If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit.
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INSTRUCTION SET REFERENCE, N-Z #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.+ Vol.
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INSTRUCTION SET REFERENCE, N-Z SCAS/SCASB/SCASW/SCASD—Scan String Opcode AE Instruction SCAS m8 64-Bit Mode Valid Compat/ Leg Mode Valid AF SCAS m16 Valid Valid AF SCAS m32 Valid Valid REX.W + AF SCAS m64 Valid N.E. AE SCASB Valid Valid AF SCASW Valid Valid AF SCASD Valid Valid REX.W + AF SCASQ Valid N.E. Description Compare AL with byte at ES:(E)DI or RDI, then set status flags1. Compare AX with word at ES:(E)DI or RDI, then set status flags.
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INSTRUCTION SET REFERENCE, N-Z The no-operands form of the instruction uses a short form of SCAS. Again, ES:(E)DI is assumed to be the memory operand and AL, AX, or EAX is assumed to be the register operand. The size of operands is selected by the mnemonic: SCASB (byte comparison), SCASW (word comparison), or SCASD (doubleword comparison). After the comparison, the (E)DI register is incremented or decremented automatically according to the setting of the DF flag in the EFLAGS register.
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INSTRUCTION SET REFERENCE, N-Z temp ← EAX – SRC; SetStatusFlags(temp); IF DF = 0 THEN (E)DI ← (E)DI + 4; ELSE (E)DI ← (E)DI – 4; FI; FI; FI; 64-bit Mode: IF (Byte cmparison) THEN temp ← AL − SRC; SetStatusFlags(temp); THEN IF DF = 0 THEN (R|E)DI ← (R|E)DI + 1; ELSE (R|E)DI ← (R|E)DI – 1; FI; ELSE IF (Word comparison) THEN temp ← AX − SRC; SetStatusFlags(temp); IF DF = 0 THEN (R|E)DI ← (R|E)DI + 2; ELSE (R|E)DI ← (R|E)DI – 2; FI; FI; ELSE IF (Doubleword comparison) THEN temp ← EAX – SRC; SetStatusFlags(temp
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INSTRUCTION SET REFERENCE, N-Z Flags Affected The OF, SF, ZF, AF, PF, and CF flags are set according to the temporary result of the comparison. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the limit of the ES segment. If the ES register contains a NULL segment selector. If an illegal memory operand effective address in the ES segment is given. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, N-Z SETcc—Set Byte on Condition Opcode 0F 97 Instruction SETA r/m8 64-Bit Mode Valid Compat/ Leg Mode Valid REX + 0F 97 SETA r/m8* Valid N.E. 0F 93 SETAE r/m8 Valid Valid REX + 0F 93 SETAE r/m8* Valid N.E. 0F 92 REX + 0F 92 0F 96 SETB r/m8 SETB r/m8* SETBE r/m8 Valid Valid Valid Valid N.E. Valid REX + 0F 96 SETBE r/m8* Valid N.E.
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INSTRUCTION SET REFERENCE, N-Z Opcode REX + 0F 92 Instruction SETNAE r/m8* 64-Bit Mode Valid Compat/ Leg Mode N.E. 0F 93 REX + 0F 93 0F 97 SETNB r/m8 SETNB r/m8* SETNBE r/m8 Valid Valid Valid Valid N.E. Valid REX + 0F 97 SETNBE r/m8* Valid N.E. 0F 93 REX + 0F 93 0F 95 REX + 0F 95 0F 9E SETNC r/m8 SETNC r/m8* SETNE r/m8 SETNE r/m8* SETNG r/m8 Valid Valid Valid Valid Valid Valid N.E. Valid N.E. Valid REX + 0F 9E SETNG r/m8* Valid N.E.
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INSTRUCTION SET REFERENCE, N-Z Opcode REX + 0F 9A 0F 9B REX + 0F 9B 0F 98 REX + 0F 98 0F 94 REX + 0F 94 Instruction SETPE r/m8* SETPO r/m8 SETPO r/m8* SETS r/m8 SETS r/m8* SETZ r/m8 SETZ r/m8* 64-Bit Mode Valid Valid Valid Valid Valid Valid Valid Compat/ Leg Mode N.E. Valid N.E. Valid N.E. Valid N.E. Description Set byte if parity even (PF=1). Set byte if parity odd (PF=0). Set byte if parity odd (PF=0). Set byte if sign (SF=1). Set byte if sign (SF=1). Set byte if zero (ZF=1). Set byte if zero (ZF=1).
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INSTRUCTION SET REFERENCE, N-Z Flags Affected None. Protected Mode Exceptions #GP(0) If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, N-Z SFENCE—Store Fence Opcode 0F AE /7 Instruction SFENCE 64-Bit Mode Valid Compat /Leg Mode Valid Description Serializes store operations. Description Performs a serializing operation on all store-to-memory instructions that were issued prior the SFENCE instruction.
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INSTRUCTION SET REFERENCE, N-Z SGDT—Store Global Descriptor Table Register Opcode* 0F 01 /0 Instruction SGDT m 64-Bit Mode Valid Compat/ Leg Mode Valid Description Store GDTR to m. NOTES: * See IA-32 Architecture Compatibility section below. Description Stores the content of the global descriptor table register (GDTR) in the destination operand. The destination operand specifies a memory location. In legacy or compatibility mode, the destination operand is a 6-byte memory location.
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INSTRUCTION SET REFERENCE, N-Z DEST[16:47] ← GDTR(Base); (* Full 32-bit base address stored *) FI; ELSE (* 64-bit Operand Size *) DEST[0:15] ← GDTR(Limit); DEST[16:79] ← GDTR(Base); (* Full 64-bit base address stored *) FI; FI; Flags Affected None. Protected Mode Exceptions #UD If the destination operand is a register. #GP(0) If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
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INSTRUCTION SET REFERENCE, N-Z Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #UD If the destination operand is a register. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol.
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INSTRUCTION SET REFERENCE, N-Z SHLD—Double Precision Shift Left 64-Bit Mode Valid Compat/ Leg Mode Valid SHLD r/m16, r16, CL Valid Valid 0F A4 SHLD r/m32, r32, imm8 Valid Valid REX.W + 0F A4 SHLD r/m64, r64, imm8 Valid N.E. 0F A5 SHLD r/m32, r32, CL Valid Valid REX.W + 0F A5 SHLD r/m64, r64, CL Valid N.E. Opcode 0F A4 Instruction SHLD r/m16, r16, imm8 0F A5 Description Shift r/m16 to left imm8 places while shifting bits from r16 in from the right.
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INSTRUCTION SET REFERENCE, N-Z Operation IF (In 64-Bit Mode and REX.
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INSTRUCTION SET REFERENCE, N-Z #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit.
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INSTRUCTION SET REFERENCE, N-Z SHRD—Double Precision Shift Right 64-Bit Mode Valid Compat/ Leg Mode Valid SHRD r/m16, r16, CL Valid Valid 0F AC SHRD r/m32, r32, mm8 Valid Valid REX.W + 0F AC SHRD r/m64, r64, imm8 Valid N.E. 0F AD SHRD r/m32, r32, CL Valid Valid REX.W + 0F AD SHRD r/m64, r64, CL Valid N.E. Opcode 0F AC Instruction SHRD r/m16, r16, imm8 0F AD Description Shift r/m16 to right imm8 places while shifting bits from r16 in from the left.
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INSTRUCTION SET REFERENCE, N-Z to 6 bits). See the summary chart at the beginning of this section for encoding data and limits. Operation IF (In 64-Bit Mode and REX.
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INSTRUCTION SET REFERENCE, N-Z If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
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INSTRUCTION SET REFERENCE, N-Z SHUFPD—Shuffle Packed Double-Precision Floating-Point Values Opcode 66 0F C6 /r ib Instruction SHUFPD xmm1, xmm2/m128, imm8 64Bit Mode Valid Compat/ Leg Mode Valid Description Shuffle packed doubleprecision floating-point values selected by imm8 from xmm1 and xmm2/m128 to xmm1.
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INSTRUCTION SET REFERENCE, N-Z Operation IF SELECT[0] = 0 THEN DEST[63:0] ← DEST[63:0]; ELSE DEST[63:0] ← DEST[127:64]; FI; IF SELECT[1] = 0 THEN DEST[127:64] ← SRC[63:0]; ELSE DEST[127:64] ← SRC[127:64]; FI; Intel C/C++ Compiler Intrinsic Equivalent SHUFPD __m128d _mm_shuffle_pd(__m128d a, __m128d b, unsigned int imm8) SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
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INSTRUCTION SET REFERENCE, N-Z #PF(fault-code) For a page fault. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If memory operand is not aligned on a 16-byte boundary, regardless of segment. If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.
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INSTRUCTION SET REFERENCE, N-Z SHUFPS—Shuffle Packed Single-Precision Floating-Point Values Opcode 0F C6 /r ib Instruction SHUFPS xmm1, xmm2/m128, imm8 64-Bit Mode Valid Compat/ Leg Mode Valid Description Shuffle packed single-precision floating-point values selected by imm8 from xmm1 and xmm1/m128 to xmm1.
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INSTRUCTION SET REFERENCE, N-Z Operation CASE (SELECT[1:0]) OF 0: DEST[31:0] ← DEST[31:0]; 1: DEST[31:0] ← DEST[63:32]; 2: DEST[31:0] ← DEST[95:64]; 3: DEST[31:0] ← DEST[127:96]; ESAC; CASE (SELECT[3:2]) OF 0: DEST[63:32] ← DEST[31:0]; 1: DEST[63:32] ← DEST[63:32]; 2: DEST[63:32] ← DEST[95:64]; 3: DEST[63:32] ← DEST[127:96]; ESAC; CASE (SELECT[5:4]) OF 0: DEST[95:64] ← SRC[31:0]; 1: DEST[95:64] ← SRC[63:32]; 2: DEST[95:64] ← SRC[95:64]; 3: DEST[95:64] ← SRC[127:96]; ESAC; CASE (SELECT[7:6]) OF 0: DEST[127:
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INSTRUCTION SET REFERENCE, N-Z #NM #UD If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0.
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INSTRUCTION SET REFERENCE, N-Z SIDT—Store Interrupt Descriptor Table Register Opcode 0F 01 /1 Instruction SIDT m 64-Bit Mode Valid Compat/ Leg Mode Valid Description Store IDTR to m. Description Stores the content the interrupt descriptor table register (IDTR) in the destination operand. The destination operand specifies a 6-byte memory location.
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INSTRUCTION SET REFERENCE, N-Z DEST[0:15] ← IDTR(Limit); DEST[16:79] ← IDTR(Base); (* Full 64-bit base address stored *) FI; FI; Flags Affected None. Protected Mode Exceptions #GP(0) If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector.
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INSTRUCTION SET REFERENCE, N-Z #UD If the destination operand is a register. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 4-312 Vol.
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INSTRUCTION SET REFERENCE, N-Z SLDT—Store Local Descriptor Table Register Opcode 0F 00 /0 Instruction SLDT r/m16 64-Bit Mode Valid Compat/ Leg Mode Valid REX.W + 0F 00 /0 SLDT r64/m16 Valid Valid Description Stores segment selector from LDTR in r/m16. Stores segment selector from LDTR in r64/m16. Description Stores the segment selector from the local descriptor table register (LDTR) in the destination operand. The destination operand can be a general-purpose register or a memory location.
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INSTRUCTION SET REFERENCE, N-Z If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
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INSTRUCTION SET REFERENCE, N-Z SMSW—Store Machine Status Word Opcode 0F 01 /4 0F 01 /4 Instruction SMSW r/m16 SMSW r32/m16 REX.W + 0F 01 /4 SMSW r64/m16 64-Bit Mode Valid Valid Compat/ Leg Mode Valid Valid Valid Valid Description Store machine status word to r/m16. Store machine status word in low-order 16 bits of r32/m16; high-order 16 bits of r32 are undefined. Store machine status word in low-order 16 bits of r64/m16; high-order 16 bits of r32 are undefined.
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INSTRUCTION SET REFERENCE, N-Z Operation DEST ← CR0[15:0]; (* Machine status word *) Flags Affected None. Protected Mode Exceptions #GP(0) If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, N-Z 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol.
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INSTRUCTION SET REFERENCE, N-Z SQRTPD—Compute Square Roots of Packed Double-Precision FloatingPoint Values Opcode 66 0F 51 /r Instruction SQRTPD xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Computes square roots of the packed double-precision floatingpoint values in xmm2/m128 and stores the results in xmm1.
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INSTRUCTION SET REFERENCE, N-Z #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0.CR4.OSXMMEXCPT(bit 10) is 1. If CPUID.01H:EDX.SSE2[bit 26] = 0. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH.
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INSTRUCTION SET REFERENCE, N-Z #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. 4-320 Vol.
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INSTRUCTION SET REFERENCE, N-Z SQRTPS—Compute Square Roots of Packed Single-Precision FloatingPoint Values Opcode 0F 51 /r Instruction SQRTPS xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Computes square roots of the packed single-precision floating-point values in xmm2/m128 and stores the results in xmm1.
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INSTRUCTION SET REFERENCE, N-Z #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH.
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INSTRUCTION SET REFERENCE, N-Z #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Vol.
PAGE 326
INSTRUCTION SET REFERENCE, N-Z SQRTSD—Compute Square Root of Scalar Double-Precision FloatingPoint Value Opcode F2 0F 51 /r Instruction SQRTSD xmm1, xmm2/m64 64-Bit Mode Valid Compat/ Leg Mode Valid Description Computes square root of the low double-precision floatingpoint value in xmm2/m64 and stores the results in xmm1.
PAGE 327
INSTRUCTION SET REFERENCE, N-Z #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1.
PAGE 328
INSTRUCTION SET REFERENCE, N-Z #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #AC(0) 4-326 Vol. 2B If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
PAGE 329
INSTRUCTION SET REFERENCE, N-Z SQRTSS—Compute Square Root of Scalar Single-Precision FloatingPoint Value Opcode F3 0F 51 /r Instruction SQRTSS xmm1, xmm2/m32 64-Bit Mode Valid Compat/ Leg Mode Valid Description Computes square root of the low single-precision floating-point value in xmm2/m32 and stores the results in xmm1.
PAGE 330
INSTRUCTION SET REFERENCE, N-Z #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1.
PAGE 331
INSTRUCTION SET REFERENCE, N-Z #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol.
PAGE 332
INSTRUCTION SET REFERENCE, N-Z STC—Set Carry Flag Opcode F9 Instruction STC 64-Bit Mode Valid Compat/ Leg Mode Valid Description Set CF flag. Description Sets the CF flag in the EFLAGS register. This instruction’s operation is the same in non-64-bit modes and 64-bit mode. Operation CF ← 1; Flags Affected The CF flag is set. The OF, ZF, SF, AF, and PF flags are unaffected. Exceptions (All Operating Modes) None. 4-330 Vol.
PAGE 333
INSTRUCTION SET REFERENCE, N-Z STD—Set Direction Flag Opcode FD Instruction STD 64-Bit Mode Valid Compat/ Leg Mode Valid Description Set DF flag. Description Sets the DF flag in the EFLAGS register. When the DF flag is set to 1, string operations decrement the index registers (ESI and/or EDI). This instruction’s operation is the same in non-64-bit modes and 64-bit mode. Operation DF ← 1; Flags Affected The DF flag is set. The CF, OF, ZF, SF, AF, and PF flags are unaffected.
PAGE 334
INSTRUCTION SET REFERENCE, N-Z STI—Set Interrupt Flag Opcode FB Instruction STI 64-Bit Mode Valid Compat/ Leg Mode Valid Description Set interrupt flag; external, maskable interrupts enabled at the end of the next instruction. Description If protected-mode virtual interrupts are not enabled, STI sets the interrupt flag (IF) in the EFLAGS register. After the IF flag is set, the processor begins responding to external, maskable interrupts after the next instruction is executed.
PAGE 335
INSTRUCTION SET REFERENCE, N-Z Table 4-4. Decision Table for STI Results PE VM IOPL CPL PVI VIP VME STI Result 0 X X X X X X IF = 1 1 0 ≥ CPL X X X X IF = 1 1 0 < CPL 3 1 0 X VIF = 1 1 0 < CPL <3 X X X GP Fault 1 0 < CPL X 0 X X GP Fault 1 0 < CPL X X 1 X GP Fault 1 1 3 X X X X IF = 1 1 1 <3 X X 0 1 VIF = 1 1 1 <3 X X 1 X GP Fault 1 1 <3 X X X 0 GP Fault NOTES: X = This setting has no impact.
PAGE 336
INSTRUCTION SET REFERENCE, N-Z ELSE IF ((IOPL < 3) and (VIP = 0) and (VME = 1)) THEN VIF ← 1; (* Set Virtual Interrupt Flag *) ELSE #GP(0); (* Trap to virtual-8086 monitor *) FI;) FI; FI; FI; Flags Affected The IF flag is set to 1; or the VIF flag is set to 1. Protected Mode Exceptions #GP(0) If the CPL is greater (has less privilege) than the IOPL of the current program or procedure. Real-Address Mode Exceptions None.
PAGE 337
INSTRUCTION SET REFERENCE, N-Z STMXCSR—Store MXCSR Register State Opcode 0F AE /3 Instruction STMXCSR m32 64Bit Mode Valid Compat/ Leg Mode Valid Description Store contents of MXCSR register to m32. Description Stores the contents of the MXCSR control and status register to the destination operand. The destination operand is a 32-bit memory location. The reserved bits in the MXCSR register are stored as 0s. This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
PAGE 338
INSTRUCTION SET REFERENCE, N-Z Real Address Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. #UD If CR0.EM[bit 2] = 1. #NM If CR0.TS[bit 3] = 1. #UD If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Virtual 8086 Mode Exceptions Same exceptions as in Real Address Mode. #PF(fault-code) For a page fault. #AC For unaligned memory reference. Compatibility Mode Exceptions Same exceptions as in Protected Mode.
PAGE 339
INSTRUCTION SET REFERENCE, N-Z STOS/STOSB/STOSW/STOSD/STOSQ—Store String Opcode AA Instruction STOS m8 64-Bit Mode Valid Compat/ Leg Mode Valid AB STOS m16 Valid Valid AB STOS m32 Valid Valid REX.W + AB AA STOS m64 STOSB Valid Valid N.E. Valid AB STOSW Valid Valid AB STOSD Valid Valid REX.W + AB STOSQ Valid N.E. Description For legacy mode, store AL at address ES:(E)DI; For 64-bit mode store AL at address RDI or EDI.
PAGE 340
INSTRUCTION SET REFERENCE, N-Z register. These must be loaded correctly before the store string instruction is executed. The no-operands form provides “short forms” of the byte, word, doubleword, and quadword versions of the STOS instructions. Here also ES:(E)DI is assumed to be the destination operand and AL, AX, or EAX is assumed to be the source operand.
PAGE 341
INSTRUCTION SET REFERENCE, N-Z FI; FI; ELSE IF (Doubleword store) THEN DEST ← EAX; THEN IF DF = 0 THEN (E)DI ← (E)DI + 4; ELSE (E)DI ← (E)DI – 4; FI; FI; FI; 64-bit Mode: IF (Byte store) THEN DEST ← AL; THEN IF DF = 0 THEN (R|E)DI ← (R|E)DI + 1; ELSE (R|E)DI ← (R|E)DI – 1; FI; ELSE IF (Word store) THEN DEST ← AX; THEN IF DF = 0 THEN (R|E)DI ← (R|E)DI + 2; ELSE (R|E)DI ← (R|E)DI – 2; FI; FI; ELSE IF (Doubleword store) THEN DEST ← EAX; THEN IF DF = 0 THEN (R|E)DI ← (R|E)DI + 4; ELSE (R|E)DI ← (R|E)DI – 4; FI
PAGE 342
INSTRUCTION SET REFERENCE, N-Z FI; FI; Flags Affected None. Protected Mode Exceptions #GP(0) If the destination is located in a non-writable segment. If a memory operand effective address is outside the limit of the ES segment. If the ES register contains a NULL segment selector. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
PAGE 343
INSTRUCTION SET REFERENCE, N-Z STR—Store Task Register Opcode 0F 00 /1 Instruction STR r/m16 64-Bit Mode Valid Compat/ Leg Mode Valid Description Stores segment selector from TR in r/m16. Description Stores the segment selector from the task register (TR) in the destination operand. The destination operand can be a general-purpose register or a memory location. The segment selector stored with this instruction points to the task state segment (TSS) for the currently running task.
PAGE 344
INSTRUCTION SET REFERENCE, N-Z Real-Address Mode Exceptions #UD The STR instruction is not recognized in real-address mode. Virtual-8086 Mode Exceptions #UD The STR instruction is not recognized in virtual-8086 mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #GP(0) If the memory address is in a non-canonical form. #SS(U) If the stack address is in a non-canonical form. #PF(fault-code) If a page fault occurs.
PAGE 345
INSTRUCTION SET REFERENCE, N-Z SUB—Subtract 64-Bit Mode Valid Valid Valid Valid Compat/ Leg Mode Valid Valid Valid N.E. SUB r/m8, imm8 SUB r/m8*, imm8 SUB r/m16, imm16 SUB r/m32, imm32 SUB r/m64, imm32 Valid Valid Valid Valid N.E. Valid Valid Valid Valid N.E. 83 /5 ib SUB r/m16, imm8 Valid Valid 83 /5 ib SUB r/m32, imm8 Valid Valid REX.W + 83 /5 ib SUB r/m64, imm8 Valid N.E. 28 /r REX + 28 /r 29 /r 29 /r REX.W + 29 /r 2A /r REX + 2A /r 2B /r 2B /r REX.
PAGE 346
INSTRUCTION SET REFERENCE, N-Z Description Subtracts the second operand (source operand) from the first operand (destination operand) and stores the result in the destination operand. The destination operand can be a register or a memory location; the source operand can be an immediate, register, or memory location. (However, two memory operands cannot be used in one instruction.) When an immediate value is used as an operand, it is sign-extended to the length of the destination operand format.
PAGE 347
INSTRUCTION SET REFERENCE, N-Z Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode.
PAGE 348
INSTRUCTION SET REFERENCE, N-Z SUBPD—Subtract Packed Double-Precision Floating-Point Values Opcode 66 0F 5C /r Instruction SUBPD xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Subtract packed double-precision floating-point values in xmm2/m128 from xmm1.
PAGE 349
INSTRUCTION SET REFERENCE, N-Z #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 1. If CPUID.01H:EDX.SSE2[bit 26] = 0. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
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INSTRUCTION SET REFERENCE, N-Z #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. 4-348 Vol.
PAGE 351
INSTRUCTION SET REFERENCE, N-Z SUBPS—Subtract Packed Single-Precision Floating-Point Values Opcode 0F 5C /r Instruction SUBPS xmm1 xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Subtract packed single-precision floating-point values in xmm2/mem from xmm1.
PAGE 352
INSTRUCTION SET REFERENCE, N-Z #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1.
PAGE 353
INSTRUCTION SET REFERENCE, N-Z #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Vol.
PAGE 354
INSTRUCTION SET REFERENCE, N-Z SUBSD—Subtract Scalar Double-Precision Floating-Point Values Opcode F2 0F 5C /r Instruction SUBSD xmm1, xmm2/m64 64-Bit Mode Valid Compat/ Leg Mode Valid Description Subtracts the low doubleprecision floating-point values in xmm2/mem64 from xmm1.
PAGE 355
INSTRUCTION SET REFERENCE, N-Z #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1.
PAGE 356
INSTRUCTION SET REFERENCE, N-Z #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #AC(0) 4-354 Vol. 2B If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
PAGE 357
INSTRUCTION SET REFERENCE, N-Z SUBSS—Subtract Scalar Single-Precision Floating-Point Values Opcode F3 0F 5C /r Instruction SUBSS xmm1, xmm2/m32 64-Bit Mode Valid Compat/ Leg Mode Valid Description Subtract the lower single-precision floating-point values in xmm2/m32 from xmm1.
PAGE 358
INSTRUCTION SET REFERENCE, N-Z #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1.
PAGE 359
INSTRUCTION SET REFERENCE, N-Z #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol.
PAGE 360
INSTRUCTION SET REFERENCE, N-Z SWAPGS—Swap GS Base Register Opcode 0F 01 /7 Instruction SWAPGS 64-Bit Mode Valid Compat/ Leg Mode Invalid Description Exchanges the current GS base register value with the value contained in MSR address C0000102H. Description SWAPGS exchanges the current GS base register value with the value contained in MSR address C0000102H (MSR_KERNELGSbase). KernelGSbase is guaranteed to be canonical; so SWAPGS does not perform a canonical check.
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INSTRUCTION SET REFERENCE, N-Z Operation IF CS.L ≠ 1 (* Not in 64-Bit Mode *) THEN #UD; FI; IF CPL ≠ 0 THEN #GP(0); FI; tmp ← GS(BASE); GS(BASE) ← KERNELGSbase; KERNELGSbase ← tmp; Flags Affected None Protected Mode Exceptions #UD If Mode ≠ 64-Bit Real-Address Mode Exceptions #UD Instruction not recognized. Virtual-8086 Mode Exceptions #UD Instruction not recognized. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #GP(0) If CPL ≠ 0. Vol.
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INSTRUCTION SET REFERENCE, N-Z SYSCALL—Fast System Call Opcode 0F 05 Instruction SYSCALL 64-Bit Mode Valid Compat/ Leg Mode Invalid Description Fast call to privilege level 0 system procedures. Description SYSCALL saves the RIP of the instruction following SYSCALL to RCX and loads a new RIP from the IA32_LSTAR (64-bit mode). Upon return, SYSRET copies the value saved in RCX to the RIP. SYSCALL saves RFLAGS (lower 32 bit only) in R11.
PAGE 363
INSTRUCTION SET REFERENCE, N-Z SS(BASE) ← 0; SS(LIMIT) ← 0xFFFFF; SS(GRANULAR) ← 1; Flags Affected All. Protected Mode Exceptions #UD If Mode ≠ 64-bit. Real-Address Mode Exceptions #UD Instruction is not recognized in this mode. Virtual-8086 Mode Exceptions #UD Instruction is not recognized in this mode. Compatibility Mode Exceptions #UD Instruction is not recognized in this mode. 64-Bit Mode Exceptions #UD If IA32_EFER.SCE = 0. Vol.
PAGE 364
INSTRUCTION SET REFERENCE, N-Z SYSENTER—Fast System Call Opcode 0F 34 Instruction SYSENTER 64-Bit Mode Valid Compat/ Leg Mode Valid Description Fast call to privilege level 0 system procedures. Description Executes a fast call to a level 0 system procedure or routine. SYSENTER is a companion instruction to SYSEXIT.
PAGE 365
INSTRUCTION SET REFERENCE, N-Z 6. Clears the VM flag in the EFLAGS register, if the flag is set. 7. Begins executing the selected system procedure. The processor does not save a return IP or other state information for the calling procedure. The SYSENTER instruction always transfers program control to a protected-mode code segment with a DPL of 0.
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INSTRUCTION SET REFERENCE, N-Z SYSENTER/SYSEXIT_Supported; FI; FI; When the CPUID instruction is executed on the Pentium Pro processor (model 1), the processor returns a the SEP flag as set, but does not support the SYSENTER/SYSEXIT instructions. Operation IF CR0.PE = 0 THEN #GP(0); FI; IF SYSENTER_CS_MSR[15:2] = 0 THEN #GP(0); FI; EFLAGS.VM ← 0; (* Insures protected mode execution *) EFLAGS.IF ← 0; (* Mask interrupts *) EFLAGS.RF ← 0; CS.SEL ← SYSENTER_CS_MSR (* Set rest of CS to a fixed value *) CS.
PAGE 367
INSTRUCTION SET REFERENCE, N-Z IA-32e Mode Operation In IA-32e mode, SYSENTER executes a fast system calls from user code running at privilege level 3 (in compatibility mode or 64-bit mode) to 64-bit executive procedures running at privilege level 0. This instruction is a companion instruction to the SYSEXIT instruction. In IA-32e mode, the IA32_SYSENTER_EIP and IA32_SYSENTER_ESP MSRs hold 64-bit addresses and must be in canonical form; IA32_SYSENTER_CS must not contain a NULL selector.
PAGE 368
INSTRUCTION SET REFERENCE, N-Z SYSEXIT—Fast Return from Fast System Call Opcode 0F 35 REX.W + 0F 35 Instruction SYSEXIT SYSEXIT 64-Bit Mode Valid Valid Compat/ Leg Mode Valid Valid Description Fast return to privilege level 3 user code. Fast return to 64-bit mode privilege level 3 user code. Description Executes a fast return to privilege level 3 user code. SYSEXIT is a companion instruction to the SYSENTER instruction.
PAGE 369
INSTRUCTION SET REFERENCE, N-Z The SYSEXIT instruction always transfers program control to a protected-mode code segment with a DPL of 3. The instruction requires that the following conditions are met by the operating system: • The segment descriptor for the selected user code segment selects a flat, 32-bit code segment of up to 4 GBytes, with execute, read, accessed, and nonconforming permissions.
PAGE 370
INSTRUCTION SET REFERENCE, N-Z CS.SEL.RPL ← 3; CS.ARbyte.P ← 1; CPL ← 3; SS.SEL ← (SYSENTER_CS_MSR + 24); (* Set rest of SS to a fixed value *); SS.BASE ← 0; SS.LIMIT ← FFFFFH; SS.ARbyte.G ←1; SS.ARbyte.S ← ; SS.ARbyte.TYPE ← 0011B; SS.ARbyte.D ← 1; SS.ARbyte.DPL ← 3; SS.SEL.RPL ← 3; SS.ARbyte.
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INSTRUCTION SET REFERENCE, N-Z • • Stack segment — Computed by adding 24 to the value in IA32_SYSENTER_CS. Stack pointer — Update ESP from 32-bit address in ECX. Flags Affected None. Protected Mode Exceptions #GP(0) If IA32_SYSENTER_CS[15:2] = 0. If CPL ≠ 0. Real-Address Mode Exceptions #GP(0) If protected mode is not enabled. Virtual-8086 Mode Exceptions #GP(0) Always Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #GP(0) If IA32_SYSENTER_CS = 0.
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INSTRUCTION SET REFERENCE, N-Z SYSRET—Return From Fast System Call Opcode 0F 07 Instruction SYSRET 64-Bit Mode Valid Compat/ Leg Mode Invalid Description Return from fast system call Description SYSCALL saves the RIP of the instruction following the SYSCALL into RCX and loads the new RIP from the LSTAR (64-bit mode only). Upon return, SYSRET copies the value saved in RCX to the RIP. In a return to 64-bit mode using Osize 64, SYSRET sets the CS selector value to MSR IA32_STAR[63:48] +16.
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INSTRUCTION SET REFERENCE, N-Z SS(PL) ← 0x3; RIP ← RCX; ELSE (* Return to Compatibility Mode *) EFLAGS ← R11; CPL ← 0x3; CS(SEL) ← IA32_STAR[63:48] ; CS(PL) ← 0x3; SS(SEL) ← IA32_STAR[63:48] + 8; SS(PL) ← 0x3; EIP ← ECX; FI; Flags Affected VM, IF, RF. Protected Mode Exceptions #UD If Mode ≠ 64-Bit. Real-Address Mode Exceptions #UD Instruction not recognized in this mode. Virtual-8086 Mode Exceptions #UD Instruction not recognized in this mode.
PAGE 374
INSTRUCTION SET REFERENCE, N-Z TEST—Logical Compare Compat/ Leg Mode Valid Opcode A8 ib Instruction TEST AL, imm8 64-Bit Mode Valid A9 iw TEST AX, imm16 Valid Valid A9 id TEST EAX, imm32 Valid Valid REX.W + A9 id TEST RAX, imm32 Valid N.E. F6 /0 ib TEST r/m8, imm8 Valid Valid REX + F6 /0 ib TEST r/m8*, imm8 Valid N.E. F7 /0 iw TEST r/m16, imm16 Valid Valid F7 /0 id TEST r/m32, imm32 Valid Valid REX.W + F7 /0 id TEST r/m64, imm32 Valid N.E.
PAGE 375
INSTRUCTION SET REFERENCE, N-Z Description Computes the bit-wise logical AND of first operand (source 1 operand) and the second operand (source 2 operand) and sets the SF, ZF, and PF status flags according to the result. The result is then discarded. In 64-bit mode, using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.
PAGE 376
INSTRUCTION SET REFERENCE, N-Z Real-Address Mode Exceptions #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs.
PAGE 377
INSTRUCTION SET REFERENCE, N-Z UCOMISD—Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS Opcode 66 0F 2E /r Instruction UCOMISD xmm1, xmm2/m64 64-Bit Mode Valid Compat/ Leg Mode Valid Description Compares (unordered) the low double-precision floating-point values in xmm1 and xmm2/m64 and set the EFLAGS accordingly.
PAGE 378
INSTRUCTION SET REFERENCE, N-Z Intel C/C++ Compiler Intrinsic Equivalent int_mm_ucomieq_sd(__m128d a, __m128d b) int_mm_ucomilt_sd(__m128d a, __m128d b) int_mm_ucomile_sd(__m128d a, __m128d b) int_mm_ucomigt_sd(__m128d a, __m128d b) int_mm_ucomige_sd(__m128d a, __m128d b) int_mm_ucomineq_sd(__m128d a, __m128d b) SIMD Floating-Point Exceptions Invalid (if SNaN operands), Denormal. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
PAGE 379
INSTRUCTION SET REFERENCE, N-Z Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.
PAGE 380
INSTRUCTION SET REFERENCE, N-Z UCOMISS—Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS Opcode 0F 2E /r Instruction UCOMISS xmm1, xmm2/m32 64-Bit Mode Valid Compat/ Leg Mode Valid Description Compare lower single-precision floating-point value in xmm1 register with lower single-precision floatingpoint value in xmm2/mem and set the status flags accordingly.
PAGE 381
INSTRUCTION SET REFERENCE, N-Z Intel C/C++ Compiler Intrinsic Equivalent int_mm_ucomieq_ss(__m128 a, __m128 b) int_mm_ucomilt_ss(__m128 a, __m128 b) int_mm_ucomile_ss(__m128 a, __m128 b) int_mm_ucomigt_ss(__m128 a, __m128 b) int_mm_ucomige_ss(__m128 a, __m128 b) int_mm_ucomineq_ss(__m128 a, __m128 b) SIMD Floating-Point Exceptions Invalid (if SNaN operands), Denormal. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
PAGE 382
INSTRUCTION SET REFERENCE, N-Z Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.
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INSTRUCTION SET REFERENCE, N-Z UD2—Undefined Instruction Opcode 0F 0B Instruction UD2 64-Bit Mode Valid Compat/ Leg Mode Valid Description Raise invalid opcode exception. Description Generates an invalid opcode. This instruction is provided for software testing to explicitly generate an invalid opcode. The opcode for this instruction is reserved for this purpose. Other than raising the invalid opcode exception, this instruction is the same as the NOP instruction.
PAGE 384
INSTRUCTION SET REFERENCE, N-Z UNPCKHPD—Unpack and Interleave High Packed Double-Precision Floating-Point Values Opcode 66 0F 15 /r Instruction UNPCKHPD xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Unpacks and Interleaves doubleprecision floating-point values from high quadwords of xmm1 and xmm2/m128. Description Performs an interleaved unpack of the high double-precision floating-point values from the source operand (second operand) and the destination operand (first operand).
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INSTRUCTION SET REFERENCE, N-Z Intel C/C++ Compiler Intrinsic Equivalent UNPCKHPD__m128d _mm_unpackhi_pd(__m128d a, __m128d b) SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1.
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INSTRUCTION SET REFERENCE, N-Z #GP(0) If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. 4-384 Vol.
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INSTRUCTION SET REFERENCE, N-Z UNPCKHPS—Unpack and Interleave High Packed Single-Precision Floating-Point Values Opcode 0F 15 /r Instruction UNPCKHPS xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Unpacks and Interleaves singleprecision floating-point values from high quadwords of xmm1 and xmm2/mem into xmm1.
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INSTRUCTION SET REFERENCE, N-Z Intel C/C++ Compiler Intrinsic Equivalent UNPCKHPS __m128 _mm_unpackhi_ps(__m128 a, __m128 b) SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1.
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INSTRUCTION SET REFERENCE, N-Z #GP(0) If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Vol.
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INSTRUCTION SET REFERENCE, N-Z UNPCKLPD—Unpack and Interleave Low Packed Double-Precision Floating-Point Values Opcode 66 0F 14 /r Instruction UNPCKLPD xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Unpacks and Interleaves doubleprecision floating-point values from low quadwords of xmm1 and xmm2/m128. Description Performs an interleaved unpack of the low double-precision floating-point values from the source operand (second operand) and the destination operand (first operand).
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INSTRUCTION SET REFERENCE, N-Z Intel C/C++ Compiler Intrinsic Equivalent UNPCKHPD__m128d _mm_unpacklo_pd(__m128d a, __m128d b) SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1.
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INSTRUCTION SET REFERENCE, N-Z #GP(0) If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. 4-390 Vol.
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INSTRUCTION SET REFERENCE, N-Z UNPCKLPS—Unpack and Interleave Low Packed Single-Precision Floating-Point Values Opcode 0F 14 /r Instruction UNPCKLPS xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Unpacks and Interleaves singleprecision floating-point values from low quadwords of xmm1 and xmm2/mem into xmm1.
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INSTRUCTION SET REFERENCE, N-Z DEST[127:96] ← SRC[63:32]; Intel C/C++ Compiler Intrinsic Equivalent UNPCKLPS __m128 _mm_unpacklo_ps(__m128 a, __m128 b) SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1.
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INSTRUCTION SET REFERENCE, N-Z 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Vol.
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INSTRUCTION SET REFERENCE, N-Z VERR/VERW—Verify a Segment for Reading or Writing Opcode 0F 00 /4 Instruction VERR r/m16 64-Bit Mode Valid Compat/ Leg Mode Valid 0F 00 /5 VERW r/m16 Valid Valid Description Set ZF=1 if segment specified with r/m16 can be read. Set ZF=1 if segment specified with r/m16 can be written. Description Verifies whether the code or data segment specified with the source operand is readable (VERR) or writable (VERW) from the current privilege level (CPL).
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INSTRUCTION SET REFERENCE, N-Z or (SegmentDescriptor(Type) ≠ conforming code segment) and (CPL > DPL) or (RPL > DPL) THEN ZF ← 0; ELSE IF ((Instruction = VERR) and (Segment readable)) or ((Instruction = VERW) and (Segment writable)) THEN ZF ← 1; FI; FI; Flags Affected The ZF flag is set to 1 if the segment is accessible and readable (VERR) or writable (VERW); otherwise, it is set to 0.
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INSTRUCTION SET REFERENCE, N-Z 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 4-396 Vol.
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INSTRUCTION SET REFERENCE, N-Z WAIT/FWAIT—Wait Opcode 9B Instruction WAIT 64-Bit Mode Valid Compat/ Leg Mode Valid 9B FWAIT Valid Valid Description Check pending unmasked floatingpoint exceptions. Check pending unmasked floatingpoint exceptions. Description Causes the processor to check for and handle pending, unmasked, floating-point exceptions before proceeding. (FWAIT is an alternate mnemonic for WAIT.) This instruction is useful for synchronizing exceptions in critical sections of code.
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INSTRUCTION SET REFERENCE, N-Z Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. 4-398 Vol.
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INSTRUCTION SET REFERENCE, N-Z WBINVD—Write Back and Invalidate Cache Opcode 0F 09 Instruction WBINVD 64-Bit Mode Valid Compat/ Leg Mode Valid Description Write back and flush Internal caches; initiate writing-back and flushing of external caches. Description Writes back all modified cache lines in the processor’s internal cache to main memory and invalidates (flushes) the internal caches.
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INSTRUCTION SET REFERENCE, N-Z Protected Mode Exceptions #GP(0) If the current privilege level is not 0. Real-Address Mode Exceptions None. Virtual-8086 Mode Exceptions #GP(0) The WBINVD instruction cannot be executed at the virtual-8086 mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. 4-400 Vol.
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INSTRUCTION SET REFERENCE, N-Z WRMSR—Write to Model Specific Register Opcode 0F 30 Instruction WRMSR 64-Bit Mode Valid Compat/ Leg Mode Valid REX.W + 0F 30 WRMSR Valid N.E. Description Write the value in EDX:EAX to MSR specified by ECX. Write the value in RDX[31:0]: RAX[31:0] to MSR specified by RCX. Description In legacy and compatibility mode, writes the contents of registers EDX:EAX into the 64-bit model specific register (MSR) specified by the ECX register.
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INSTRUCTION SET REFERENCE, N-Z Operation IF 64-BIt Mode and REX.W used THEN MSR[RCX] ← RDX:RAX; ELSE IF (Non-64-Bit Modes or Default 64-Bit Mode) MSR[ECX] ← EDX:EAX; FI; FI; Flags Affected None. Protected Mode Exceptions #GP(0) If the current privilege level is not 0. If the value in ECX specifies a reserved or unimplemented MSR address. If the value in EDX:EAX sets bits that are reserved in the MSR specified by ECX.
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INSTRUCTION SET REFERENCE, N-Z XADD—Exchange and Add Opcode 0F C0 /r Instruction XADD r/m8, r8 64-Bit Mode Valid Compat/ Leg Mode Valid REX + 0F C0 /r XADD r/m8*, r8* Valid N.E. 0F C1 /r XADD r/m16, r16 XADD r/m32, r32 XADD r/m64, r64 Valid Valid Valid Valid Valid N.E. 0F C1 /r REX.W + 0F C1 /r Description Exchange r8 and r/m8; load sum into r/m8. Exchange r8 and r/m8; load sum into r/m8. Exchange r16 and r/m16; load sum into r/m16. Exchange r32 and r/m32; load sum into r/m32.
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INSTRUCTION SET REFERENCE, N-Z Flags Affected The CF, PF, AF, SF, ZF, and OF flags are set according to the result of the addition, which is stored in the destination operand. Protected Mode Exceptions #GP(0) If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit.
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INSTRUCTION SET REFERENCE, N-Z #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol.
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INSTRUCTION SET REFERENCE, N-Z XCHG—Exchange Register/Memory with Register Compat/ Leg Mode Valid Valid Valid N.E. Description Exchange r16 with AX. Exchange AX with r16. Exchange r32 with EAX. Exchange r64 with RAX. Opcode 90+rw 90+rw 90+rd REX.W + 90+rd 90+rd REX.W + 90+rd 86 /r Instruction XCHG AX, r16 XCHG r16, AX XCHG EAX, r32 XCHG RAX, r64 64-Bit Mode Valid Valid Valid Valid XCHG r32, EAX XCHG r64, RAX Valid Valid Valid N.E. Exchange EAX with r32. Exchange RAX with r64.
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INSTRUCTION SET REFERENCE, N-Z or absence of the LOCK prefix or of the value of the IOPL. (See the LOCK prefix description in this chapter for more information on the locking protocol.) This instruction is useful for implementing semaphores or similar data structures for process synchronization. (See “Bus Locking” in Chapter 7 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for more information on bus locking.
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INSTRUCTION SET REFERENCE, N-Z Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode.
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INSTRUCTION SET REFERENCE, N-Z XLAT/XLATB—Table Look-up Translation Opcode D7 Instruction XLAT m8 64-Bit Mode Valid Compat/ Leg Mode Valid D7 XLATB Valid Valid REX.W + D7 XLATB Valid N.E. Description Set AL to memory byte DS:[(E)BX + unsigned AL]. Set AL to memory byte DS:[(E)BX + unsigned AL]. Set AL to memory byte [RBX + unsigned AL].
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INSTRUCTION SET REFERENCE, N-Z AL ← (RBX + ZeroExtend(AL)); FI; Flags Affected None. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, N-Z XOR—Logical Exclusive OR Opcode 34 ib 35 iw 35 id REX.W + 35 id Instruction XOR AL, imm8 XOR AX, imm16 XOR EAX, imm32 XOR RAX, imm32 64-Bit Mode Valid Valid Valid Valid Compat/ Leg Mode Valid Valid Valid N.E. 80 /6 ib REX + 80 /6 ib 81 /6 iw 81 /6 id REX.W + 81 /6 id XOR r/m8, imm8 XOR r/m8*, imm8 XOR r/m16, imm16 XOR r/m32, imm32 XOR r/m64, imm32 Valid Valid Valid Valid Valid Valid N.E. Valid Valid N.E.
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INSTRUCTION SET REFERENCE, N-Z corresponding bits of the operands are different; each bit is 0 if the corresponding bits are the same. This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically. In 64-bit mode, using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits.
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INSTRUCTION SET REFERENCE, N-Z #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs.
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INSTRUCTION SET REFERENCE, N-Z XORPD—Bitwise Logical XOR for Double-Precision Floating-Point Values Opcode 66 0F 57 /r Instruction XORPD xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Bitwise exclusive-OR of xmm2/m128 and xmm1. Description Performs a bitwise logical exclusive-OR of the two packed double-precision floatingpoint values from the source operand (second operand) and the destination operand (first operand), and stores the result in the destination operand.
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INSTRUCTION SET REFERENCE, N-Z Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault.
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INSTRUCTION SET REFERENCE, N-Z XORPS—Bitwise Logical XOR for Single-Precision Floating-Point Values Opcode 0F 57 /r Instruction XORPS xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Bitwise exclusive-OR of xmm2/m128 and xmm1. Description Performs a bitwise logical exclusive-OR of the four packed single-precision floatingpoint values from the source operand (second operand) and the destination operand (first operand), and stores the result in the destination operand.
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INSTRUCTION SET REFERENCE, N-Z Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault.
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INSTRUCTION SET REFERENCE, N-Z 4-418 Vol.
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CHAPTER 5 VMX INSTRUCTION REFERENCE 5.1 OVERVIEW This chapter describes the virtual-machine extensions (VMX) for the Intel 64 and IA-32 architectures. VMX is intended to support virtualization of processor hardware and a system software layer acting as a host to multiple guest software environments. The virtual-machine extensions (VMX) includes five instructions that manage the virtual-machine control structure (VMCS) and five instruction that manage VMX operation.
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VMX INSTRUCTION REFERENCE • VMXON — This instruction takes a single 64-bit source operand that is in memory. It causes a logical processor to enter VMX root operation and to use the memory referenced by the operand to support VMX operation. Only VMCALL can be executed in compatibility mode (causing a VM exit). The other VMX instructions generate invalid-opcode exceptions if executed in compatibility mode. 5.2 CONVENTIONS The operation sections for the VMX instructions in Section 5.
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VMX INSTRUCTION REFERENCE VMfailValid(ErrorNumber):// executed only if there is a current VMCS CF ← 0; PF ← 0; AF ← 0; ZF ← 1; SF ← 0; OF ← 0; Set the VM-instruction error field to ErrorNumber; The different VM-instruction error numbers are enumerated in Appendix J, “VM Instruction Error Numbers,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B. 5.3 VMX INSTRUCTIONS This section provides detailed descriptions of the VMX instructions. Vol.
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VMX INSTRUCTION REFERENCE VMCALL—Call to VM Monitor Opcode 0F 01 C1 Instruction VMCALL Description Call to VM monitor by causing VM exit. Description This instruction allows guest software can make a call for service into an underlying VM monitor. The details of the programming interface for such calls are VMM-specific; this instruction does nothing more than cause a VM exit, registering the appropriate exit reason. Use of this instruction in VMX root operation invokes an SMM monitor (see Section 24.16.
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VMX INSTRUCTION REFERENCE 3B); leave SMM; VMfailValid(VMCALL with incorrect MSEG revision identifier); ELSE read SMM-monitor features field in MSEG (see Section 24.16.6.2, in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B); IF features field is invalid THEN leave SMM; VMfailValid(VMCALL with invalid SMM-monitor features); ELSE activate dual-monitor treatment of SMIs and SMM (see Section 24.16.
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VMX INSTRUCTION REFERENCE Compatibility Mode Exceptions #UD If executed outside VMX non-root operation. 64-Bit Mode Exceptions #UD 5-6 Vol. 2B If executed outside VMX operation.
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VMX INSTRUCTION REFERENCE VMCLEAR—Clear Virtual-Machine Control Structure Opcode 66 0F C7 /6 Instruction VMCLEAR m64 Description Copy VMCS data to VMCS region in memory. Description This instruction applies to the VMCS whose VMCS region resides at the physical address contained in the instruction operand. The instruction ensures that VMCS data for that VMCS (some of these data may be currently maintained on the processor) are copied to the VMCS region in memory.
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VMX INSTRUCTION REFERENCE IF operand addr = current-VMCS pointer THEN current-VMCS pointer ← FFFFFFFF_FFFFFFFFH; FI; VMsucceed; FI; FI; Flags Affected See the operation section and Section 5.2. Use of Prefixes LOCK Causes #UD. REP* Reserved and may cause unpredictable behavior (applies to both REPNE/REPNZ and REP/REPE/REPZ).
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VMX INSTRUCTION REFERENCE Virtual-8086 Mode Exceptions #UD The VMCLEAR instruction is not recognized in virtual-8086 mode. Compatibility Mode Exceptions #UD The VMCLEAR instruction is not recognized in compatibility mode. 64-Bit Mode Exceptions #GP(0) If the current privilege level is not 0. If the source operand is in the CS, DS, ES, FS, or GS segments and the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs in accessing the memory operand.
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VMX INSTRUCTION REFERENCE VMLAUNCH/VMRESUME—Launch/Resume Virtual Machine Opcode 0F 01 C2 0F 01 C3 Instruction VMLAUNCH VMRESUME Description Launch virtual machine managed by current VMCS. Resume virtual machine managed by current VMCS. Description Effects a VM entry managed by the current VMCS. • VMLAUNCH fails if the launch state of current VMCS is not “clear”. If the instruction is successful, it sets the launch state to “launched.
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VMX INSTRUCTION REFERENCE THEN VMfailValid(VM entry with invalid VMX-control field(s)) or VMfailValid(VM entry with invalid host-state field(s)) or VMfailValid(VM entry with invalid executive-VMCS pointer)) or VMfailValid(VM entry with non-launched executive VMCS) or VMfailValid(VM entry with executive-VMCS pointer not VMXON pointer) or VMfailValid(VM entry with invalid VM-execution control fields in executive VMCS) as appropriate; ELSE Attempt to load guest state and PDPTRs as appropriate; clear address-r
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VMX INSTRUCTION REFERENCE Further details of the operation of the VM-entry appear in Chapter 22 of IA-32 Intel Architecture Software Developer’s Manual, Volume 3B. Flags Affected See the operation section and Section 5.2. Use of Prefixes LOCK Causes #UD REP* Cause #UD (includes REPNE/REPNZ and REP/REPE/REPZ) Segment overrides Ignored Operand size Causes #UD Address size Ignored REX Ignored Protected Mode Exceptions #GP(0) If the current privilege level is not 0.
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VMX INSTRUCTION REFERENCE VMPTRLD—Load Pointer to Virtual-Machine Control Structure Opcode 0F C7 /6 Instruction VMPTRLD m64 Description Loads the current VMCS pointer from memory. Description Marks the current-VMCS pointer valid and loads it with the physical address in the instruction operand. The instruction fails if its operand is not properly aligned, sets unsupported physical-address bits, or is equal to the VMXON pointer.
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VMX INSTRUCTION REFERENCE FI; FI; Flags Affected See the operation section and Section 5.2. Use of Prefixes LOCK Causes #UD REPNE/REPNZ Causes #UD REP/REPE/REPZ Changes encoding to that of VMXON; see “VMXON—Enter VMX Operation” for operation and interactions with other prefixes. Segment overrides Treated normally Operand size Changes encoding to that of VMCLEAR; see “VMCLEAR—Clear Virtual-Machine Control Structure” for operation and interactions with other prefixes.
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VMX INSTRUCTION REFERENCE Virtual-8086 Mode Exceptions #UD The VMPTRLD instruction is not recognized in virtual-8086 mode. Compatibility Mode Exceptions #UD The VMPTRLD instruction is not recognized in compatibility mode. 64-Bit Mode Exceptions #GP(0) If the current privilege level is not 0. If the source operand is in the CS, DS, ES, FS, or GS segments and the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs in accessing the memory source operand.
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VMX INSTRUCTION REFERENCE VMPTRST—Store Pointer to Virtual-Machine Control Structure Opcode 0F C7 /7 Instruction VMPTRST Description Stores the current VMCS pointer into memory. Description Stores the current-VMCS pointer into a specified memory address. The operand of this instruction is always 64 bits and is always in memory. Operation IF (register operand) or (not in VMX operation) or (RFLAGS.VM = 1) or (IA32_EFER.LMA = 1 and CS.
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VMX INSTRUCTION REFERENCE If the DS, ES, FS, or GS register contains an unusable segment. If the destination operand is located in a read-only data segment or any code segment. #PF(fault-code) If a page fault occurs in accessing the memory destination operand. #SS(0) If the memory destination operand effective address is outside the SS segment limit. If the SS register contains an unusable segment. #UD If operand is a register. If not in VMX operation.
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VMX INSTRUCTION REFERENCE VMREAD—Read Field from Virtual-Machine Control Structure Opcode 0F 78 0F 78 Instruction VMREAD r/m64, r64 VMREAD r/m32, r32 Description Reads a specified VMCS field (in 64-bit mode). Reads a specified VMCS field (outside 64-bit mode). Description Reads a specified field from the VMCS and stores it into a specified destination operand (register or memory). The specific VMCS field is identified by the VMCS-field encoding contained in the register source operand.
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VMX INSTRUCTION REFERENCE Flags Affected See the operation section and Section 5.2. Use of Prefixes LOCK Causes #UD REP* Cause #UD (includes REPNE/REPNZ and REP/REPE/REPZ) Segment overrides Treated normally Operand size Causes #UD Address size Treated normally REX Register extensions treated normally; operand-size overrides ignored Protected Mode Exceptions #GP(0) If the current privilege level is not 0.
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VMX INSTRUCTION REFERENCE 64-Bit Mode Exceptions #GP(0) If the current privilege level is not 0. If the memory destination operand is in the CS, DS, ES, FS, or GS segments and the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs in accessing a memory destination operand. #SS(0) If the memory destination operand is in the SS segment and the memory address is in a non-canonical form. #UD If not in VMX operation. 5-20 Vol.
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VMX INSTRUCTION REFERENCE VMRESUME—Resume Virtual Machine See VMLAUNCH/VMRESUME—Launch/Resume Virtual Machine. Vol.
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VMX INSTRUCTION REFERENCE VMWRITE—Write Field to Virtual-Machine Control Structure Opcode 0F 79 0F 79 Instruction VMWRITE r64, r/m64 VMWRITE r32, r/m32 Description Writes.a specified VMCS field (in 64-bit mode) Writes.a specified VMCS field (outside 64-bit mode) Description Writes to a specified field in the VMCS specified by a secondary source operand (register only) using the contents of a primary source operand (register or memory).
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VMX INSTRUCTION REFERENCE VMsucceed; FI; Flags Affected See the operation section and Section 5.2. Use of Prefixes LOCK Causes #UD REP* Cause #UD (includes REPNE/REPNZ and REP/REPE/REPZ) Segment overrides Treated normally Operand size Causes #UD Address size Treated normally REX Register extensions treated normally; operand-size overrides ignored Protected Mode Exceptions #GP(0) If the current privilege level is not 0.
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VMX INSTRUCTION REFERENCE 64-Bit Mode Exceptions #GP(0) If the current privilege level is not 0. If the memory source operand is in the CS, DS, ES, FS, or GS segments and the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs in accessing a memory source operand. #SS(0) If the memory source operand is in the SS segment and the memory address is in a non-canonical form. #UD If not in VMX operation. 5-24 Vol.
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VMX INSTRUCTION REFERENCE VMXOFF—Leave VMX Operation Opcode 0F 01 C4 Instruction VMXOFF Description Leaves VMX operation. Description Takes the logical processor out of VMX operation, unblocks INIT signals, re-enables A20M, and clears any address-range monitoring.1 Operation IF (not in VMX operation) or (RFLAGS.VM = 1) or (IA32_EFER.LMA = 1 and CS.
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VMX INSTRUCTION REFERENCE Address size Ignored REX Ignored Protected Mode Exceptions #GP(0) If executed in VMX root operation with CPL > 0. #UD If executed outside VMX operation. Real-Address Mode Exceptions #UD A logical processor cannot be in real-address mode while in VMX operation and the VMXOFF instruction is not recognized outside VMX operation. Virtual-8086 Mode Exceptions #UD The VMXOFF instruction is not recognized in virtual-8086 mode.
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VMX INSTRUCTION REFERENCE VMXON—Enter VMX Operation Opcode F3 0F C7 /6 Instruction VMXON m64 Description Enter VMX root operation. Description Puts the logical processor in VMX operation with no current VMCS, blocks INIT signals, disables A20M, and clears any address-range monitoring established by the MONITOR instruction.1 The operand of this instruction is a 4KB-aligned physical address (the VMXON pointer) that references the VMXON region, which the logical processor may use to support VMX operation.
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VMX INSTRUCTION REFERENCE ELSE current-VMCS pointer ← FFFFFFFF_FFFFFFFFH; enter VMX operation; block INIT signals; block and disable A20M; clear address-range monitoring; VMsucceed; FI; FI; FI; ELSIF in VMX non-root operation THEN VMexit; ELSIF CPL > 0 THEN #GP(0); ELSE VMfail(“VMXON executed in VMX root operation”); FI; Flags Affected See the operation section and Section 5.2.
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VMX INSTRUCTION REFERENCE #SS(0) If the memory source operand effective address is outside the SS segment limit. If the SS register contains an unusable segment. #UD If operand is a register. If executed with CR4.VMXE = 0. Real-Address Mode Exceptions #UD The VMXON instruction is not recognized in real-address mode. Virtual-8086 Mode Exceptions #UD The VMXON instruction is not recognized in virtual-8086 mode.
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VMX INSTRUCTION REFERENCE 5-30 Vol.
PAGE 451
APPENDIX A OPCODE MAP Use the opcode tables in this chapter to interpret Intel 64 and IA-32 architecture object code. Instructions are divided into encoding groups: • 1-byte, 2-byte and 3-byte opcode encodings are used to encode integer, system, MMX technology, SSE/SSE2/SSE3/SSSE3, and VMX instructions. Maps for these instructions are given in Table A-2 through Table A-6. • Escape opcodes (in the format: ESC character, opcode, ModR/M byte) are used for floating-point instructions.
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OPCODE MAP A.2 KEY TO ABBREVIATIONS Operands are identified by a two-character code of the form Zz. The first character, an uppercase letter, specifies the addressing method; the second character, a lowercase letter, specifies the type of operand. A.2.1 Codes for Addressing Method The following abbreviations are used to document addressing methods: A Direct address: the instruction has no ModR/M byte; the address of the operand is encoded in the instruction.
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OPCODE MAP following values: a base register, an index register, a scaling factor, and a displacement. R The R/M field of the ModR/M byte may refer only to a general register (for example, MOV (0F20-0F23)). S The reg field of the ModR/M byte selects a segment register (for example, MOV (8C,8E)). U The R/M field of the ModR/M byte selects a 128-bit XMM register. V The reg field of the ModR/M byte selects a 128-bit XMM register. W A ModR/M byte follows the opcode and specifies the operand.
PAGE 454
OPCODE MAP A.2.3 Register Codes When an opcode requires a specific register as an operand, the register is identified by name (for example, AX, CL, or ESI). The name indicates whether the register is 64, 32, 16, or 8 bits wide. A register identifier of the form eXX or rXX is used when register width depends on the operand-size attribute. eXX is used when 16 or 32-bit sizes are possible; rXX is used when 16, 32, or 64-bit sizes are possible.
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OPCODE MAP Example A-1. Look-up Example for 1-Byte Opcodes Opcode 030500000000H for an ADD instruction is interpreted using the 1-byte opcode map (Table A-2) as follows: • The first digit (0) of the opcode indicates the table row and the second digit (3) indicates the table column. This locates an opcode for ADD with two operands. • The first operand (type Gv) indicates a general register that is a word or doubleword depending on the operand-size attribute.
PAGE 456
OPCODE MAP Example A-2. Look-up Example for 2-Byte Opcodes Look-up opcode 0FA4050000000003H for a SHLD instruction using Table A-3. • The opcode is located in row A, column 4. The location indicates a SHLD instruction with operands Ev, Gv, and Ib. Interpret the operands as follows: — Ev: The ModR/M byte follows the opcode to specify a word or doubleword operand. — Gv: The reg field of the ModR/M byte selects a general-purpose register.
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OPCODE MAP — Wdq: The R/M field of the ModR/M byte selects either a 128-bit XMM register or memory location. — Ib: Immediate data is encoded in the subsequent byte of the instruction. • The next byte is the ModR/M byte (C1H). The reg field indicates that the first operand is XMM0. The mod shows that the R/M field specifies a register and the R/M indicates that the second operand is XMM1. • • The last byte is the immediate byte (08H).
PAGE 458
OPCODE MAP A.3 ONE, TWO, AND THREE-BYTE OPCODE MAPS See Table A-2 through Table A-5 below. The tables are multiple page presenations. Rows and columns with sequential relationships are placed on facing pages to make look-up tasks easier. Note that table footnotes are not presented on each page. Table footnotes for each table are presented on the last page of the table. A-8 Vol.
PAGE 459
OPCODE MAP Table A-2. One-byte Opcode Map: (00H — F7H) * 0 1 2 3 0 Eb, Gb Ev, Gv Gb, Eb Eb, Gb Ev, Gv Gb, Eb Eb, Gb Ev, Gv Gb, Eb 1 5 Gv, Ev AL, Ib rAX, Iz Gv, Ev AL, Ib rAX, Iz Gv, Ev AL, Ib rAX, Iz ADC 2 AND 3 XOR Eb, Gb Ev, Gv Gb, Eb Gv, Ev AL, Ib rAX, Iz 6 7 PUSH ESi64 POP ESi64 PUSH SSi64 POP SSi64 SEG=ES (Prefix) DAAi64 SEG=SS (Prefix) AAAi64 eSI REX.RX eDI REX.RXB INCi64 general register / REXo64 Prefixes 4 eAX REX eCX REX.B eDX REX.X eBX REX.
PAGE 460
OPCODE MAP Table A-2. One-byte Opcode Map: (08H — FFH) * 8 9 A B 0 Eb, Gb Ev, Gv Gb, Eb Eb, Gb Ev, Gv Gb, Eb Eb, Gb Ev, Gv Gb, Eb 1 Eb, Gb Ev, Gv Gb, Eb eCX REX.WB eDX REX.WX AL, Ib rAX, Iz Gv, Ev AL, Ib rAX, Iz PUSH DSi64 POP DSi64 Gv, Ev AL, Ib rAX, Iz SEG=CS (Prefix) DASi64 SEG=DS (Prefix) AASi64 Gv, Ev AL, Ib eSI REX.WRX eDI REX.WRXB rAX, Iz eBX REX.WXB eSP REX.WR eBP REX.
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OPCODE MAP Table A-3.
PAGE 462
OPCODE MAP Table A-3.
PAGE 463
OPCODE MAP Table A-3.
PAGE 464
OPCODE MAP Table A-3.
PAGE 465
OPCODE MAP Table A-4. Three-byte Opcode Map: 00H — F7H (First Two Bytes are 0F 38H) * 0 0 1 2 3 4 5 6 7 pshufb Pq, Qq pshufb (66) Vdq, Wdq phaddw Pq, Qq phaddw (66) Vdq, Wdq phaddd Pq, Qq phaddd (66) Vdq, Wdq phaddsw Pq, Qq phaddsw (66) Vdq, Wdq pmaddubsw Pq, Qq pmaddubsw (66) Vdq, Wdq phsubw Pq, Qq phsubw (66) Vdq, Wdq phsubd Pq, Qq phsubd (66) Vdq, Wdq phsubsw Pq, Qq phsubsw (66) Vdq, Wdq 1 2 3 4 5 6 7 8 9 A B C D E F Vol.
PAGE 466
OPCODE MAP Table A-4. Three-byte Opcode Map: 08H — FFH (First Two Bytes are 0F 38H) * 0 8 9 A B psignb Pq, Qq psignb (66) Vdq, Wdq psignw Pq, Qq psignw (66) Vdq, Wdq psignd Pq, Qq psignd (66) Vdq, Wdq pmulhrsw Pq, Qq pmulhrsw (66) Vdq, Wdq 1 C D E pabsb Pq, Qq pabsb (66) Vdq, Wdq pabsw Pq, Qq pabsw (66) Vdq, Wdq pabsd Pq, Qq pabsd (66) Vdq, Wdq F 2 3 4 5 6 7 8 9 A B C D E F NOTES: * All blanks in all opcode maps are reserved and must not be used.
PAGE 467
OPCODE MAP Table A-5. Three-byte Opcode Map: 00H — F7H (First two bytes are 0F 3AH) * 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 A B C D E F Vol.
PAGE 468
OPCODE MAP Table A-5. Three-byte Opcode Map: 08H — FFH (First Two Bytes are 0F 3AH) * 8 9 0 A B C D E F palignr Pq, Qq, Ib palignr(66) Vdq, Wdq, Ib 1 2 3 4 5 6 7 8 9 A B C D E F NOTES: * All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locations. A-18 Vol.
PAGE 469
OPCODE MAP A.4 OPCODE EXTENSIONS FOR ONE-BYTE AND TWOBYTE OPCODES Some 1-byte and 2-byte opcodes use bits 3-5 of the ModR/M byte (the nnn field in Figure A-1) as an extension of the opcode. mod nnn R/M Figure A-1. ModR/M Byte nnn Field (Bits 5, 4, and 3) Opcodes that have opcode extensions are indicated in Table A-6 and organized by group number. Group numbers (from 1 to 16, second column) provide a table entry point.
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OPCODE MAP A.4.2 Opcode Extension Tables See Table A-6 below. Table A-6.
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OPCODE MAP Table A-6.
PAGE 472
OPCODE MAP A.5 ESCAPE OPCODE INSTRUCTIONS Opcode maps for coprocessor escape instruction opcodes (x87 floating-point instruction opcodes) are in Table A-7 through Table A-22. These maps are grouped by the first byte of the opcode, from D8-DF. Each of these opcodes has a ModR/M byte. If the ModR/M byte is within the range of 00H-BFH, bits 3-5 of the ModR/M byte are used as an opcode extension, similar to the technique used for 1-and 2-byte opcodes (see Section A.4).
PAGE 473
OPCODE MAP A.5.2.1 Escape Opcodes with D8 as First Byte Table A-7 and A-8 contain maps for the escape instruction opcodes that begin with D8H. Table A-7 shows the map if the ModR/M byte is in the range of 00H-BFH. Here, the value of bits 3-5 (the nnn field in Figure A-1) selects the instruction. Table A-7. D8 Opcode Map When ModR/M Byte is Within 00H to BFH * nnn Field of ModR/M Byte (refer to Figure A.
PAGE 474
OPCODE MAP A.5.2.2 Escape Opcodes with D9 as First Byte Table A-9 and A-10 contain maps for escape instruction opcodes that begin with D9H. Table A-9 shows the map if the ModR/M byte is in the range of 00H-BFH. Here, the value of bits 3-5 (the nnn field in Figure A-1) selects the instruction. Table A-9.
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OPCODE MAP A.5.2.3 Escape Opcodes with DA as First Byte Table A-11 and A-12 contain maps for escape instruction opcodes that begin with DAH. Table A-11 shows the map if the ModR/M byte is in the range of 00H-BFH. Here, the value of bits 3-5 (the nnn field in Figure A-1) selects the instruction. Table A-11.
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OPCODE MAP A.5.2.4 Escape Opcodes with DB as First Byte Table A-13 and A-14 contain maps for escape instruction opcodes that begin with DBH. Table A-13 shows the map if the ModR/M byte is in the range of 00H-BFH. Here, the value of bits 3-5 (the nnn field in Figure A-1) selects the instruction. Table A-13.
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OPCODE MAP A.5.2.5 Escape Opcodes with DC as First Byte Table A-15 and A-16 contain maps for escape instruction opcodes that begin with DCH. Table A-15 shows the map if the ModR/M byte is in the range of 00H-BFH. Here, the value of bits 3-5 (the nnn field in Figure A-1) selects the instruction. Table A-15.
PAGE 478
OPCODE MAP A.5.2.6 Escape Opcodes with DD as First Byte Table A-17 and A-18 contain maps for escape instruction opcodes that begin with DDH. Table A-17 shows the map if the ModR/M byte is in the range of 00H-BFH. Here, the value of bits 3-5 (the nnn field in Figure A-1) selects the instruction. Table A-17.
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OPCODE MAP A.5.2.7 Escape Opcodes with DE as First Byte Table A-19 and A-20 contain opcode maps for escape instruction opcodes that begin with DEH. Table A-19 shows the opcode map if the ModR/M byte is in the range of 00H-BFH. In this case, the value of bits 3-5 (the nnn field in Figure A-1) selects the instruction. Table A-19.
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OPCODE MAP A.5.2.8 Escape Opcodes with DF As First Byte Table A-21 and A-22 contain the opcode maps for escape instruction opcodes that begin with DFH. Table A-21 shows the opcode map if the ModR/M byte is in the range of 00H-BFH. Here, the value of bits 3-5 (the nnn field in Figure A-1) selects the instruction. Table A-21.
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APPENDIX B INSTRUCTION FORMATS AND ENCODINGS This appendix provides machine instruction formats and encodings of IA-32 instructions. The first section describes the IA-32 architecture’s machine instruction format. The remaining sections show the formats and encoding of general-purpose, MMX, P6 family, SSE/SSE2/SSE3, x87 FPU instructions, and VMX instructions. Those instruction formats also apply to Intel 64 architecture. Instruction formats used in 64-bit mode are provided as supersets of the above. B.
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INSTRUCTION FORMATS AND ENCODINGS B.1.1 Legacy Prefixes The legacy prefixes noted in Figure B-1 include 66H, 67H, F2H and F3H. They are optional, except when F2H, F3H and 66H are used in new instruction extensions. Legacy prefixes must be placed before REX prefixes. Refer to Chapter 2, “Instruction Format,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A, for more information on legacy prefixes. B.1.
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INSTRUCTION FORMATS AND ENCODINGS Table B-1.
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INSTRUCTION FORMATS AND ENCODINGS Table B-3.
PAGE 485
INSTRUCTION FORMATS AND ENCODINGS Table B-5.
PAGE 486
INSTRUCTION FORMATS AND ENCODINGS B.1.4.4 Sign-Extend (s) Bit The sign-extend (s) bit occurs in instructions with immediate data fields that are being extended from 8 bits to 16 or 32 bits. See Table B-7. Table B-7. Encoding of Sign-Extend (s) Bit Effect on 8-Bit Immediate Data s Effect on 16- or 32-Bit Immediate Data 0 None None 1 Sign-extend to fill 16-bit or 32-bit destination None B.1.4.
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INSTRUCTION FORMATS AND ENCODINGS B.1.4.6 Special-Purpose Register (eee) Field When control or debug registers are referenced in an instruction they are encoded in the eee field, located in bits 5 though 3 of the ModR/M byte (an alternate encoding of the sreg field). See Table B-9. Table B-9.
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INSTRUCTION FORMATS AND ENCODINGS Table B-10. Encoding of Conditional Test (tttn) Field tttn Mnemonic 0000 B.1.4.
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INSTRUCTION FORMATS AND ENCODINGS B.1.5 Other Notes Table B-12 contains notes on particular encodings. These notes are indicated in the tables shown in the following sections by superscripts. Table B-12. Notes on Instruction Encoding Symbol A Note A value of 11B in bits 7 and 6 of the ModR/M byte is reserved. B.2 GENERAL-PURPOSE INSTRUCTION FORMATS AND ENCODINGS FOR NON-64-BIT MODES Table B-13 shows machine instruction formats and encodings for general purpose instructions in non-64-bit modes.
PAGE 490
INSTRUCTION FORMATS AND ENCODINGS Table B-13. General Purpose Instruction Formats and Encodings for Non-64-Bit Modes (Contd.
PAGE 491
INSTRUCTION FORMATS AND ENCODINGS Table B-13. General Purpose Instruction Formats and Encodings for Non-64-Bit Modes (Contd.
PAGE 492
INSTRUCTION FORMATS AND ENCODINGS Table B-13. General Purpose Instruction Formats and Encodings for Non-64-Bit Modes (Contd.
PAGE 493
INSTRUCTION FORMATS AND ENCODINGS Table B-13. General Purpose Instruction Formats and Encodings for Non-64-Bit Modes (Contd.
PAGE 494
INSTRUCTION FORMATS AND ENCODINGS Table B-13. General Purpose Instruction Formats and Encodings for Non-64-Bit Modes (Contd.
PAGE 495
INSTRUCTION FORMATS AND ENCODINGS Table B-13. General Purpose Instruction Formats and Encodings for Non-64-Bit Modes (Contd.
PAGE 496
INSTRUCTION FORMATS AND ENCODINGS Table B-13. General Purpose Instruction Formats and Encodings for Non-64-Bit Modes (Contd.
PAGE 497
INSTRUCTION FORMATS AND ENCODINGS Table B-13. General Purpose Instruction Formats and Encodings for Non-64-Bit Modes (Contd.
PAGE 498
INSTRUCTION FORMATS AND ENCODINGS Table B-13. General Purpose Instruction Formats and Encodings for Non-64-Bit Modes (Contd.
PAGE 499
INSTRUCTION FORMATS AND ENCODINGS Table B-13. General Purpose Instruction Formats and Encodings for Non-64-Bit Modes (Contd.
PAGE 500
INSTRUCTION FORMATS AND ENCODINGS Table B-13. General Purpose Instruction Formats and Encodings for Non-64-Bit Modes (Contd.
PAGE 501
INSTRUCTION FORMATS AND ENCODINGS Table B-13. General Purpose Instruction Formats and Encodings for Non-64-Bit Modes (Contd.
PAGE 502
INSTRUCTION FORMATS AND ENCODINGS Table B-13. General Purpose Instruction Formats and Encodings for Non-64-Bit Modes (Contd.
PAGE 503
INSTRUCTION FORMATS AND ENCODINGS Table B-13. General Purpose Instruction Formats and Encodings for Non-64-Bit Modes (Contd.
PAGE 504
INSTRUCTION FORMATS AND ENCODINGS B.2.1 General Purpose Instruction Formats and Encodings for 64-Bit Mode Table B-15 shows machine instruction formats and encodings for general purpose instructions in 64-bit mode. Table B-14. Special Symbols Symbol Application S If the value of REX.W. is 1, it overrides the presence of 66H. w The value of bit W. in REX is has no effect. Table B-15.
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INSTRUCTION FORMATS AND ENCODINGS Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.
PAGE 506
INSTRUCTION FORMATS AND ENCODINGS Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.
PAGE 507
INSTRUCTION FORMATS AND ENCODINGS Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.
PAGE 508
INSTRUCTION FORMATS AND ENCODINGS Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.
PAGE 509
INSTRUCTION FORMATS AND ENCODINGS Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.
PAGE 510
INSTRUCTION FORMATS AND ENCODINGS Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.
PAGE 511
INSTRUCTION FORMATS AND ENCODINGS Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.
PAGE 512
INSTRUCTION FORMATS AND ENCODINGS Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.
PAGE 513
INSTRUCTION FORMATS AND ENCODINGS Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.
PAGE 514
INSTRUCTION FORMATS AND ENCODINGS Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.
PAGE 515
INSTRUCTION FORMATS AND ENCODINGS Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.
PAGE 516
INSTRUCTION FORMATS AND ENCODINGS Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.
PAGE 517
INSTRUCTION FORMATS AND ENCODINGS Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.
PAGE 518
INSTRUCTION FORMATS AND ENCODINGS Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.
PAGE 519
INSTRUCTION FORMATS AND ENCODINGS Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.
PAGE 520
INSTRUCTION FORMATS AND ENCODINGS Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.
PAGE 521
INSTRUCTION FORMATS AND ENCODINGS Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.
PAGE 522
INSTRUCTION FORMATS AND ENCODINGS Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.
PAGE 523
INSTRUCTION FORMATS AND ENCODINGS Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.
PAGE 524
INSTRUCTION FORMATS AND ENCODINGS Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.
PAGE 525
INSTRUCTION FORMATS AND ENCODINGS Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.
PAGE 526
INSTRUCTION FORMATS AND ENCODINGS Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.
PAGE 527
INSTRUCTION FORMATS AND ENCODINGS Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.
PAGE 528
INSTRUCTION FORMATS AND ENCODINGS Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.
PAGE 529
INSTRUCTION FORMATS AND ENCODINGS Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.
PAGE 530
INSTRUCTION FORMATS AND ENCODINGS Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.
PAGE 531
INSTRUCTION FORMATS AND ENCODINGS Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.
PAGE 532
INSTRUCTION FORMATS AND ENCODINGS Table B-15. General Purpose Instruction Formats and Encodings for 64-Bit Mode (Contd.
PAGE 533
INSTRUCTION FORMATS AND ENCODINGS B.3 PENTIUM® PROCESSOR FAMILY INSTRUCTION FORMATS AND ENCODINGS The following table shows formats and encodings introduced by the Pentium processor family. Table B-16. Pentium Processor Family Instruction Formats and Encodings, Non-64-Bit Modes Instruction and Format Encoding CMPXCHG8B – Compare and Exchange 8 Bytes EDX:EAX with memory64 0000 1111 : 1100 0111 : mod 001 r/m Table B-17.
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INSTRUCTION FORMATS AND ENCODINGS B.4 64-BIT MODE INSTRUCTION ENCODINGS FOR SIMD INSTRUCTION EXTENSIONS Non-64-bit mode instruction encodings for MMX Technology, SSE, SSE2, and SSE3 are covered by applying these rules to Table B-19 through Table B-30. Table B-32 lists special encodings (instructions that do not follow the rules below). 1.
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INSTRUCTION FORMATS AND ENCODINGS B.5.2 MMX Technology and General-Purpose Register Fields (mmxreg and reg) When MMX technology registers (mmxreg) are used as operands, they are encoded in the ModR/M byte in the reg field (bits 5, 4, and 3) and/or the R/M field (bits 2, 1, and 0). If an MMX instruction operates on a general-purpose register (reg), the register is encoded in the R/M field of the ModR/M byte. B.5.
PAGE 536
INSTRUCTION FORMATS AND ENCODINGS Table B-19. MMX Instruction Formats and Encodings (Contd.
PAGE 537
INSTRUCTION FORMATS AND ENCODINGS Table B-19. MMX Instruction Formats and Encodings (Contd.
PAGE 538
INSTRUCTION FORMATS AND ENCODINGS Table B-19. MMX Instruction Formats and Encodings (Contd.
PAGE 539
INSTRUCTION FORMATS AND ENCODINGS B.6 P6 FAMILY INSTRUCTION FORMATS AND ENCODINGS Table B-20 shows the formats and encodings for several instructions that were introduced into the IA-32 architecture in the P6 family processors. Table B-20.
PAGE 540
INSTRUCTION FORMATS AND ENCODINGS B.7 SSE INSTRUCTION FORMATS AND ENCODINGS The SSE instructions use the ModR/M format and are preceded by the 0FH prefix byte. In general, operations are not duplicated to provide two directions (that is, separate load and store variants). The following three tables (Tables B-21, B-22, and B-23) show the formats and encodings for the SSE SIMD floating-point, SIMD integer, and cacheability and memory ordering instructions, respectively.
PAGE 541
INSTRUCTION FORMATS AND ENCODINGS Table B-21. Formats and Encodings of SSE Floating-Point Instructions (Contd.
PAGE 542
INSTRUCTION FORMATS AND ENCODINGS Table B-21. Formats and Encodings of SSE Floating-Point Instructions (Contd.
PAGE 543
INSTRUCTION FORMATS AND ENCODINGS Table B-21. Formats and Encodings of SSE Floating-Point Instructions (Contd.
PAGE 544
INSTRUCTION FORMATS AND ENCODINGS Table B-21. Formats and Encodings of SSE Floating-Point Instructions (Contd.
PAGE 545
INSTRUCTION FORMATS AND ENCODINGS Table B-21. Formats and Encodings of SSE Floating-Point Instructions (Contd.
PAGE 546
INSTRUCTION FORMATS AND ENCODINGS Table B-21. Formats and Encodings of SSE Floating-Point Instructions (Contd.
PAGE 547
INSTRUCTION FORMATS AND ENCODINGS Table B-22. Formats and Encodings of SSE Integer Instructions (Contd.
PAGE 548
INSTRUCTION FORMATS AND ENCODINGS Table B-23.
PAGE 549
INSTRUCTION FORMATS AND ENCODINGS B.8 SSE2 INSTRUCTION FORMATS AND ENCODINGS The SSE2 instructions use the ModR/M format and are preceded by the 0FH prefix byte. In general, operations are not duplicated to provide two directions (that is, separate load and store variants). The following three tables show the formats and encodings for the SSE2 SIMD floating-point, SIMD integer, and cacheability instructions, respectively.
PAGE 550
INSTRUCTION FORMATS AND ENCODINGS Table B-25. Formats and Encodings of SSE2 Floating-Point Instructions (Contd.
PAGE 551
INSTRUCTION FORMATS AND ENCODINGS Table B-25. Formats and Encodings of SSE2 Floating-Point Instructions (Contd.
PAGE 552
INSTRUCTION FORMATS AND ENCODINGS Table B-25. Formats and Encodings of SSE2 Floating-Point Instructions (Contd.
PAGE 553
INSTRUCTION FORMATS AND ENCODINGS Table B-25. Formats and Encodings of SSE2 Floating-Point Instructions (Contd.
PAGE 554
INSTRUCTION FORMATS AND ENCODINGS Table B-25. Formats and Encodings of SSE2 Floating-Point Instructions (Contd.
PAGE 555
INSTRUCTION FORMATS AND ENCODINGS Table B-25. Formats and Encodings of SSE2 Floating-Point Instructions (Contd.
PAGE 556
INSTRUCTION FORMATS AND ENCODINGS Table B-25. Formats and Encodings of SSE2 Floating-Point Instructions (Contd.
PAGE 557
INSTRUCTION FORMATS AND ENCODINGS Table B-25. Formats and Encodings of SSE2 Floating-Point Instructions (Contd.
PAGE 558
INSTRUCTION FORMATS AND ENCODINGS Table B-26. Formats and Encodings of SSE2 Integer Instructions (Contd.
PAGE 559
INSTRUCTION FORMATS AND ENCODINGS Table B-26. Formats and Encodings of SSE2 Integer Instructions (Contd.
PAGE 560
INSTRUCTION FORMATS AND ENCODINGS Table B-26. Formats and Encodings of SSE2 Integer Instructions (Contd.
PAGE 561
INSTRUCTION FORMATS AND ENCODINGS Table B-26. Formats and Encodings of SSE2 Integer Instructions (Contd.
PAGE 562
INSTRUCTION FORMATS AND ENCODINGS Table B-26. Formats and Encodings of SSE2 Integer Instructions (Contd.
PAGE 563
INSTRUCTION FORMATS AND ENCODINGS Table B-26. Formats and Encodings of SSE2 Integer Instructions (Contd.
PAGE 564
INSTRUCTION FORMATS AND ENCODINGS Table B-26. Formats and Encodings of SSE2 Integer Instructions (Contd.
PAGE 565
INSTRUCTION FORMATS AND ENCODINGS Table B-27.
PAGE 566
INSTRUCTION FORMATS AND ENCODINGS B.9 SSE3 FORMATS AND ENCODINGS TABLE The tables in this section provide SSE3 formats and encodings. Some SSE3 instructions require a mandatory prefix (66H, F2H, F3H) as part of the two-byte opcode. These prefixes are included in the tables. When in IA-32e mode, use of the REX.R prefix permits instructions that use general purpose and XMM registers to access additional registers. Some instructions require the REX.W prefix to promote the instruction to 64-bit operation.
PAGE 567
INSTRUCTION FORMATS AND ENCODINGS Table B-28. Formats and Encodings of SSE3 Floating-Point Instructions (Contd.) Instruction and Format mem to xmmreg Encoding 01100110:00001111:01111101: mod xmmreg r/m HSUBPS—Sub horizontally packed SP FP numbers XMM2/Mem to XMM1 xmmreg2 to xmmreg1 11110010:00001111:01111101:11 xmmreg1 xmmreg2 mem to xmmreg 11110010:00001111:01111101: mod xmmreg r/m Table B-29.
PAGE 568
INSTRUCTION FORMATS AND ENCODINGS Table B-30. Formats and Encodings for SSE3 Integer and Move Instructions (Contd.
PAGE 569
INSTRUCTION FORMATS AND ENCODINGS Table B-31. Formats and Encodings for SSSE3 Instructions (Contd.
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INSTRUCTION FORMATS AND ENCODINGS Table B-31. Formats and Encodings for SSSE3 Instructions (Contd.
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INSTRUCTION FORMATS AND ENCODINGS Table B-31. Formats and Encodings for SSSE3 Instructions (Contd.
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INSTRUCTION FORMATS AND ENCODINGS Table B-31. Formats and Encodings for SSSE3 Instructions (Contd.) Instruction and Format Encoding PSIGNW—Packed Sign Words mmreg to mmreg 0000 1111:0011 1000: 0000 1001:11 mmreg1 mmreg2 mem to mmreg 0000 1111:0011 1000: 0000 1001: mod mmreg r/m xmmreg to xmmreg 0110 0110:0000 1111:0011 1000: 0000 1001:11 xmmreg1 xmmreg2 mem to xmmreg 0110 0110:0000 1111:0011 1000: 0000 1001: mod xmmreg r/m B.
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INSTRUCTION FORMATS AND ENCODINGS Table B-32. Special Case Instructions Promoted Using REX.W (Contd.
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INSTRUCTION FORMATS AND ENCODINGS Table B-32. Special Case Instructions Promoted Using REX.W (Contd.
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INSTRUCTION FORMATS AND ENCODINGS Table B-32. Special Case Instructions Promoted Using REX.W (Contd.
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INSTRUCTION FORMATS AND ENCODINGS Table B-32. Special Case Instructions Promoted Using REX.W (Contd.) Instruction and Format Encoding mmreg to reg64 0100 1R0B 0000 1111:1101 0111:11 r64 mmreg xmmreg to reg32 0100 0RXB 0110 0110 0000 1111:1101 0111:11 r32 mmreg xmmreg to reg64 0110 0110 0000 1111:1101 0111:11 r64 xmmreg B.12 FLOATING-POINT INSTRUCTION FORMATS AND ENCODINGS Table B-33 shows the five different formats used for floating-point instructions.
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INSTRUCTION FORMATS AND ENCODINGS The Mod and R/M fields of the ModR/M byte have the same interpretation as the corresponding fields of the integer instructions. The SIB byte and disp (displacement) are optionally present in instructions that have Mod and R/M fields. Their presence depends on the values of Mod and R/M, as for integer instructions. Table B-34 shows the formats and encodings of the floating-point instructions. Table B-34.
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INSTRUCTION FORMATS AND ENCODINGS Table B-34. Floating-Point Instruction Formats and Encodings (Contd.
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INSTRUCTION FORMATS AND ENCODINGS Table B-34. Floating-Point Instruction Formats and Encodings (Contd.
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INSTRUCTION FORMATS AND ENCODINGS Table B-34. Floating-Point Instruction Formats and Encodings (Contd.) Instruction and Format FLDZ – Load +0.
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INSTRUCTION FORMATS AND ENCODINGS Table B-34. Floating-Point Instruction Formats and Encodings (Contd.
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INSTRUCTION FORMATS AND ENCODINGS B.13 VMX INSTRUCTIONS Table B-35 describes virtual-machine extensions (VMX). Table B-35. Encodings for VMX Instructions Instruction and Format Encoding VMCALL—Call to VM Monitor Call VMM: causes VM exit.
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INSTRUCTION FORMATS AND ENCODINGS Table B-35. Encodings for VMX Instructions Instruction and Format Encoding VMXOFF—Leave VMX Operation Leave VMX. 00001111 00000001 11000100 VMXON—Enter VMX Operation Enter VMX. 11110011 000011111 11000111: mod 110 r/m Vol.
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INSTRUCTION FORMATS AND ENCODINGS B-104 Vol.
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APPENDIX C INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS The two tables in this appendix itemize the Intel C/C++ compiler intrinsics and functional equivalents for the Intel MMX technology, SSE, SSE2, SSE3, and SSSE3 instructions. There may be additional intrinsics that do not have an instruction equivalent. It is strongly recommended that the reader reference the compiler documentation for the complete list of supported intrinsics. Please refer to http://www.intel.
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INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS The packed values are represented in right-to-left order, with the lowest value being used for scalar operations. Consider the following example operation: double a[2] = {1.0, 2.0}; __m128d t = _mm_load_pd(a); The result is the same as either of the following: __m128d t = _mm_set_pd(2.0, 1.0); __m128d t = _mm_setr_pd(1.0, 2.0); In other words, the XMM register that holds the value t will look as follows: 2.0 127 1.
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INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS Table C-1.
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INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS Table C-1. Simple Intrinsics (Contd.
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INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS Table C-1. Simple Intrinsics (Contd.
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INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS Table C-1. Simple Intrinsics (Contd.
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INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS Table C-1. Simple Intrinsics (Contd.
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INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS Table C-1. Simple Intrinsics (Contd.
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INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS Table C-1. Simple Intrinsics (Contd.
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INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS Table C-1. Simple Intrinsics (Contd.
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INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS Table C-1. Simple Intrinsics (Contd.
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INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS Table C-1. Simple Intrinsics (Contd.
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INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS Table C-1. Simple Intrinsics (Contd.
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INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS Table C-1. Simple Intrinsics (Contd.
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INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS C.2 COMPOSITE INTRINSICS Table C-2.
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INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS Table C-2. Composite Intrinsics (Contd.
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INDEX FOR VOLUMES 2A & 2B Numerics 64-bit mode control and debug registers, 2-15 default operand size, 2-15 direct memory-offset MOVs, 2-14 general purpose encodings, B-24 immediates, 2-14 introduction, 2-9 machine instructions, B-1 reg (reg) field, B-4 REX prefixes, 2-9, B-2 RIP-relative addressing, 2-14 SIMD encodings, B-54 special instruction encodings, B-92 summary table notation, 3-7 A AAA instruction, 3-19 AAD instruction, 3-21 AAM instruction, 3-23 AAS instruction, 3-25 Access rights, segment descri
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INDEX Compatibility, software, 1-4 Condition code flags, EFLAGS register, 3-115 Condition code flags, x87 FPU status word flags affected by instructions, 3-15 setting, 3-404, 3-406, 3-409 Conditional jump, 3-495 Conforming code segment, 3-514 Constants (floating point), loading, 3-342 Control registers, moving values to and from, 3-597 Cosine, x87 FPU operation, 3-310, 3-379 CPL, 3-109, 4-394 CPUID instruction, 3-160, 3-175 36-bit page size extension, 3-175 APIC on-chip, 3-174 basic CPUID information, 3-16
PAGE 603
INDEX DF (direction) flag, EFLAGS register, 3-106, 3-136, 3-462, 3-544, 3-655, 4-18, 4-287, 4-331 Displacement (operand addressing), 2-4 DIV instruction, 3-262 Divide error exception (#DE), 3-262 DIVPD instruction, 3-266 DIVPS instruction, 3-269 DIVSD instruction, 3-272 DIVSS instruction, 3-275 DS register, 3-135, 3-522, 3-543, 3-654, 4-17 E EDI register, 4-286, 4-331, 4-337 Effective address, 3-528 EFLAGS register condition codes, 3-119, 3-301, 3-307 flags affected by instructions, 3-14 loading, 3-511 po
PAGE 604
INDEX FRSTOR instruction, 3-368 FS register, 3-522 FSAVE instruction, 3-371 FSAVE/FNSAVE instructions, 3-368 FSCALE instruction, 3-375 FSIN instruction, 3-377 FSINCOS instruction, 3-379 FSQRT instruction, 3-382 FST instruction, 3-384 FSTCW instruction, 3-387 FSTENV instruction, 3-390 FSTP instruction, 3-384 FSTSW instruction, 3-393 FSUB instruction, 3-396 FSUBP instruction, 3-396 FSUBR instruction, 3-400 FSUBRP instruction, 3-400 FTST instruction, 3-404 FUCOM instruction, 3-406 FUCOMI instruction, 3-307 FU
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INDEX Interrupts interrupt vector 4, 3-465 returning from, 3-484 software, 3-465 INTn instruction, 3-465 INTO instruction, 3-465 Intrinsics compiler functional equivalents, C-1 composite, C-15 description of, 3-12 list of, C-1 simple, C-2 INVD instruction, 3-480 INVLPG instruction, 3-482 IOPL (I/O privilege level) field, EFLAGS register, 3-109, 4-220, 4-332 IRET instruction, 3-484 IRETD instruction, 3-484 J Jcc instructions, 3-495 JMP instruction, 3-501 Jump operation, 3-501 L L1 Context ID, 3-172 LAHF i
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INDEX MONITOR instruction, 3-588 CPUID flag, 3-172 feature data, 3-180 MOV instruction, 3-591 MOV instruction (control registers), 3-597 MOV instruction (debug registers), 3-600 MOVAPD instruction, 3-602 MOVAPS instruction, 3-604 MOVD instruction, 3-606 MOVDDUP instruction, 3-610 MOVDQ2Q instruction, 3-617 MOVDQA instruction, 3-613 MOVDQU instruction, 3-615 MOVHLPS instruction, 3-619 MOVHPD instruction, 3-621 MOVHPS instruction, 3-623 MOVLHP instruction, 3-626 MOVLHPS instruction, 3-626 MOVLPD instruction,
PAGE 607
INDEX P P6 family processors description of, 1-1 machine encodings, B-59 PABSB instruction, 4-22 PABSD instruction, 4-22 PABSW instruction, 4-22 PACKSSDW instruction, 4-26 PACKSSWB instruction, 4-26 PACKUSWB instruction, 4-30 PADDB instruction, 4-33 PADDD instruction, 4-33 PADDQ instruction, 4-37 PADDSB instruction, 4-40 PADDSW instruction, 4-40 PADDUSB instruction, 4-44 PADDUSW instruction, 4-44 PADDW instruction, 4-33 PALIGNR instruction, 4-48 PAND instruction, 4-51 PANDN instruction, 4-54 PAUSE instruct
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INDEX PSUBUSW instruction, 4-198 PSUBW instruction, 4-187 PUNPCKHBW instruction, 4-202 PUNPCKHDQ instruction, 4-202 PUNPCKHQDQ instruction, 4-202 PUNPCKHWD instruction, 4-202 PUNPCKLBW instruction, 4-207 PUNPCKLDQ instruction, 4-207 PUNPCKLQDQ instruction, 4-207 PUNPCKLWD instruction, 4-207 PUSH instruction, 4-212 PUSHA instruction, 4-217 PUSHAD instruction, 4-217 PUSHF instruction, 4-220 PUSHFD instruction, 4-220 PXOR instruction, 4-223 R RC (rounding control) field, x87 FPU control word, 3-333, 3-342, 3
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INDEX floating-point encodings, B-69 integer instruction encodings, B-77 SSE3 CPUID flag, 3-172 SSE3 extensions CPUID flag, 3-172 event mgmt instruction encodings, B-87 floating-point instruction encodings, B-86 integer instruction encodings, B-87, B-88 SSSE3 extensions, B-88 CPUID flag, 3-172 Stack, pushing values on, 4-213 Status flags, EFLAGS register, 3-119, 3-122, 3-301, 3-307, 3-498, 4-292, 4-373 STC instruction, 4-330 STD instruction, 4-331 Stepping information, 3-180 STI instruction, 4-332 STMXCSR
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INDEX loading, 3-346 restoring, 3-368 saving, 3-371, 3-390, 3-393 TOP field, 3-328 x87 FPU flags affected by instructions, 3-15 x87 FPU tag word, 3-346, 3-368, 3-371, 3-390 XADD instruction, 3-541, 4-403 XCHG instruction, 3-541, 4-406 XLAB instruction, 4-409 INDEX-10 Vol.
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