CK00 Clock Synthesizer/Driver Design Guidelines November 13, 2000 Order Number 249206-001
CK00 Clock Synthesizer/Driver Design Guidelines Page 2
CK00 Clock Synthesizer/Driver Design Guidelines Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
CK00 Clock Synthesizer/Driver Design Guidelines 1. INTRODUCTION ...................................................................................................6 1.1 Clock Synthesizer Overview ...........................................................................................................6 1.2 Applicable Documents.....................................................................................................................6 1.3 Drive Specification.................................
CK00 Clock Synthesizer/Driver Design Guidelines 6.7 Defined option for PCI_bankSTOP# functionality ......................................................................49 6.8 I C Considerations .........................................................................................................................49 6.9 I C Byte Locations for CKFF .........................................................................................................
CK00 Clock Synthesizer/Driver Design Guidelines 1. Introduction This document provides technical specifications for development of the CK00 class of clock ® ® components, based on requirements of the Intel Pentium 4 processor and other Intel Architecture (IA) platforms. The CK00 is intended to be applicable to a wide variety of system implementations. The CK00 class of clocks contains new features, most notably the adoption of a new differential clock output type. 1.
CK00 Clock Synthesizer/Driver Design Guidelines IBIS Reference The IBIS Open Forum is an industry-wide forum that controls the official IBIS specification. Minutes of IBIS meetings, email correspondence, proposals for specification changes, etc. are online at “vhdl.org”. To join in the email discussions , send a message to “ibisrequest@vhdl.org” and request that your name be added to the IBIS mail reflector. Be sure to include your email address. The IBIS home page can be found at http://www.eia.
CK00 Clock Synthesizer/Driver Design Guidelines CKx_WBY Differential Hosts 14M Mref, Mref_b 66M reference 14.318MHz seed CKFF 66MHz seed 3V66’s Divide by Two 33MHz PCI’s PLL 14.318, 48 CKx_SKS Mref Seed Clks Diff Clks PLL 3V66s Divide by Two PCIs PLL 14.318, 48 Figure 1.
CK00 Clock Synthesizer/Driver Design Guidelines 2. Example Circuits The differential Host clock signals are to be established by a current mode current steering buffer conceptually similar to that shown in Figure 2.1. IOut is established by a mirrored and scaled copy of a reference current, IRef. The method of establishing IRef is explained in Section 2.1 in the manner believed to be the best known method. Internal External 3.3V Iout R=Zo R=Zo Figure 2.1 – Conceptual Output Circuit 2.
CK00 Clock Synthesizer/Driver Design Guidelines Where RRef is the external reference resistor and 1.1V was chosen for the reference voltage, according to the following reasoning: 1) The voltage is close to the voltage that will be present at the final output of the buffer when generating interesting values of Voh (ie. 0.71V). Thus, the reference voltage was chosen close to this value to provide an environment better for current mirror matching. 2) 1.
CK00 Clock Synthesizer/Driver Design Guidelines scale factors set to either IOut = 5*IRef or IOut = 6*IRef. As shown in Section 8.2, RRef=475 corresponds to an IRef of 2.32mA. Vdd ~ 3.3V IRef = [Vdd - Vdiode] / Rr Vdiode uncertainty would contribute large inaccuracy IRef + Vdiode ~ 0.5V to 1.0V - RRef Figure 2.3 – Conventional Current Reference Circuit – not used The transistor MDum was included in Figure 2.
CK00 Clock Synthesizer/Driver Design Guidelines Series Isolation Resistor C_die + Cpkg = 1 - 6 pF Rs = ~ 33 R=Zo Rs = ~ 33 R=Zo Figure 2.4 – Illustration of Series Isolation Resistance Rs The series resistors RS have the tradeoff of reducing the amount of voltage headroom available to the current driving circuit. For the principal Voh configuration of Voh=0.7V, the voltage at the output of the buffer will be in the range of 1.1V and be similar to the voltage at the reference resistor RRef.
CK00 Clock Synthesizer/Driver Design Guidelines Effect of Rs on Overshoot and Ringback Ringback and Overshoot (V relative to Voh) Relative to Voh Example Only Vovst + 0.1V Vrbk 0 Vovst Vrbk - 0.13V 1 10 20 30 40 Rs (Ohms) Figure 2.5 – Effect of Rs on Overshoot and Ringback for Example System It should be noted that the voltages in Figure 2.5 could actually be much worse, depending on how the reflections are damped in the rest of the network.
CK00 Clock Synthesizer/Driver Design Guidelines 3. Electrical Requirements This section details the electrical parameters for the differential host clock buffers, multiple types of 3.3V clock output buffers, and a 5.0V-compatible 3.3V PCI clock driver output buffer. The different types of 3.3V drivers are needed to compensate for different board layout topologies. Due to voltage and timing constraints, low-voltage differential swing outputs have been defined.
CK00 Clock Synthesizer/Driver Design Guidelines Table 3.2 Absolute Maximum DC I/O Symbol Parameter Min. Max. Units Notes Vih3 3.3V Input High Voltage -0.5 4.6 V 1 Vil3 3.3V Input Low Voltage −0.5 V Input ESD protection 2000 V ESD prot. 2 Notes: 1. Maximum Vih is not to exceed maximum 0.7V above VDD. 2. Human body model. Table 3.3 DC Operating Requirements Symbol Parameter VDD3 3.3V Supply Voltage Vih3 3.3V Input High Voltage Vil3 3.
CK00 Clock Synthesizer/Driver Design Guidelines Table 3.3 Maximum Current Draw Part Parameter Min. Max. Units Notes CKx_SKS Current from 3.3V supply N/A 250 mA 1,2,3,4 CKx_WBY Current from 3.3V supply N/A 200 mA 1,2,3,4 CKFF Current from 3.3V supply N/A 350 mA 1,4 Notes: 1. Conditions: Max Power supply (3.465V), all active 2. Configured with 475 Ohm current reference resistor at Iout=6*Iref 3. Host = 133MHz 4.
CK00 Clock Synthesizer/Driver Design Guidelines 3.2 Buffer Specifications: The V/I curves, and Trise/Tfall specifications are targeted at achieving acceptable switching behavior under the lumped load conditions as described in Section 4 of this specification. Pullup and pull-down sides for each of the buffers have separate V/I curves, which are provided, in the following sections.
CK00 Clock Synthesizer/Driver Design Guidelines 3.2.1 TYPE 3: Buffer Characteristics Table 3.5 Operating Requirements Symbol Parameter Condition Min Iohmin Pull-Up Current Vout = 1.0 V -29 Iohmax Pull-Up Current Vout = 3.135 V Iolmin Pull-Down Current Vout = 1.95 V Iolmax Pull-Down Current Vout = 0.4 V trh 3.3V Type 3 Output Rise Edge Rate 3.3V ±5% tfh Typ Max -23 29 Units Notes mA 1 mA 1 mA 1 27 mA 1 0.5 2.0 V/nS 2 0.5 2.0 V/nS 2 @ 0.4V – 2.4 V 3.3V ±5% 3.
CK00 Clock Synthesizer/Driver Design Guidelines Type 3 Pull-Down Pull-Down I (mA) I (mA) min typ 0 0 9 13 14 21 17 26 20 29 25 37 26 39 27 41 28 43 29 45 29 45 45 Voltage (V) 0 0.4 0.65 0.85 1 1.4 1.5 1.65 1.8 1.95 3.135 3.6 I (mA) max 0 27 41 52 59 76 79 84 88 92 102 102 120 100 30 50 90 min typ max 80 IOL 60 40 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 Vout Figure 3.2 TYPE 3: Pull-Down Characteristics Notes (Figure 3.2): 1. Must meet the temperature and voltage range specified in 2. Table 3.
CK00 Clock Synthesizer/Driver Design Guidelines 3.6 Test Point 3.135 2.4 DC Drive Point 1.4 Voltage (V) Voltage (V) 0 1 1.4 1.5 1.65 1.8 2 2.4 2.6 3.135 3.3 3.6 Pull-Up I (mA) I (mA) I (mA) min typ max -34 -59 -195 -33 -58 -194 -31 -55 -189 -30 -54 -184 -28 -52 -172 -25.5 -50 -159 -22 -46 -140 -14.5 -35 -100 -11 -28 -83 0 -6 -33 0 -19 0 AC Drive Point 0 -31 Typical Conditions -55 -189 Current (mA) Figure 3.3 TYPE 5: Pull-Up Characteristics Notes (Figure 3.3): 1.
CK00 Clock Synthesizer/Driver Design Guidelines VDD AC Drive Point Voltage (V) Pull-Down Voltage I (mA) I(mA) I (mA) (V) min typ max 0 0 0 0 0.4 9.4 18 38 0.65 14 30 64 0.85 17.7 38 84 1 20 43 100 1.4 26.5 53 139 1.5 28 55 148 1.65 29 56 163 1.8 30 57 175 1.95 30 58 178 3.135 31 59 187 3.6 32 59 188 Typical Conditions 1.8 DC Drive Point 0.3 Test Point 0 0 30 57 175 Current (mA) Figure 3.4 TYPE 5: PCI Clock Output Buffer Pull-Down Characteristics Notes (Figure 3.4): 1.
CK00 Clock Synthesizer/Driver Design Guidelines 3.2.3 Type X1 Current-mode Output Buffer Characteristics The current-mode output buffer details and current reference circuit details are contained elsewhere in this document. For the purposes of this section, the following parameters are used to specify output buffer characteristics: 1) Output impedance of the current mode buffer circuit – Ro (See Figure 3.5) 2) Minimum and maximum required voltage operation range of the circuit – Vop (See Figure 3.
CK00 Clock Synthesizer/Driver Design Guidelines The various output current configurations are shown in the appendix of this document. For all configurations, the deviation from the expected output current is +/- 7% as shown in Table 3.8. Table 3.8 – Current Accuracy Conditions Configuration Load Iout Vdd = nominal (3.30V) All combinations of M0, M1 and Rr shown in Table 6.9 Nominal test load for given configuration Iout Vdd = 3.30 +/- 5% All combinations of M0, M1 and Rr shown in Table 6.
CK00 Clock Synthesizer/Driver Design Guidelines 4. AC Timing 4.1 Timing Requirements Table 4.1 AC Timing Requirements Symbol TPeriod AbsMinPeriod Parameter Host CLK period - average Absolute minimum Host CLK Period 133 MHz Host 100 MHz Host Min Max Min Max Units Notes 7.5 7.65 10.0 10.2 nS 11, 14 7.35 N/A 9.85 N/A nS 11, 14 11, 13, 17 Ioh Output Current 12.9 14.9 12.9 14.9 mA (Voh) (Voltage at given load) (0.65) (0.74) (0.65) (0.74) (V) Vol Vss = 0.0 0.05 Vss = 0.
CK00 Clock Synthesizer/Driver Design Guidelines TLOW 3V66 CLK low time 5.05 N/A 5.05 N/A 6 ,10 TRISE 3V66 CLK rise time 0.5 2.0 0.5 2.0 8 TFALL 3V66 CLK fall time 0.5 2.0 0.5 2.0 8 TPeriod PCI CLK period 30.0 N/A 30.0 N/A THIGH PCI CLK high time 12.0 N/A 12.0 TLOW PCI CLK low time 12.0 N/A TRISE PCI CLK rise time 0.5 TFALL PCI CLK fall time tpZL, tpZH tpLZ, tpZH tstable All clock Stabilization from power-up nS 2, 3, 9 N/A nS 5 ,10 12.0 N/A nS 6 ,10 2.
CK00 Clock Synthesizer/Driver Design Guidelines Table 4.2 Group Skew And Jitter Limits Output group Pin-pin Skew Cycle-Cycle Jitter Duty Cycle Nom Vdd Skew, jitter measure point Or Pair-toPair Skew MAX Host 150 pS 200 pS 45/55 N/A Crossing 100 pS 150pS 45/55 N/A Crossing MRef N/A 250 pS 45/55 3.3 V 1.5 V 48MHz N/A 350 pS 45/55 3.3 V 1.5 V 3V66 250 pS 300 pS 45/55 3.3 V 1.5 V PCI 500 pS 500 pS 45/55 3.3 V 1.5 V REF N/A 1000 pS 45/55 3.3V 1.
CK00 Clock Synthesizer/Driver Design Guidelines 4.1.2 Multiple PLL Jitter Tracking Specification. The clock driver’s closed loop jitter bandwidth must be set low to allow any PLL-based device to track the jitter created by the clock driver. This 1:1 relationship is critical when the clock driver drives two or more PLLs. A worst-case timing issue would occur if one PLL attenuated the jitter and another device (PLL or non-PLL) tracked the jitter completely.
CK00 Clock Synthesizer/Driver Design Guidelines Rs Rp Test nodes Rs 5. Rp Test and Measurement The tables below provide acceptable lumped load test loads over which the vendor is expected to test and guarantee all AC parameters for the clock driver. The vendor is encouraged to provide information on the correlation between lumped load performance and system performance as an applications exercise to fully describe the operation of the product. Table 5.
CK00 Clock Synthesizer/Driver Design Guidelines Table 5.3 Resistive Lumped Test Loads for Differential Host Clock Clock Host Clocks – 60 ohm configuration Host Clocks – 50 ohm configuration Host Clocks – Double Terminated configuration Rs 33.2 1% 33.2 1% Rp 61.9 1% 49.9 1% Units Ohms 0 24.9 1% Ohms Notes 2, 3, 5 Ohms 1, 2, 3, 5 4 1. Expected test load configuration unless otherwise noted. This is a 50 Ohm environment test load. This assumes device is configured for 50 Ohm environment. 2.
CK00 Clock Synthesizer/Driver Design Guidelines 3.3 Volt Measure Points Vdd3 Voh = 2.4V Vih = 2.0V 1.5V Vih = 0.8V Voh = 0.4V Figure 5.
CK00 Clock Synthesizer/Driver Design Guidelines 6. Appendices 6.1 Pin-outs and Features The following addendum defines a generic pin-out and base requirements for Intel Architecture based platforms. It is intended to be used with another clock driver or drivers to clock the memory devices. CKx_SKS clock chip (56 SSOP and 56 TSSOP): Description: This clock is intended to be used in single processor systems and two processor systems.
CK00 Clock Synthesizer/Driver Design Guidelines Table 6.1 CKx_SKS Pin Description Table Pin Type Qty Symbol Description 55 3.3V output 1 3VMref 3V reference to memory clock driver 54 3.3V output 1 3VMRef_b 3V reference to memory clock driver (out of phase with 3Vmref) 52 Input 1 Spread# Invokes Spread Spectrum functionality on the Differential Host clocks, MRef/MRef_b clocks, 66MHz clocks, and 33MHz PCI clocks. Active Low.
CK00 Clock Synthesizer/Driver Design Guidelines CKx_WBY clock chip (48 SSOP Package and 48 TSSOP): Description: This is intended as the main clock source in certain multiple-chip clock partitions. This clock is intended to be used with the FF. The WBY/FF pair is intended to be used in twoprocessor, and four-processor platforms. ! Six Differential Host Clock Pairs ! Two 3V Single Ended memory reference clocks 180 degrees out of phase ! One 66MHz reference output ! One14.
CK00 Clock Synthesizer/Driver Design Guidelines Table 6.2 CKx_WBY Pin Description Table Pin Type Qty Symbol Description 45,44 Buffer X1 Host/Host_b Host pair 1 42,41 Buffer X1 Host/Host_b Host pair 2 39,38 Buffer X1 Host/Host_b Host pair 3 36,35 Buffer X1 Host/Host_b Host pair 4 33,32 Buffer X1 Host/Host_b Host pair 5 30,29 Buffer X1 Host/Host_b Host pair 6 27 Special 1 I_Ref This pin establishes the reference current for the Host pairs.
CK00 Clock Synthesizer/Driver Design Guidelines CKFF clock chip (48 SSOP and 48 TSSOP): Description: This is a slave clock to the WBY. This can also be used as a slave clock to future variants of the WBY. For Spread Spectrum Tracking, there must not be a PLL in the path of the 66MHz clocks or the 33MHz PCI clocks. The 66MHz and 33MHz clocks are intended to be buffered and/or divided from the 66_in seed clock input.
CK00 Clock Synthesizer/Driver Design Guidelines 2 2 I C is not implemented, pins 29 and 30 should be immune to I C signals to allow placement on 2 a platform which has I C implemented. Table 6.3 CKFF Pin Description Table Pin Type Qty Symbol Description 55,54 3.3V output 2 Ref 14.318MHz 3.3V outputs 51,50,47,46,43,42 3.3V output 6 3V66 66MHz 3.3V outputs 37,36 3.3V output 2 48MHz 48MHz output. See accuracy specifications.
CK00 Clock Synthesizer/Driver Design Guidelines CKx_RGR clock chip Future pin-out (48 TSSOP and 48 SSOP): Description: This clock is intended as a future spin of the SKS. This clock is intended for single processor platforms. ! Two Differential Host Clock Pairs ! Two 3V Single Ended memory reference clocks 180 degrees out of phase ! Three 3V, 66MHz Clocks ! Ten 3V, 33MHz PCI Clocks ! Two 48MHz Clocks ! Two 14.
CK00 Clock Synthesizer/Driver Design Guidelines Table 6.4 CKx_RGR Pin Description Table Pin 48,1 Type Output and Qty 2 Latched Input Symbol Ref/MultSel0 Description Ref/MultSel1 MultSel0 and MultSel1 inputs are sensed on power-up and then internally latched prior to the pin being used for output of 3V 14.318MHz clocks.
CK00 Clock Synthesizer/Driver Design Guidelines 6.2 Select Pin Logic Table 6.
CK00 Clock Synthesizer/Driver Design Guidelines Table 6.
CK00 Clock Synthesizer/Driver Design Guidelines Table 6.7 Select Functions – CKx_WBY SEL100/133 SELA SELB Function 0 0 0 0 0 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 Active 100MHz Active 100MHz, ref_out Low, 66_out Low, 3VMRef and 3VMRef_b Low (Reserved) HI-Z all outputs Active 133MHz (Reserved) (Reserved) Test Mode SEL 100/133 SELA SELB Host MRef 66M seed 14.318M seed 0 0 0 100MHz 50MHz 66MHz 14.
CK00 Clock Synthesizer/Driver Design Guidelines Table 6.
CK00 Clock Synthesizer/Driver Design Guidelines Table 6.9 Host Swing Select Functions – CKx_SKS, CKx_WBY, CKx_RGR MultSel0 MultSel1 Board Target Trace/Term Z 0 0 60 ohms 0 0 50 ohms 0 1 60 ohms 0 1 50 ohms 1 0 60 ohms 1 0 50 ohms 1 1 60 ohms 1 1 50 ohms Reference R, Iref = Vdd/(3*Rr) Rr = 475 1%, Iref=2.32mA Rr = 475 1%, Iref=2.32mA Rr = 475 1% Iref=2.32mA Rr = 475 1%, Iref=2.32mA Rr = 475 1%, Iref=2.32mA Rr = 475 1%, Iref=2.32mA Rr = 475 1%, Iref=2.32mA Rr = 475 1%, Iref=2.
CK00 Clock Synthesizer/Driver Design Guidelines 6.3 Spread Spectrum Clocking (SSC) Criteria: Spread Spectrum functionality on the CK00 class of clock drivers is required and acts as an on/off switch for different forms of spread spectrum modulation techniques. Any given system design may or may not use this feature due to platform-level timing issues. The following specifications are included in the current CK00 definition: 1. No external modulation frequency source is required 2.
CK00 Clock Synthesizer/Driver Design Guidelines Highest peak ∆ non-SSC SSC δ of fnom fnom Figure 6 Spectral Fundamental Frequency Comparison 7. To achieved sufficient system-level EMI reduction, it is desired that SSC reduce the spectral peaks in the non-SSC mode by the amount specified in Table 4.
CK00 Clock Synthesizer/Driver Design Guidelines output clocks, is shown in Figure 7, as functions of modulation frequency, modulation profile, and spread amount. This plot is obtained through PLL behavior simulations assuming a jitter-free ideal modulated input clock to the PLL. The parameters of the simulated PLL are: (VCO gain) * (charge-pump current) = 2800 (Hz/V)(A), nd feedback divider =2, 2 -order filter: C1 = 11 pF; C2 = 356 pF; R = 9.75 kΩ. 9.
CK00 Clock Synthesizer/Driver Design Guidelines 6.4 Non-production Frequencies for System Debug Some system debug applications exist where CPU frequencies that are above and below the specified 100, 133 MHz are of interest for this device. The ability to use this device in a lab environment using a 10 or 20 MHz crystal is desired.
CK00 Clock Synthesizer/Driver Design Guidelines 6.6 Package Data C H E L D K A e B A1 56 SSOP: Table of Dimensions (inches, unless otherwise specified) Body 56 (300mil) Min Max E 0.291 0.299 H 0.395 0.420 C 0.009 0.013 L 0.020 0.040 φ 0° 8° Symbol D 0.720 0.730 K - A 0.095 0.110 A1 0.008 0.016 e 0.025 48 SSOP: Table of Dimensions (inches, unless otherwise specified) Body 48 (300mil) Min Max E 0.291 0.299 H 0.395 0.420 C 0.009 0.013 L 0.020 0.040 Symbol D φ 0.620 0° 8° 0.
CK00 Clock Synthesizer/Driver Design Guidelines 6.7 Defined option for PCI_bankSTOP# functionality For the SKS and RGR clock devices, an option should be included such that the Spread# pin would be replaced by a PCI_bankSTOP# pin which will shut off (hold LOW) the top five PCI clocks (pins 8,9,11,12,14 for the SKS and pins 6,7,9,10,12 for the RGR). The PCI_bankSTOP# pin should be active LOW. In a system where PCI_bankSTOP# is implemented, spread spectrum will be defaulted to ON. 6.
CK00 Clock Synthesizer/Driver Design Guidelines transferred. Indexed bytes are not allowed. However, the Intel controller has a more specific format than the generic I2C protocol. The clock driver must meet this protocol which is more rigorous than previously stated I2C protocol. Treat the description from the viewpoint of controller.
CK00 Clock Synthesizer/Driver Design Guidelines A transfer is considered valid after the acknowledge bit corresponding to the byte count is read by the controller. The serial controller interface can be simplified by discarding the information in both the command code and the byte count bytes and simply reading all the bytes that are sent to the clock driver after being addressed by the controller. It is expected that the controller will not provide more bytes than the clock driver can handle.
CK00 Clock Synthesizer/Driver Design Guidelines 6.9 I2C Byte Locations for CKFF At power up all CKFF outputs should be enabled and active. The Sdata and Sclock inputs should both have internal pull-up resistors with values above 100K Ohms for complete platform flexibility. CKFF Serial Configuration Map A) The serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 .
CK00 Clock Synthesizer/Driver Design Guidelines Byte 0 : CKFF Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name PCI0 PCI1 PCI2 PCI3 PCI4 PCI5 PCI6 PCI7 Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Notes: 1. Inactive means outputs are held LOW and are disabled from switching.
CK00 Clock Synthesizer/Driver Design Guidelines Notes: 3. Inactive means outputs are held LOW and are disabled from switching.
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