R Intel® Pentium® 4 Processor in the 478-pin Package / Intel® 850 Chipset Family Platform Design Guide January 2003 Document Number: 249888-008
Introduction R INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
Introduction R Contents Introduction........................................................................................................................ 17 1 1.1 1.2 1.3 1.4 1.5 2 Related Documentation ........................................................................................ 18 Conventions and Terminology.............................................................................. 19 System Overview....................................................................................
Introduction R 4.3.3 4.4 5 System Bus Routing.......................................................................................................... 61 5.1 5.2 5.3 5.4 5.5 5.6 6 Return Path........................................................................................................... 62 GTLREF Layout and Routing Recommendations ................................................ 63 Processor Configuration ....................................................................................
Introduction R 6.1.2.3 6.2 7 Differential Clock Compensation ......................................... 96 6.1.2.3.1 Non-Differentially Routed Clocks – 533 MHz Rambus RDRAM* Technology ............................ 97 6.1.2.4 Signal Layer Alternation for Rambus RIMM Connector Pin Compensation ..................................................................... 98 6.1.2.5 Rambus RIMM Connector Impedance Compensation........ 98 6.1.3 RSL Signal Termination ..................................................
Introduction R 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 6 9.1.3 Primary IDE Connector Requirements................................................ 137 9.1.4 Secondary IDE Connector Requirements ........................................... 138 Communication and Networking Riser (CNR).................................................... 139 9.2.1 CNR Placement .................................................................................. 139 ® Intel AC’97 .......................................................
Introduction R 9.9.3.5.2 9.10 9.11 9.12 9.13 9.14 9.15 9.16 ® Distance from Intel 82562EH to Magnetics Module ............................................................... 174 9.9.3.5.3 Distance from LPF to Phone RJ11 .................... 175 ® 9.9.4 Intel 82562ET / 82562EM Guidelines................................................ 175 ® 9.9.4.1 Guidelines for Intel 82562ET / 82562EM Component Placement.......................................................................... 175 9.9.4.
Introduction R 12 Power Distribution Guidelines ......................................................................................... 229 12.1 12.2 12.3 12.4 12.5 12.6 12.7 Definitions ........................................................................................................... 229 Power Management ........................................................................................... 229 12.2.1 ACPI Hardware Model ...................................................................
Introduction R 16.2 16.3 16.4 16.5 16.6 16.7 16.8 16.9 16.10 16.11 16.12 16.13 CK00 Routing Guidelines ................................................................................... 274 16.2.1 CK00 Clocking .................................................................................... 274 RAMBUS Technology Routing Guidelines ......................................................... 276 16.3.1 RSL Signals ........................................................................................
Introduction R Figures Figure 1.Typical System Configuration ............................................................................. 23 Figure 2. Processor Socket Quadrant Layout ................................................................... 29 ® Figure 3. Intel 850/850E Chipset Quadrant Layout ......................................................... 30 ® Figure 4. Intel ICH2 Quadrant Layout.............................................................................. 30 Figure 5.
Introduction R Figure 49. Voltage Divider Network for Reference Voltage Generation............................ 82 Figure 50. Pull-Down Circuit.............................................................................................. 83 ® Figure 51. Example Intel MCH Decoupling Guidelines for Chipset ................................. 84 Figure 52. Customer Reference Platform System Bus Routing – Top Layer ................... 85 Figure 53, Customer Reference Platform System Bus Routing – Bottom Layer ...
Introduction R Figure 96. Modem Codecs .............................................................................................. 142 Figure 97. Audio and Modem Codecs............................................................................. 142 Figure 98. Audio Codecs................................................................................................. 143 Figure 99. Audio and Audio/Modem Codecs................................................................... 143 Figure 100.
Introduction R Figure 148. Layer 3 Power Delivery Shape (VCC_CPU and VSS) ................................. 207 Figure 149. Layer 4 Power Delivery Shape (VCC_CPU and VSS) ................................. 208 Figure 150. Layer 5 Power Delivery Shape (VSS) .......................................................... 209 Figure 151. Bottom Layer Power Delivery Shape (VCC_CPU)....................................... 210 Figure 152. Alternating VCC_CPU/VSS Capacitor Placement .....................................
Introduction R Tables Table 1. Platform Conventions and Terminology .............................................................. 19 ® Table 2. Intel ICH2 Codec Options.................................................................................. 25 Table 3. Placement Assumptions for the Desktop Configuration (6-Layer Motherboard). 31 Table 4. Placement Assumptions for the Desktop Configuration (4-Layer Motherboard). 32 Table 5. BCLK [1:0] Routing Guidelines............................................
Introduction R Table 49. Three-Phase Decoupling Requirements ......................................................... 202 Table 50. Four-Phase Decoupling Locations .................................................................. 202 Table 51. Three-Phase Decoupling Locations ................................................................ 203 Table 52. Airflow Requirements ...................................................................................... 221 ® ® Table 53.
Introduction R Revision History Rev -001 -002 Description • Initial revision. Date August 2001 • Added ICH2 RTC Section 9.8.8 Power-well Isolation Control January 2002 • Added ICH2 RTC Section 9.8.9 Power Supply PS_ON Considerations • Replaced ICH2 LAN Figure 121 Trace Routing • Added ICH2 LAN Section 9.9.5 82562ET/EM Disable Guidelines • Added ICH2 LAN Section 9.9.6 82562ET/82562EH Dual Footprint Guidelines • Added ICH2 Section 9.10 FWH Guidelines • Updated ICH2 Section 12.6 ICH2 5VREF and Vcc3.
Introduction R 1 Introduction In this document when a reference is made to the processor and/or the Intel® Pentium® 4 processor in the 478-pin package, it is intended that this includes the Intel® Pentium® 4 processor in the 478pin package, and the Intel® Pentium® 4 processor with 512-KB L2 cache on 0.13 micron process. Where a reference is intended to refer to a specific processor, the specific processors will be listed separately.
Introduction R 1.1 Related Documentation Refer to the following documents or models for more information. All Intel issued documentation revision numbers are subject to change, and the latest revision should be used. The specific revision numbers referenced should be used for all documents not released by Intel.
Introduction R 1.2 Conventions and Terminology This section defines conventions and terminology that will be used throughout this document. Table 1. Platform Conventions and Terminology Term Aggressor Definition A network that transmits a coupled signal to another network is the aggressor network. AGTL+ The processor System Bus uses a bus technology called AGTL+, or Assisted Gunning Transceiver Logic.
Introduction R Term GTL+ ISI GTL+ is the bus technology used by the Intel Pentium Pro processor. This is an incident wave switching, open-drain bus with pull-up resistors that provide both the high logic level and termination. It is an enhancement to the GTL (Gunning Transceiver Logic) bus technology. Inter-symbol interference is the effect of a previous signal (or transition) on the interconnect delay.
Introduction R 1.3 System Overview The Pentium 4 processor in the 478-pin package with the Intel 850 chipset family delivers Intel's highest performance desktop platform to date. The processor, chipset, and memory are balanced to provide the best possible performing systems. 1.3.1 Intel® Pentium® 4 Processor in the 478-pin Package This processor has a number of features that significantly increase its performance from previous generation IA-32 processors.
Introduction R 1.3.2.1 Intel® 82850/82850E Memory Controller Hub (MCH) The MCH component provides the processor interface, Direct RDRAM device interface, AGP interface and hub interfaces in an Intel 850 chipset platform.
Introduction R 1.3.3 System Configurations Figure 1 illustrates a typical processor and Intel 850 chipset-based system configuration for professional and high performance desktops using the Pentium 4 processor in the 478-pin package. Figure 1.Typical System Configuration Processor Intel® 850 Chipset Main Memory RDRAM 4x AGP Graphics Controller AGP 2.
Introduction R 1.4 Platform Initiatives 1.4.1 Intel® 850 Chipset 1.4.1.1 Rambus Direct RDRAM* Device Interface The Direct RDRAM device interface provides the necessary memory bandwidth to obtain optimal performance from the processor as well as a high-performance AGP graphics controller. The MCH Direct RDRAM device interface supports 300 MHz, 400 MHz and 533 MHz operation, delivering up to 3.2 GB/s of theoretical memory bandwidth using two Direct Rambus channels operating in lock step.
Introduction R 1.4.2.2 Intel® AC’97 6-Channel Support The Audio Codec ’97 (AC’97) Specification defines a digital link that can be used to attach an audio codec (AC), a modem codec (MC), an audio/modem codec (AMC), or both an AC and an MC. The AC’97 Specification defines the interface between the system logic and the audio or modem codec known as the AC-link.
Introduction R 1.4.2.3 Low Pin Count (LPC) Interface In the platform, the super I/O component uses the Low Pin Count (LPC) interface. The LPC super I/O component requires the same feature set as traditional super I/O components. It should include a keyboard and mouse controller, floppy disk controller and serial and parallel ports. In addition to the standard super I/O features, an integrated game port is recommended because the AC’97 interface does not provide support for a game port.
Introduction R 1.4.3 Platform Manageability The Intel 850 chipset platform integrates several functions designed to manage the system and lower the total cost of ownership (TCO) of the system. These system management functions are designed to report errors, diagnose the system and recover from system lockups without the aid of an external micro-controller.
Introduction R 1.5 PC ’99/’01 Platform Compliance PC ‘99 and PC ’01 are intended to provide guidelines for hardware design that will result in optimal user experience, particularly when the hardware is used with the Windows* family of operating systems. The PC ’99 and PC ’01 design guides include PC ‘99 and PC ’01 requirements and recommendations for basic consumer and office implementations, such as desktop, mobile, and workstation systems, and entertainment PC’s.
Component Quadrant Layout R 2 Component Quadrant Layout The quadrant layouts shown are approximations. The quadrant layout figures do not show the exact component ball count; only general quadrant information is presented and is intended for reference while using this document. Only the exact pin or ball assignment should be used to conduct routing analysis. Refer to the following documents for pin or ball assignment information.
Component Quadrant Layout R 2.2 Intel® 850/850E Chipset Component Quadrant Layout Figure 3 and Figure 4 show the quadrant layouts for the Intel 850 chipset components. ® Figure 3. Intel 850/850E Chipset Quadrant Layout AGP System Bus RAC B MCH OLGA Hub Interface RAC A Pin 1 in this corner ® Figure 4.
Platform Placement and Stack-Up Overview R 3 Platform Placement and Stack-Up Overview In this section, examples of Intel 850 chipset platform component placement and stack-up are described for desktop systems in 6-layer ATX and 4-layer µATX motherboard form factors. 3.1 Platform Component Placement 3.1.1 Six-Layer Motherboard Figure 5 shows general component placement for a Pentium 4 processor in the 478-pin package and Intel 850 chipset-based desktop 6-layer motherboard system.
Platform Placement and Stack-Up Overview R Figure 5. Desktop Component Placement Example (6-Layer Motherboard) 3.1.2 Four-Layer Motherboard Figure 6 shows general component placement for a Pentium 4 processor in the 478-pin package and Intel 850 chipset-based desktop 4-layer motherboard system. The assumptions used for the component placement are described in Table 3 and are consistent with the 4-layer customer reference board (CRB) schematics. Table 4.
Platform Placement and Stack-Up Overview R Figure 6.
Platform Placement and Stack-Up Overview R 3.1.2.1 Four-Layer Motherboard Routing Strategy The routing strategy used on the 4-layer CRB is as follows: • Hub interface routing Route hub interface signals across the middle of the two RIMM connectors on channel A and then across to the ICH2. Breakout hub interface signals on top layer to allow 1.8V core and RAC MCH power to be supplied to the MCH in the hub interface pin field on the bottom layer and power plane.
Platform Placement and Stack-Up Overview R Figure 7 shows the general routing strategy for the 4-layer CRB. Figure 7.
Platform Placement and Stack-Up Overview R 3.2 Motherboard Layer Stack-Up 3.2.1 Six-Layer Motherboard Stack-Up Figure 8 shows a six-layer stack-up for the system. It is for reference only and the actual board stack-up may vary depending upon the following considerations. The separation between layers 2 and 3 should be kept as large as possible. A distance greater than 2x should be kept between signals on layers 2 and signals on layer 3.
Platform Placement and Stack-Up Overview R 3.2.2 Design Considerations • Standard vias should be 14 mil hole with a 26 mil pad. Figure 9. Example Stack-Up for 6-Layer ATX Form Factor 1 oz L2 / L5 Thickness (m ils) Top - Signal (plated 1/2oz C u) 2.1 m ils A L2 - Power (unplated 1oz Cu) 2.1 0.4 4 0.3 1.2 0.2 4.3 0.5 1.2 0.2 6.5 0.5 F 23 0.5 E 6.5 0.5 1.2 0.2 4.3 0.5 1.2 0.2 4 0.3 2.1 0.4 61.6 4.7 C 1.2 m ils D B L3 - Signal (unplated 1oz Cu) 1.2 m ils 6.
Platform Placement and Stack-Up Overview R 3.2.3 Four-Layer Motherboard Stack-Up The following figure shows a 4-layer stack-up. • If possible, signals should be referenced to a VSS plane. ® ® ® Figure 10. 4-Layer Intel Pentium 4 Processor in the 478 Pin Package and Intel 850 Chipset Example Stack-Up for µATX Form Factor Component Side Layer 1 ½ oz cu 4.5 Mil Prepreg Power Plane Layer 2 1 oz cu Total Thickness: 62 mils ~48 Mil Core Gound Layer 3 1 oz cu 4.
Platform Clock Routing Guidelines R 4 Platform Clock Routing Guidelines Intel recommends CK00 compliant clocking for this platform. For more information on CK00 compliance, for the 82850 chipset with 400 MHz processor system bus refer to the CK00 Clock Synthesizer/Driver Design Guidelines.
Platform Clock Routing Guidelines R Figure 11. Clocking Architecture Using the CK00 CK00 100 MHz 100 MHz CPU# CPU CPU BCLK[0] BCLK[1] Debug Port 100 MHz 100 MHz CPU# CPU BCLK[0] BCLK[1] MCH 100 MHz CPU# 100 MHz CPU 66 MHz 66 BCLK[0] BCLK[1] 66IN AGP Connector 66 MHz 66 66 MHz 66 33 MHz PCIF 48 MHz USB 33 MHz 14.318 MHz PCIF CLK ICH2 CLK66 PCICLK CLK48 APICCLK CLK14 PCI Connectors CLK CLK 33 MHz PCI CLK 33 MHz PCI 33 MHz PCI 14.
Platform Clock Routing Guidelines R 4.1 Routing Guidelines for System Bus Clocks The CK00 clock synthesizer provides four sets of 100 MHz differential clock outputs. The 100 MHz differential clocks are driven to the processor and MCH as shown in Figure 12. Figure 12. Processor BCLK Topology RT RS Clock Driver RS CK00 RT Processor No Connect RT RS RS RT MCH RT RS RS RT Debug Port BCLK_Topo NOTE: Connect the CK00 component’s HOST pin to the BCLK0 pins on the processor and MCH.
Platform Clock Routing Guidelines R clock driver’s output parasitics, which would otherwise appear in parallel with the termination resistor Rt. The value of Rt should be selected to match the characteristic impedance of the system board and Rs should be 33 Ω. Figure 13.
Platform Clock Routing Guidelines R EMI constraints Clocks are a significant contributor to EMI and should be treated with care. Following these recommendations can aid in EMI reduction: • Route clocks on inner layers. • On internal signals layers maintain a minimum of 100 mils from the edge of the clock traces to the edge of the system board.
Platform Clock Routing Guidelines R Layout Guideline Value Illustration Notes Clock driver to processor and clock driver to Chipset length matching (LT) 0.600 inches ±0.010 inches (Add to MCH trace length) Figure 12 10 BCLK0 – BCLK1 length matching ±10 mils Figure 12 — Rs Series termination value 33 Ω ±5% Figure 12 — Rt Shunt termination value 49.9 Ω ±1% (for 50 Ω MB impedance) Figure 12 11 NOTES: 1.
Platform Clock Routing Guidelines R Figure 14. Clock Skew as Measured from Agent to Agent Figure 15.
Platform Clock Routing Guidelines R 4.2 BCLK[1:0] Frequency Select 4.2.1 100 MHz Operation – Intel® 82850 Chipset The BCLK[1:0] frequency should be set for 100 MHz operation for the 82850 chipset. This is accomplished with a 470 Ω pull-down on the CK-00 SEL100/133 input. In addition, the platform should be prevented from operating with a processor that requires a BCLK[1:0] frequency other than 100 MHz. The correct frequency select circuitry is show in Figure 16. Figure 16.
Platform Clock Routing Guidelines R 4.2.2 133 MHz Operation – Intel® 82850E Chipset The BCLK[1:0] frequency should be set for 133 MHz operation for the 82850E chipset. This is accomplished with a 1 kΩ pull-up to VCC3_CLK on the CK-00 SEL100/133 input. The correct frequency select circuitry is show in the Figure below. Figure 17.
Platform Clock Routing Guidelines R 4.3 Routing Guidelines for Rambus RDRAM* Device Clocks The CK00 clock synthesizer provides two 3.3 V clock reference outputs [3Vmref and 3Vmref#] for the Direct Rambus* Clock Generator (DRCG* device). Two DRCG devices are required in an 850 chipset dual-Direct RDRAM channel interface. Some clock vendors may also have a DMCG (Direct Multiple Clock Generator) component that combines the function of two DRCG devices into one part.
Platform Clock Routing Guidelines R 4.3.2 Intel® MCH to Rambus DRCG* (Phase Aligning Clocks) The RCLKOUT and HCLKOUT signals from the MCH should be routed to the SYNCLKN and PCLKM signals on the DRCG, respectively, as shown in Figure 19. Note that the VddiPD power pin on the DRCG can be connected directly to 1.8 V near the DRCG if the 1.8 V plane extends near the DRCG. However, if a 1.
Platform Clock Routing Guidelines R 4.3.3.1 Trace Lengths Figure 20 shows the critical RDRAM device clock routing sections, with the routing lengths for each section defined in Table 6. Figure 20. Rambus RDRAM* Device Clock Routing Dimension MCH DRCG TERM A B C D RDRAM_Clk_Routing Table 6.
Platform Clock Routing Guidelines R For 300/400 MHz RDRAM technology: In clock routing sections ‘A’ and ‘D’, it is recommended that the clock signals (CTM/CTM# and CFM/CFM#) be routed differentially. For 533MHz RDRAM technology: See Section 6.1.2.3 for CTM/CTM#, CFM/CFM# differential clock compensation requirements. If the clock signals CTM/CTM# and CFM/CFM# are not routed differentially, then an additional 10pS per inch should be added to CTM/CTM# - MCH to first RIMM connector guideline only.
Platform Clock Routing Guidelines R Figure 22. Non-Differential Clock Routing 10 m ils G ROUND 18 m ils 6 m ils CLOCK 10 m ils 6 m ils GROUND GROUND/POW ER PLANE NonDiff-clk_route NOTE: “CLOCK” stands for the signals CTM, CTM#, CFM and CFM#. Note: The CTM/CTM# and CFM/CFM# clock signals must be ground referenced (with continuous ground island/plane) at all times. 4.3.3.
Platform Clock Routing Guidelines R Figure 23. CFM/CFM# Termination – 300/400 MHz Rambus RDRAM* Technology 28 Ω -2% or 27 Ω - 1% 28 Ω -2% or 27 Ω - 1% R1 R2 C1 0.1 uF CFM_Term Figure 24. CFM/CFM# Termination – 533 MHz Rambus RDRAM* Technology R1 27 Ω - 1% R2 27 Ω - 1% C1 0.
Platform Clock Routing Guidelines R 4.3.4 Rambus DRCG* Impedance Matching Circuit The external DRCG impedance matching circuit is shown in Figure 25. Figure 25. Rambus DRCG* Impedance Matching Network 3.3v To 3.3V DRCG Supply Connection FBead CD2 CD CD2 CBulk CD VDD IR VDDO ZCH VDD P CD RS RP CD RP RS VDD CMID2 CMID CF DRCG RT ZCH RT C CD VDDIPD VDDO CD DRCG_Imp_Match Table 7. Rambus DRCG* Impedance Matching Network Values Component Nominal Value Notes CD 0.
Platform Clock Routing Guidelines R The circuit shown is required to match the impedance of the DRCG to the 28 Ω channel impedance. More detailed information can be found in the Direct Rambus Clock Generator Specification. The previously recommended 15 pF capacitors on CTM/CTM# should be removed. The 4 pF capacitor shown in the figure should not be assembled (“no-stuff”). 4.3.5 Rambus DRCG* Layout Example Figure 26.
Platform Clock Routing Guidelines R 4.4 Routing Guidelines for 66 MHz and 33 MHz Clocks 4.4.1 66 MHz / 33 MHz Clock Relationships Figure 27 below shows the clock routing relationships between the 66 MHz clocks and the 33 MHz clocks. The routing guidelines and the topologies for these clocks are also documented. Figure 27. 66 MHz / 33 MHz Clock Relationships Z AGP_66 to AGP Slot Z+ CLK_66 to ICH2, M CH 4.0" - 5.0" 2.0" - 4.0" Z+ PCI_33 to PCI Slots Z+ CLK_33 to ICH2, FW H, SIO 4.0" - 6.
Platform Clock Routing Guidelines R 4.4.2 66 MHz Clock Routing Length Guidelines Table 8. 66 MHz Clock Routing Length Guidelines Clock Group Length of Trace A (in) Length of Trace B (in) R1 (Ω) AGP_66 0” to 0.5” Z 33 CLK_66 0” to 0.5” Z + (4” – 5”) 33 NOTE: The routing length value of Z is 5 to 9 inches. Figure 28 and Figure 29 show the recommended clock routing topologies for the 66 MHz clocks. Figure 28.
Platform Clock Routing Guidelines R 4.4.3 33 MHz Clock Routing Length Guidelines Table 9 summarizes the layout recommendations between the CK00 clock synthesizer and PCI connectors, ICH2, FWH and SIO components that require a 33 MHz clock. Table 9. 33 MHz Clock Routing Guidelines Clock Group Length of Trace A (inches) Length of Trace B (inches) R1 (Ω) PCI_33 0 to 0.5 Z + (2 – 4) 33 CLK_33 0 to 0.5 Z + (4 – 6) 33 NOTE: The routing length value of Z is 5 to 9 inches.
Platform Clock Routing Guidelines R Figure 31.
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System Bus Routing R 5 System Bus Routing Table 10 summarizes the layout recommendations the processor configurations and expands on specific design issues and their recommendations. Table 10. System Bus Routing Summary for the Processor Parameter Processor Routing Guidelines Line to line spacing Data groups, address groups and control signals should be routed with 7 mil traces and 13 mil spacing between traces.
System Bus Routing R Parameter Common Clock line lengths Topology Routing priorities Processor Routing Guidelines 6 – 10 inches pin to pin No length compensation is necessary. Point to point (chipset to processor). All signals should be referenced to VSS. Ideally, layer changes should not occur for any signals. If a layer change must occur, reference plane must be VSS and the layers must all be of the same configuration (all stripline or all microstrip for example). Refer to Section 5.
System Bus Routing R 5.2 GTLREF Layout and Routing Recommendations There are four AGTL+ GTLREF pins on the processor that are used to set the reference voltage level for the AGTL+ signals (GTLREF). Because all of these pins are connected inside the processor package, the GTLREF voltage only needs to be supplied to one of the four pins. The other three pins can be left unconnected. Figure 32. GTLREF Routing VCC_CPU 49.9 Ω 1%, L1 = 1.
System Bus Routing R 5.3 Processor Configuration Both recommendations and considerations are described in this section. For proper operation of the processor and the Intel 850 chipset, it is necessary that the system designer meet the timing and voltage specifications of each component. The following recommendations are Intel’s best guidelines based on extensive simulation and experimentation that make assumptions that may be different than an OEM's system design.
System Bus Routing R 5.3.1.1 Design Recommendations Below are the design recommendations for the data, address, strobes, and common clock signals. For the following discussion, the pad is defined as the attach point of the silicon pad to the package substrate. Data The pin to pin distance from the processor to the chipset should be between 2.0 to 10 inches (i.e., 2.0 inches < L1 < 10 inches).
System Bus Routing R Common Clock Common clock signals should be routed to a minimum pin to pin motherboard length of 6 inches and a maximum motherboard length of 10 inches. Figure 33. Processor Topology Length L1 Processor 850 MCH Pad Pad Package trace Motherboard PCB trace 5.3.1.2 Design Considerations Intel has found that the following recommendations aid in the routing of the processor, given the example stack-up shown in Figure 9. • Line width is 7.0 mil. • Trace to trace spacing is 13.
System Bus Routing R Net Name Intel® Pentium® 4 Processor in 478-pin Package Length (inches) Intel® Pentium® 4 Processor with 512-KB L2 Cache on 0.13 Micron Process Package Length (inches) A#[15] 0.230 0.253 A#[16] 0.192 0.204 REQ#[0] 0.407 0.448 REQ#[1] 0.181 0.232 REQ#[2] 0.246 0.294 REQ#[3] 0.317 0.357 REQ#[4] 0.352 0.360 ADSTB#[1] 0.208 0.220 A#[17] 0.463 0.477 A#[18] 0.409 0.399 A#[19] 0.290 0.316 A#[20] 0.235 0.257 A#[21] 0.335 0.333 A#[22] 0.382 0.
System Bus Routing R Net Name Intel® Pentium® 4 Processor in 478-pin Package Length (inches) Intel® Pentium® 4 Processor with 512-KB L2 Cache on 0.13 Micron Process Package Length (inches) D#[07] 0.433 0.495 D#[08] 0.493 0.537 D#[09] 0.568 0.612 D#[10] 0.249 0.298 D#[11] 0.174 0.232 D#[12] 0.562 0.616 D#[13] 0.439 0.485 D#[14] 0.157 0.209 D#[15] 0.527 0.572 DBI#[0] 0.286 0.332 DSTBN#[1] 0.290 0.312 DSTBP#[1] 0.298 0.313 D#[16] 0.263 0.281 D#[17] 0.479 0.
System Bus Routing R Net Name Intel® Pentium® 4 Processor in 478-pin Package Length (inches) Intel® Pentium® 4 Processor with 512-KB L2 Cache on 0.13 Micron Process Package Length (inches) D#[33] 0.224 0.227 D#[34] 0.177 0.180 D#[35] 0.380 0.361 D#[36] 0.270 0.273 D#[37] 0.460 0.448 D#[38] 0.443 0.431 D#[39] 0.380 0.386 D#[40] 0.169 0.162 D#[41] 0.352 0.333 D#[42] 0.388 0.373 D#[43] 0.338 0.321 D#[44] 0.428 0.412 D#[45] 0.381 0.379 D#[46] 0.222 0.219 D#[47] 0.
System Bus Routing R Net Name Intel® Pentium® 4 Processor in 478-pin Package Length (inches) Intel® Pentium® 4 Processor with 512-KB L2 Cache on 0.13 Micron Process Package Length (inches) DBI#[3] 0.203 0.201 BCLK[0] 0.540 0.596 BCLK[1] 0.539 0.
System Bus Routing R 5.4 Routing Guidelines for Asynchronous GTL+ and Other Signals This section describes layout recommendations for signals other than data, strobe and address. Table 13 lists the signals covered in this section. 1,3 Table 13.
System Bus Routing R 5.4.1 Topologies The following sections describe the topologies and layout recommendations for the miscellaneous signals. 5.4.1.1 Topology 1: Asynchronous GTL+ Signals Driven by the Processor These signals (FERR#, PROCHOT# and THERMTRIP#) should adhere to the following routing and layout recommendations. Figure 34 and Figure 35 illustrate the recommended topologies.
System Bus Routing R Table 15. Layout Recommendations for PROCHOT# and THERMTRIP# Signals (Topology 1b) Trace Zo Trace Spacing L1 L2 L3 Rpu 60 Ω 7 mil 1–17” 10” max 3” max 62 Ω ±5% Figure 35. Routing Illustration for PROCHOT# and THERMTRIP# (Topology 1B) L2 Voltage Translator Processor VDD CPU External Logic RPU L1 L3 Topo1b_PROCHOT_Route 5.4.1.
System Bus Routing R 5.4.1.3 Topology 2A: INIT# Table 17. Layout Recommendations for INIT# (Topology 2A) Trace Zo Trace Spacing L1 L2 L3 L4 L5 Rpu 60 Ω 7 mil 2” max 10” max 3” max 17” max 3” max 300 Ω 5% Figure 37. Routing Illustration for INIT# VCC_FWH VCC_CPU 300 Ω ±5% Processor RPU ICH2 L2 L3 L4 L1 Voltage Translator L5 FWH Topo2a_Route Level shifting is required for the INIT# signal to the FWH in order to meet the input logic levels of the FWH.
System Bus Routing R 5.4.1.4 Topology 2B: Asynchronous GTL+ Signals Driven by Intel® ICH2 This signal (Open Drain; PWRGOOD) should adhere to the following routing and layout recommendations. Figure 39 illustrates the recommended topology. Table 18. Layout Recommendations for Miscellaneous Signals (Topology 2B) Trace Zo Trace Spacing L1 7 mil 60 Ω L3 1–12" Rpu 3" max 300 Ω ±5% Figure 39. Routing Illustration for PWRGOOD VCC_CPU Processor ICH2 RPU L3 L1 Topo2b_pwrgd_Route 5.4.1.
System Bus Routing R 5.4.1.6 Topology 4: BR0# and RESET# Since the processor does not have on-die termination on the BR0# and RESET# signals, it is necessary to terminate using discrete components on the system board. Connect the signals between the components as shown in Figure 41. The Intel 850 chipset has on-die termination and thus it is necessary to terminate only at the processor end. The value of Rt should be 51 Ω ±5% for RESET#. The value of Rt should be 150–220 Ω ±5% for BR0#. Figure 41.
System Bus Routing R 5.4.1.10 Topology 7: THERMDA/THERMDC Routing Guidelines The processor incorporates an on-die thermal diode. THERMDA (diode anode) and THERMDC (diode cathode) pins on the processor can be connected to a thermal sensor located on the system board to monitor the die temperature of the processor for thermal management/long term die temperature change monitoring purpose.
System Bus Routing R 5.4.1.12 Topology 9: Processor Voltage Regulator Sequencing Requirements The Pentium 4 processor with 512KB L2 cache on .13 micron process requires a 1.2 V supply to the VCCVID pin to support the on-die VID generation circuitry. The current requirements for this voltage is 30 mA. A linear regulator is recommended to generate this voltage. The on-die VID generation circuitry also has some power sequencing requirements.
System Bus Routing R Figure 42. Passing Monotonic Rising Edge Voltage Waveform Figure 43.
System Bus Routing R 5.4.1.14 Topology 10: THERMTRIP# Power Down Circuit It is required that power is removed from the processor core within 0.5 seconds of the assertion of the THERMTRIP# signal. Below is an example circuit that will power down the processor voltage regulator when THERMTRIP# is asserted. Figure 44. THERMTRIP# Power Down Circuit 12V 5V 3.3k 10 3V STANDBY 1k 10k 0.
System Bus Routing R Figure 46: Power-on Sequence Timing Diagram Power Up Sequence VCCVID Ta Tb VID_GOOD VID[4:0] BCLK VCC_CPU PWRGOOD Tc Td RESET# Ta= 1ms minimum (VCCVID > 1V to VID_GOOD high) Tb= 50ms maximum (VID_GOOD to Vcc valid maximum time) Tc= T37 (PWRGOOD inactive pulse width) = 10 BCLKs min Td= T36 (PWRGOOD to RESET# de-assertion time) = 1ms(min), 10ms(max) Note: VID_GOOD is not a processor signal. This signal is routed to the output enable pin of the voltage regluator control silicon.
System Bus Routing R Figure 48. THERMTRIP# Power Down Sequence THERMTRIP# Power Down Sequence T1 THERMTRIP# VID_GOOD VCC_CPU PWRGOOD T1 < 0.5 seconds Note: VID_GOOD is not a processor signal. This signal is routed to the output enable pin of the voltage regluator control silicon. THERMTRIP_PWR-Down_Sequence 5.5 Intel® MCH System Bus Interface A voltage divider network should supply host interface reference voltages locally as shown in Figure 49, Figure 50 and as specified by Table 20. Figure 49.
System Bus Routing R Figure 50. Pull-Down Circuit R1 VSS Table 20. Reference Voltage Network Values Signal R1 R2 Tolerance Figure Notes HDVREF[3:0] 100 Ω 50 Ω ±1% Figure 49 1,2 HAVREF[1:0] 100 Ω 50 Ω ±1% Figure 49 1,2 CCVREF 100 Ω 50 Ω ±1% Figure 49 1,2 HRCOMP[1:0] 25 Ω — ±1% Figure 50 3 HSWNG[1:0] 50 Ω 100 Ω ±1% Figure 49 4 NOTES: 1. 2/3 VTT Resistor Network 2. Single voltage divider for these signals. 3. Independent of board impedance. 4. 1/3 VTT Resistor Network 5.
System Bus Routing R ® Figure 51. Example Intel MCH Decoupling Guidelines for Chipset Address and Control Field 2-3 0.1 uF with 603 body over the address and control signals and as close to the chipset package as possible 4-5 0.
System Bus Routing R 5.6 System Bus Routing Guidelines - Four-Layer Motherboard The following are descriptions and illustrations of system bus routing on the 4-layer customer reference board. Figure 52.
System Bus Routing R Figure 53, Customer Reference Platform System Bus Routing – Bottom Layer Bottom Layer Data Addr Roughly half of the signals are routed on the bottom of the board referenced to GND, and the other half of the signals are routed on the top of the board referenced to VCCP. The signals are routed from the MCH to both sides of the processor socket. No signals are routed through the center of the socket.
System Bus Routing R 5.6.1 Processor Power Delivery Power must be distributed as a plane. This plane can be constructed as an island on a layer used for other signals, on a supply plane with other power islands, or as a dedicated layer of the PCB. Processor power should never be distributed by traces alone. Intel recommends that a minimum of four planes be dedicated to power delivery in the power delivery area for Intel Pentium 4 processor system boards.
System Bus Routing R Figure 55.
Memory Interface Routing R 6 Memory Interface Routing The Direct Rambus channel is a multi-symbol interconnect. Due to the length of the interconnect and frequency of operation, this bus is designed to allow multiple command and data packets to be present on a signal wire at any given instant. For example, the driving device can send the next data out before the previous data has left the bus. The nature of the multi-symbol interconnect forces many requirements on the bus design and topology.
Memory Interface Routing R 6.1 Rambus RDRAM* Device Routing Guidelines The MCH has two Direct Rambus channels. The layout guidelines presented below are applicable for each channel. One channel should be routed entirely microstrip (outer layers) or stripline (inner layers). Figure 56 illustrates an example routing topology for the MCH. ® Figure 56.
Memory Interface Routing R Table 21. Direct Rambus Channel Signal Groups Group Signal RSL Signals DQA[8:0] DQB[8:0] RQ[7:0] CMOS Signals CMD(1) SCK*(1) SIO Clocking Signals CTM CTM# CFM CFM# NOTES: 1. These are high-speed CMOS signals 6.1.1 Rambus Signaling Level (RSL) Signals The Direct Rambus channel RSL signals are high-speed signals that transmit data between the MCH and RDRAM component at speeds up to 1066 MHz.
Memory Interface Routing R The following figure and table document the Direct Rambus channel topology for a 28 Ω channel. Figure 57. Example Direct Rambus Channel Routing MCH Term A B C RIMM to RIMM MCH to st 1 RIMM RIMM to Termination NOTE: This diagram only illustrates the routing of one Direct Rambus channel. However, the example routing shown can be applied to both channels. Table 22.
Memory Interface Routing R To ensure a solid memory subsystem design, the RSL signals routing rules need to be followed. Below is a break down of the key areas to watch when design your platform. • To control crosstalk and odd/even mode velocity deltas, there must be a 10 mil ground isolation trace between adjacent RSL signals (see Figure 58). The 10 mil ground isolation traces must be connected to ground with vias distributed less than every 1 inch. A via must be placed within less than 0.
Memory Interface Routing R 6.1.2 Rambus* Signaling Level (RSL) Channel Compensation The RSL and clocking signals require special compensation for any discontinuities introduced in the channel. Since the Direct Rambus channel only allows for 125ps of interconnect skew, it is critical to minimize skew and to match the skew on RSL and clocking signals within a given channel.
Memory Interface Routing R Listed below are a few definitions. • Package Dimension (∆ ∆LPKG): a representation of the length from the pad to the ball. • Board Trace Length (LMB): the trace length on the board. • Nominal Length: the length to which all signals are matched. As Figure 59 shows, L1 plus L3 must be length matched to L2 plus L4 within ±10 mils. Equation 2.
Memory Interface Routing R Figure 60. "Dummy" vs. "Real" Vias “DUMMY Via” “REAL Via” Trace Trace PCB PCB PCB Via PCB Via dum_vias_vs_real 6.1.2.3 Differential Clock Compensation If the RDRAM device clocks (CTM, CTM#, CFM and CFM#) are routed differential, the clock signals must be longer than the RSL signals due to their increased trace velocity because they are routed as a differential pair.
Memory Interface Routing R Note: This compensation factor is based on the Intel 850 chipset customer reference board (CRB) stackup. The lengthening of the clock signals, to compensate for their trace velocity change, only applies to routing between the MCH and first RIMM connector. The clock signals should be matched in length to the RSL signals between RIMM connectors. Equation 5.
Memory Interface Routing R 6.1.2.4 Signal Layer Alternation for Rambus RIMM Connector Pin Compensation RSL and clocking signals must alternate layers as they are routed through the channel to compensate for signals on bottom layer having to travel a longer distance through the pin connector. This is illustrated in Figure 61.
Memory Interface Routing R The amount of capacitance needed depend on the length the signals have to travel though the RIMM connector pin (i.e., a signal on the bottom layer has to travel though more of the RIMM connector pin than a signal on the top layer). This can be achieved on the motherboard by adding a copper tab to the specified RSL pins at each connector. Table 23.
Memory Interface Routing R The following is an example calculation for a board where εr is 4.2 and thickness of prepreg is 4.5. Note these numbers will vary with differences in prepreg thickness. Table 24. Copper Tab Area Calculation Layer Dielectric Thickness Separation Between Signal Traces & Copper Tab Minimum Ground Flood Air Gap Between Signal & GND Flood Compensating Capacitance in Cplate (pF)1 CTAB Area in sq mils Top 4.5 6 10 6 0.8 ~3460 Inner 1 4.5 6 10 6 0.
Memory Interface Routing R Figure 63. Bottom Layer CTAB with RSL Signal Routed on the Same Layer (Ceff = 1.35 pF) The CTAB can be implemented on the multiple layers to minimize routing and space constrains. Figure 64 issues the use of CTABs on the top and bottom layer for bottom layer RSL and clocking signals routed between RIMM connectors. Figure 64. Bottom Layer CTABs Split Across the Top and Bottom Layer to Achieve an Effect Ceff ~1.
Memory Interface Routing R 6.1.3 RSL Signal Termination All RSL signals must be terminated to 1.8 V (Vterm) using 27 Ω 1% or 28 Ω 2% resistors (300/400 MHz RDRAM technology) or 27 Ω 1% (533 MHz RDRAM technology) at the end of the channel opposite the MCH. Resistor packs are acceptable, however discrete resistors are recommended for increased margin. The RSL and clocking signals from the last RIMM connector to termination should be routed on the top layer.
Memory Interface Routing R Figure 66.
Memory Interface Routing R 6.1.4 Rambus RDRAM* Device Reference Voltage The RDRAM device reference voltage (RAMREF) must be generated as shown in Figure 67 for 300/400 MHz RDRAM technology designs and Figure 68 for 533 MHz RDRAM technology designs. RAMREF should be generated from a typical resistor divider using 2% tolerant resistors. Additionally, RAMREF must be decoupled locally at each RIMM connector, at the resistor divider network, and at the MCH.
Memory Interface Routing R 6.1.5 High-Speed CMOS Routing Due to the synchronous requirements between RSL signals and high-speed CMOS signals, the CMOS signals should be routed as part of the RSL channel. They must be impedance matched and properly terminated (using a different termination scheme than the RSL signals). It is not necessary to perform the length match calculation for high-speed CMOS signals.
Memory Interface Routing R Figure 70. SIO Routing MCH SIN SIO RIMM #1 RIMM #2 N N 3 3 2 2 1 SIN SOUT 1 SOUT 2.
Memory Interface Routing R 6.1.7 Suspend-to-RAM Shunt Transistor When the system enters or exits Suspend-to-RAM, power will be ramping to the MCH (i.e., it will be powering-up or powering-down). When power is ramping, the state of the MCH outputs is not guaranteed. Therefore, the MCH may drive the CMOS signals and issue CMOS commands. The only command RDRAM device would respond to is the power-down exit command.
Memory Interface Routing R Figure 71. Rambus RDRAM* Device CMOS Shunt Transistor 5 mils wide MCH 175 mils 5V R I M M S 175 mils R Control Logic Q SCK 5 mils wide R I M M S MCH 175 mils 175 mils 2N3904 CMD This implementation is applicable for RIMM connectors down solution only and is not needed on the repeater channels. Also, this implementation is not necessary if Suspend-to-RAM is not supported within the system 6.1.
Memory Interface Routing R 6.1.9 533 MHz (PC1066) Rambus RIMM Module Thermal Consideration 533 MHz (PC1066) RIMM modules will generate more heat than 400 MHz (PC800) RIMM modules. System designers should insure proper airflow to prevent overheating of memory or other components in the system environment when using PC1066 RIMM modules.
Memory Interface Routing R 6.2 Rambus Technology Routing Guidelines - FourLayer Motherboard To enable a 4-layer design, the RIMM connectors on channel A are placed horizontal and form a 90 degree angle to the RIMM connectors on channel B. See figure below for placement information. Figure 72.
Memory Interface Routing R The breakout of the RSL signals is also critical because it will impact the 1.8V MCH power delivery. RSL signals around the hub interface need to be routed on the top layer to maximize the 1.8V core and RAC power delivery. Follow the MCH Rambus technology breakout shown in the following figures. ® Figure 73.
Memory Interface Routing R ® Figure 74. Rambus Technology Intel MCH Breakout (Bottom Layer) Bottom Layer Channel B Channel A 6.2.1 Optimized Rambus RDRAM* Device Routing Rules for a Four-Layer Motherboard Design This section documents ONLY the routing guideline changes from the general guidelines outlined in the Intel® Pentium® 4 Processor in the 478 Pin Package / Intel® 850 Chipset Family Platform Design Guide.
AGP Interface Routing R 7 AGP Interface Routing For detailed AGP Interface functionality (protocols, rules and signaling mechanisms, etc.) refer to the AGP Interface Specification, Revision 2.0, which can be obtained from http://www.agpforum.org. This design guide focuses only on specific Intel 850 chipset-based platform recommendations. The latest AGP Interface Specification enhances the functionality of the original AGP Interface Specification, Revision 1.0 by allowing 4x data transfers and 1.
AGP Interface Routing R Strobe signals are not used in the 1x AGP mode. In 2x AGP mode, AD[15:0] and C/BE[1:0]# are associated with AD_STB0, AD[31:16] and C/BE[3:2]# are associated with AD_STB1, and SBA[7:0] is associated with SB_STB. In 4X AGP mode, AD[15:0] and C/BE[1:0]# are associated with AD_STB0 and AD_STB0#, AD[31:16] and C/BE[3:2]# are associated with AD_STB1 and AD_STB1#, and SBA[7:0] is associated with SB_STB and SB_STB#. 7.
AGP Interface Routing R 20 mils (1:4). The strobe pair must be length matched to less than ±0.1 inches (i.e., a strobe and its compliment must be the same length within 0.1 inches). If the board impedance is 15%, the trace spacing increases to 20 mils. See the AGP interfaces trace length summary section for detailed information regarding 15% tolerance signals. Figure 75.
AGP Interface Routing R 7.1.3 AGP Interfaces Trace Length Summary The 2X/4X Timing Domain Signals can be routed with 5 mil spacing when breaking out of the MCH. The routing must widen to the documented requirements within 0.3 inches of the MCH package. When matching trace length for the AGP 4X interface, all traces should be matched from the ball of the MCH to the pin on the AGP connector. It is not necessary to compensate for the length of the AGP signals on the MCH package.
AGP Interface Routing R 7.1.4 I/O Decoupling Guidelines A minimum of six 0.01 µF capacitors are required for I/O decoupling. The designer should evenly distribute placement of decoupling capacitors among the AGP interface signal field and placed as close to the MCH as possible (no further than 0.15 inches from the edge of the MCH package). It is recommended that the designer use a low ESL ceramic capacitor, such as a 0603 body type, X7R dielectric.
AGP Interface Routing R 7.1.5 Signal Power/Ground Referencing Recommendations It is strongly recommended that, at a minimum, the following critical signals be referenced to ground from the MCH to an AGP connector utilizing a minimum number of vias on each net; AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, SB_STB#, G_GTRY#, G_IRDY#, G_GNT# and ST[2:0].
AGP Interface Routing R Figure 77. AGP 2.0 VREF Generation and Distribution for 1.5 V Cards VDDQ 500 pF Vrefgc 1 kΩ 1% Pin A66 AGP Add-in Card 82 Ω 1% 220–330 Ω Vrefcg Pin B66 1 kΩ 1% MCH GREF[1:0] 0.1 uF 82 Ω 1% 500 pF AGP_2V_VREF_Gen 7.1.8 Intel® MCH AGP Interface Buffer Compensation The MCH AGP interface supports resistive buffer compensation (GRCOMP[1:0]). The GRCOMP[1:0] signals must be tied to a 40 Ω ± 2% or 39 Ω ± 1% pull-down resistor to ground.
AGP Interface Routing R The MCH G_PAR signal also needs an external pull-up resistor. This signal must have an external pull-up resistor to ensure that G_PAR remains at a valid logic level during AGP protocol transactions. Table 27.
AGP Interface Routing R 7.1.10 AGP Signal Voltage Tolerance List Table 28 documents 3.3 V tolerant signals and 5 V tolerant signals (Refer to the AGP Specification for more details) on the AGP interface. All other signals, in the VDDQ group, are not 3.3 V tolerant during 1.5 V AGP operation. Table 28. 3.3 V and 5 V Tolerant Signals during 1.5 V Operation 3.3 V Tolerant Signals 5 V Tolerant Signals PME# USB+ INTA# USB- INTB# OVRCNT# PERR# SERR# CLK RST 7.1.11 AGP Connector Only 1.
AGP Interface Routing R The AGP interconnect design requires that the AGP card must be retained to the extent that the card does not back out more than 0.99 mm (0.039 in) within the AGP connector. To accomplish this it is recommended that new cards implement an additional notch feature in the mechanical keying tab to allow an anchor point on the AGP card for interfacing with an AGP RM.
AGP Interface Routing R Figure 79. AGP Left Handed Retention Mechanism Keep-out Information Engineering Change Request number 48 (ECR #48) of the AGP specification details the AGP RM, which is recommended for all AGP cards. These are approved changes to the Accelerated Graphics Port (AGP) Interface Specification, Revision 2.0. Intel intends to incorporate the AGP RM changes into later revisions of the AGP Interface Specification.
AGP Interface Routing R 7.3 AGP Routing Guidelines - Four-Layer Motherboard AGP signals are routed on the bottom of the board reference GND. Signals routed on the top of the board are referenced to VDDQ. Figure 80.
AGP Interface Routing R Figure 81.
AGP Interface Routing R Figure 82.
Hub Interface Routing R 8 Hub Interface Routing 8.1 Hub Interface Routing Guidelines The MCH and ICH2 ballout assignments have been optimized to simplify the hub interface routing between these devices. It is recommended that the hub interface signals be routed directly from the MCH to ICH2 with all signals referenced to VSS. Layer transition should be keep to a minimum. If a layer change is required, use only two vias per net and keep all data signals and associated strobe signal on the same layer.
Hub Interface Routing R 8.2 8-Bit Hub Interface Routing Guidelines This section describes the routing guidelines for the 8-bit hub interface. This hub interface connects the ICH2 to the MCH. This interface supports normal buffer mode. When the buffers are configured for normal mode, the trace impedance must equal 60 Ω ± 15%. Table 30.
Hub Interface Routing R The reference voltage generated by a single HIREF divider should be bypassed to ground at each component with a 0.01µF capacitor located close to the component HUBREF pin. If the reference voltage is generated locally, the bypass capacitor needs to be close to the component HUBREF pin. Example HIREF divider circuits are shown in Figure 84 and Figure 85. Figure 84. 8-Bit Hub Interface with a Shared Reference Divider Circuit (Normal Mode) 1.
Hub Interface Routing R 8.2.4 8-Bit Hub Interface Compensation The hub interface uses a compensation signal to adjust buffer characteristics to the specific board characteristic. The hub interface requires Resistive Compensation (RCOMP). Table 32. 8-Bit Hub Interface RCOMP Resistor Values 8.2.
Hub Interface Routing R 8.3 Hub Interface Routing Guidelines - Four-Layer Motherboard To optimize the MCH 1.8V core and RAC power delivery, the hub interface should be routed on the top layer. The 1.8V power pins within the hub interface pin field should have VIAs to the 1.8V power plane on layer 2 and 4 as well as attach to the high reference decoupling capacitors. See the below graphic for more details. Figure 86. Example Hub Interface Breakout / 1.
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I/O Controller Hub 2 R 9 I/O Controller Hub 2 9.1 This Chapter Provides Information on the Intel® 82801BA I/O Controller Hub 2 (ICH2) IDE Interface This section contains guidelines for connecting and routing the ICH2 IDE interface. The ICH2 has two independent IDE channels. This section provides guidelines for IDE connector cabling and system board design, including component and resistor placement, and signal termination for both IDE channels.
I/O Controller Hub 2 R 9.1.2 Cable Detection for Ultra ATA/66 and Ultra ATA/100 The ICH2 IDE Controller supports PIO, Multi-word (8237 style) DMA, and Ultra DMA modes 0 through 5. The ICH2 needs to determine the type of cable that is present, in order to configure itself for the fastest possible transfer mode that the hardware can support. An 80-conductor IDE cable is required for Ultra ATA/66 and Ultra ATA/100. This cable uses the same 40-pin connector as the old 40-pin IDE cable.
I/O Controller Hub 2 R 9.1.2.1 Combination Host-Side/Device-Side Cable Detection Host side detection (described in the ATA/ATAPI-4 Standard, Section 5.2.11) requires the use of two GPI pins (one for each IDE channel). The proper way to connect the PDIAG#/CBLID# signal of the IDE connector to the host is shown in Figure 87. All IDE devices have a 10 kΩ pull-up resistor to 5 volts on this signal. Not all of the GPI and GPIO pins on the ICH2 are 5-volt tolerant.
I/O Controller Hub 2 R 9.1.2.2 Device-Side Cable Detection For platforms that must implement Device-Side detection only (e.g., NLX platforms), a 0.047 µF capacitor is required on the motherboard as shown in Figure 88. This capacitor should not be populated when implementing the recommended combination Host-Side/Device-Side cable detection mechanism described above. Figure 88.
I/O Controller Hub 2 R 9.1.3 Primary IDE Connector Requirements The 10 kΩ resistor to ground on the PDIAG/CBLID signal is now required on both the Primary and Secondary Connectors. This change is to prevent the GPI pin from floating if a device is not present on either IDE interface. Figure 89. Connection Requirements for Primary IDE Connector PCIRST# * PDD[15:0] PDA[2:0] PDCS[3,1]# PDIOR# PDIOW # PDDACK# 3.3 V 3.3 V 4.7 k Ω 8.
I/O Controller Hub 2 R 9.1.4 Secondary IDE Connector Requirements Figure 90. Connection Requirements for Secondary IDE Connector 22–47 Ω PCIRST#* SDD[15:0] ICH2 3.3 V 3.3 V 4.7 kΩ SIORDY 8.2–10 kΩ IRQ15 PDIAG# / CBLID# GPIOy Secondary IDE Connector SDA[2:0] SDCS1#,SDCS3# SDIOR# SDIOW# SDDREQ SDDACK# CSEL 10 kΩ * Due to ringing, PCIRST# must be buffered. IDE_secondary_conn_require • 22 Ω – 47 Ω series resistors are required on RESET#.
I/O Controller Hub 2 R 9.2 Communication and Networking Riser (CNR) The Communication and Networking Riser (CNR) Specification defines a hardware scalable Original Equipment Manufacturer (OEM) system board riser and interface. This interface supports multi-channel audio, V.90 analog modem, phone-line based networking, and 10/100 Ethernet based networking. The CNR specification defines the interface, which should be configured prior to shipment of the system.
I/O Controller Hub 2 R 9.3 Intel® AC’97 The ICH2 implements an AC’97 2.1 compliant digital controller. Any codec attached to the ICH2 AC-link must be AC’97 2.1 compliant as well. Contact your codec vendor for information on 2.1 compliant products. The AC’97 2.1 specification is on the Intel website: http://developer.intel.com/pc-supp/platform/ac97/index.htm The AC-link is a bi-directional, serial PCM digital stream.
I/O Controller Hub 2 R Figure 93. Audio Codec AC’97 Digital Link ICH2 AC’97 Audio Codec Audio Port AC97_1-audio-codec Figure 94. Modem Codec Modem Port ICH2 AC’97 Digital Link AC’97 Audio / Modem Codec AC97_M_codecs Figure 95.
I/O Controller Hub 2 R Figure 96. Modem Codecs Modem Port AC’97 Modem Codec AC’97 Digital Link ICH2 Modem Port AC’97 Modem Codec AC97_2-M_codecs Figure 97.
I/O Controller Hub 2 R Figure 98. Audio Codecs ICH2 AC’97 Digital Link AC’97 Audio Codec Audio Port AC’97 Audio Codec Audio Port AC97_2-audio-codecs Figure 99. Audio and Audio/Modem Codecs M odem Port AC’97 Audio/ Modem Codec IC H2 AC’97 D igital Link Audio Port AC’97 Audio Codec Audio Port A C97_A_A-M_codec The AC’97 interface can be routed using 5 mil traces with 5 mil space between the traces. Maximum length between ICH2 to CODEC/CNR is 14 inches in a tee topology.
I/O Controller Hub 2 R The ICH2 has weak pull-downs/pull-ups that are only enabled when the AC-Link Shut Off bit in the ICH2 is set. This will keep the link from floating when the AC-link is off, or there are no codecs present. If the Shut-off bit is not set, it implies that there is a codec on the link. Therefore, the codec and ICH2 will drive BITCLK and AC_SDOUT, respectively. However, AC_SDIN0 and AC_SDIN1 may not be driven.
I/O Controller Hub 2 R Figure 100.
I/O Controller Hub 2 R Figure 101. CDC_DN_ENAB# Support Circuitry for Multi-Channel Audio Upgrade Motherboard Prim ary Audio Codec CNR Board SDAT A_IN RESET # Audio Codec From AC '97 Controller RESET # SDAT A_IN AC97_RESET# ID0# Vcc RB 100kohm s To General Purpose Input To AC '97 Digital Controller CDC_DN_ENAB# RA 10kohm s SDATA_IN0 SDATA_IN1 CNR Connector Figure 102 shows the circuitry required on the motherboard to support a two-codec down configuration.
I/O Controller Hub 2 R Figure 103. CDC_DN_ENAB# Support for Two-Codecs on Motherboard / Two-Codecs on CNR Codec A Codec B SDAT A_IN RESET # Motherboard CNR Board SDATA_IN R ESET# Codec C R ESET# From AC '97 Controller AC97_RESET# SD AT A_IN Vcc Codec D To General Purpose Input To AC '97 Digital Controller RB 1kohms CDC_DN_ENAB# R ESET# SD AT A_IN RA 10kohm s SDATA_IN0 SDATA_IN1 CNR Connector Circuit Notes • All CNR designs include resistor RB.
I/O Controller Hub 2 R 9.3.2 Valid Codec Configurations Table 35. Codec Configurations Valid Codec Configurations Invalid Codec Configurations AC(Primary) MC(Primary) + X(any other type of codec) MC(Primary) AMC(Primary) + AMC(Secondary) AMC(Primary) AMC(Primary) + MC(Secondary) AC(Primary) + MC(Secondary) AC(Primary) + AC(Secondary) AC(Primary) + AMC(Secondary) 9.
I/O Controller Hub 2 R Figure 104 illustrates the recommended USB schematic: Figure 104. USB Data Signals 15 ohm < 1" P+ Motherboard Trace 45 ohm 15k Driver 15 ohm < 1" P- Motherboard Trace 45 ohm 15k ICH2 Optional 47 pf USB Connector Driver 90 ohm Optional 47 pf Transmission Line USB Twisted Pair Cable The following are Recommended USB Trace Characteristics. • Impedance ‘Z0’ = 45.4 Ω • Line Delay = 160.2 ps • Capacitance = 3.5 pF • Inductance = 7.3 nH • Res @ 20° C = 53.9 m Ω 9.
I/O Controller Hub 2 R 9.6 SMBus/SMLink Interface The SMBus interface on the ICH2 is the same as that on the ICH2. It uses two signals SMBCLK and SMBDATA to send and receive data from components residing on the bus. These signals are used exclusively by the SMBus Host Controller. The SMBus Host Controller resides inside the ICH2. If the SMBus is used only for the RAMBUS SPD EEPROMs (one on each RIMM connector), both signals should be pulled up with a 4.7 kΩ resistor to 3.3 V.
I/O Controller Hub 2 R Note: Intel does not support external access of the ICH2’s Integrated LAN Controller via the SMLink interface. Also, Intel does not support access of the ICH2’s SMBus Slave Interface by the ICH2’s SMBUS Host Controller. Refer to the Intel® 82801BA I/O Controller Hub 2 (ICH2) and Intel® 82801BAM I/O Controller Hub 2 Mobile (ICH2-M) Datasheet for full functionality descriptions of the SMLink and SMBus interface. 9.6.1 SMBus Architecture and Design Considerations 9.6.1.
I/O Controller Hub 2 R 9.6.1.3 The Unified VCC_ Suspend Architecture In this design all SMBus devices are powered by the VCC_Suspend supply. Consideration must be made to provide enough VCC_Suspend current while in STR. Figure 106. Unified VCC_Suspend Architecture Vsus Vsus ICH2 9.6.1.4 Vsus SM BUS DEVICES SM BUS The Unified VCC_Core Architecture In this design, all SMBUS devices are powered by the VCC_Core supply.
I/O Controller Hub 2 R 9.6.1.5 Mixed Architecture This design allows for SMBus devices to communicate while in STR, yet minimizes VCC_Suspend leakage by keeping non-essential devices on the core supply. This is accomplished by the use of a “bus switch” to isolate the devices powered by the core and suspend supplies. See Figure 108. Figure 108.
I/O Controller Hub 2 R 9.7.1 PCI Routing – Four-Layer Motherboard PCI signals are routed with 5mil trace width and 5mil trace to trace spacing. The PCI signals are routed on the bottom side of the boards and should be referenced to VCC3.3. Minimize the number of PCI signals that cross power splits. Figure 110.
I/O Controller Hub 2 R Figure 111.
I/O Controller Hub 2 R Figure 112.
I/O Controller Hub 2 R 9.8 RTC The ICH2 contains a real time clock (RTC) with 256 bytes of battery backed SRAM. The internal RTC module provides two key functions: keeping date and time and storing system data in its RAM when the system is powered down. This section will present the recommended hookup for the RTC circuit for the ICH2. This circuit is not the same as the circuit used for the PIIX4. 9.8.1 RTC Crystal The ICH2 RTC module requires an external oscillating source of 32.
I/O Controller Hub 2 R 9.8.2 External Capacitors To maintain the RTC accuracy, the external capacitor C1 needs to be 0.047 µF, and the external capacitor values (C2 and C3) should be chosen to provide the manufacturer’s specified load capacitance (Cload) for the crystal when combined with the parasitic capacitance of the trace, socket (if used), and package.
I/O Controller Hub 2 R The battery must be connected to the ICH2 via an isolation schottky diode circuit. The Schottky diode circuit allows the ICH2 RTC-well to be powered by the battery when the system power is not available, but by the system power when it is available. To do this, the diodes are set to be reverse biased when the system power is not available. Figure 114 is an example of a diode circuitry that is used. Figure 114. Diode Circuit to Connect RTC External Battery VCC3_3SBY 1 kΩ VccRTC 1.
I/O Controller Hub 2 R ® Figure 115. RTCRST External Circuit for the Intel ICH2 RTC VCC3_3SBY Diode / battery circuit 1 kΩ Vcc RTC 1.0 µF 8.2 k Ω RTCRST# 2.2 µF RTCRST circuit RTC_RTCRESET_ext_circ 9.8.6 RTC Routing Guidelines • All RTC OSC signals (RTCX1, RTCX2, VBIAS) should all be routed with trace lengths of less than 1 inch, the shorter the better. • Minimize the capacitance between RTCX1 and RTCX2 in the routing (optimal would be a ground line between them).
I/O Controller Hub 2 R 9.8.8 Power-Well Isolation Control The RTC-well inputs (RSMRST#, RTCRST#, INTRUDER#) must be either pulled up to VCCRTC or pulled down to ground while in G3 state. RTCRST# when configured as shown in Figure 116 meets this requirement. RSMRST# should have a weak external pull-down to ground and INTRUDER# should have a weak external pull-up to VCCRTC.
I/O Controller Hub 2 R 9.8.9 Power Supply PS_ON Consideration • If a pulse on SLP_S3# or SLP_S5# is short enough (~ 10–100 ms) such that PS_ON is driven active during the exponential decay of the power rails, a few power supplies may not be designed to handle this short pulse condition. In this case, the power supply will not respond to this event and never power back up. These power supplies would need to be unplugged and re-plugged to bring the system back up.
I/O Controller Hub 2 R ® Figure 117. Intel ICH2 / LAN Connect Section B ICH2 C Magnetics 82562EH/82562ET m odule Dual footprint A Connector Refer to 82562EH/82562ET section D LAN_connect Table 37. LAN Design Guide Section Reference Layout Section ICH2 – LAN Interconnect General Routing Guidelines ® ® Figure 117 Design Guide Section A 9.9.1 ICH2 – LAN Interconnect Guidelines B,C,D 9.9.2 General LAN Routing Guidelines and Considerations 82562EH B 9.9.
I/O Controller Hub 2 R 9.9.1 Intel® ICH2 – LAN Interconnect Guidelines This section contains guidelines to the design of motherboards and riser cards to comply with LAN Connect. It should not be treated as a specification and the system designer must ensure through simulations or other techniques that the system meets the specified timings. Special care must be given to matching the LAN_CLK traces to those of the other signals, as shown below.
I/O Controller Hub 2 R Table 38. Length Requirements for Single Solution Interconnect Component Minimum (inches) Maximum (inches) 82562EH L=4.5 L=10 82562ET L=3.5 L=10 CNR L=3 L=9 Notes Signal Lines LAN_RXD[2:1] and LAN_TXD[2:1] not connected NOTE: Length of trace from connector to LOM should be 0.5 to 3 inches. 9.9.1.3 LOM/CNR Interconnect The following guidelines allow for an all inclusive motherboard solution. This layout combines LOM, dual footprint, and the CNR solutions.
I/O Controller Hub 2 R Additional guidelines for this configuration are as follows: • Stubs due to the resistor pack should not be present on the interface. • The resistor pack value can be 0 Ω or 22 Ω. • LAN on motherboard PLC can be a dual footprint configuration. 9.9.1.4 Signal Routing and Layout LAN Connect signals must be carefully routed on the motherboard to meet the timing and signal quality requirements of this interface specification.
I/O Controller Hub 2 R 9.9.1.7 Line Termination Line termination mechanisms are not specified for the LAN Connect interface. Slew rate controlled output buffers achieve acceptable signal integrity by controlling signal reflection, over/undershoot, and ringback. A 33 Ω series resistor can be installed at the driver side of the interface should the developer have concerns about over/undershoot.
I/O Controller Hub 2 R Figure 121. Trace Routing 45 degrees 45 degrees Trace 9.9.2.1.1 Trace Geometry and Length The key factors in controlling trace EMI radiation are the trace length and the ratio of trace-width to trace-height above the ground plane. To minimize trace inductance, high-speed signals and signal layers that are close to a ground or power plane should be as short and wide as practical. Ideally, this trace width to height above the ground plane ratio is between 1:1 and 3:1.
I/O Controller Hub 2 R 9.9.2.2 Power and Ground Connections Some rules and guidelines to follow for power and ground connections: • All VCC pins should be connected to the same power supply. • All VSS pins should be connected to the same ground plane. • Use one decoupling capacitor per power pin for optimized performance. • Place decoupling as close as possible to power pins. 9.9.2.2.
I/O Controller Hub 2 R Some rules to follow that will help reduce circuit inductance in both backplanes and motherboards. • Route traces over a continuous plane with no interruptions (do not route over a split plane). If there are vacant areas on a ground or power plane, avoid routing signals over the vacant area. This will increase inductance and EMI radiation levels. • Separate noisy digital grounds from analog grounds to reduce coupling. • Noisy digital grounds may effect sensitive DC subsystems.
I/O Controller Hub 2 R 5. 6. 7. 8. Routing the transmit differential traces next to the receive differential traces. The transmit trace that is closest to one of the receive traces will put more crosstalk onto the closest receive trace and can greatly degrade the receiver's BER over long cables. After exiting the PLC, the transmit traces should be kept 0.3 inches or more away from the nearest receive trace.
I/O Controller Hub 2 R 9.9.3 Intel® 82562EH Home/PNA* Guidelines For correct LAN performance, designers must follow the general guidelines outlined in Section 9.9.2. Additional guidelines for implementing an 82562EH Home/PNA* LAN connect component are provided below. 9.9.3.
I/O Controller Hub 2 R 9.9.3.4 Phoneline HPNA Termination The transmit/receive differential signal pair is terminated with a pair of 51.1Ω (1%) resistors. This parallel termination should be placed close to the 82562EH. The center, common point between the 51.1 Ω resistors is connected to a pair of 806 Ω resistors and a single 0.022 µF capacitor. The opposite end of one 806 Ω resistor is tied to VCCA (3.3 V), and the opposite end of the other 806 Ω resistor and the capacitor are connected to ground.
I/O Controller Hub 2 R 9.9.3.5 Critical Dimensions There are three dimensions to consider during layout. Distance ‘B’ from the line RJ11 connector to the magnetics module, distance ‘C’ from the phone RJ11 to the LPF (if implemented), and distance ‘A’ from 82562EH to the magnetics module (See Figure 124). Figure 124. Critical Dimensions for Component Placement B A ICH2 Magnetics m odule 82562EH C Line RJ11 LPF Phone RJ11 EEPRO M LAN_crit_dim_comp_place Table 40. Critical Dimension Values 9.9.3.
I/O Controller Hub 2 R 9.9.3.5.3 Distance from LPF to Phone RJ11 This distance ‘C’ should be less then 1 inch. In regards to trace symmetry, route differential pairs with consistent separation and with exactly the same lengths and physical dimensions. Asymmetrical and unequal length in the differential pairs contribute to common mode noise and this can degrade the receive circuit performance and contribute to radiated emissions from the transmit side 9.9.
I/O Controller Hub 2 R 9.9.4.2 Crystals and Oscillators To minimize the effects of EMI, clock sources should not be placed near I/O ports or board edges. Radiation from these devices may be coupled onto the I/O ports or out of the system chassis. Crystals should also be kept away from the Ethernet magnetics module to prevent interference of communication.
I/O Controller Hub 2 R Figure 126. Critical Dimensions for Component Placement B ICH2 82562ET A Magnetics Module Line RJ45 EEPROM LAN_crit_dim_comp_place2 Table 41. Critical Dimension Values 9.9.4.4.1 Distance Priority Guideline A 1 < 1 inch B 2 < 1 inch Distance from Magnetics Module to RJ45 The distance A in Figure 126 above should be given the highest priority in board layout.
I/O Controller Hub 2 R 9.9.4.4.2 Distance from Intel® 82562ET to Magnetics Module Distance B should also be designed to be less than one inch between devices. The high-speed nature of the signals propagating through these traces requires that the distance between these components be closely observed. In general, any section of traces that is intended for use with high-speed signals should observe proper termination practices.
I/O Controller Hub 2 R 9.9.4.6.1 Termination Plane Capacitance It is recommended that the termination plane capacitance equal a minimum value of 1500 pF. This helps reduce the amount of crosstalk on the differential pairs (TDP/TDN and RDP/RDN) from the unused pairs of the RJ45. Pads may be placed for an additional capacitance to chassis ground, which may be required if the termplane capacitance is not large enough to pass EFT (Electrical Fast Transient) testing.
I/O Controller Hub 2 R 9.9.5 Intel® 82562 ET/EM Disable Guidelines To disable the 82562ET/EM, the device must be isolated (disabled) prior to reset (RSM_PWROK) asserting. Using a GPIO, such as GPO28 to be LAN_Enable (enabled high), LAN will default to enabled on initial power-up and after an AC power loss. This circuit (see Figure 128) will allow this behavior. BIOS by controlling the GPIO can disable the LAN microcontroller. ® Figure 128.
I/O Controller Hub 2 R 9.9.6 82562ET / 82562EH Dual Footprint Guidelines These guidelines characterize the proper layout for a dual footprint solution. This configuration enables the developer to install either the 82562EH or the 82562ET/82562EM components while having only one motherboard design. The following are guidelines for the 82562ET/82562EH Dual Footprint option. The dual footprint for this particular solution uses a SSOP footprint for 82562ET and a TQFP footprint for 82562EH.
I/O Controller Hub 2 R The following are additional guidelines for this configuration: • L = 3 .5 to 4.5 inches • Stub < 0.5 inches • Either 82562EH or 82562ET/82562EM can be installed. Not both • 82562ET pins 28,29, and 30 overlap with 82562EH pins 17,18, and 19. • Overlapping pins are tied to ground. • No other signal pads should overlap or touch. • The 82562EH and 82562ET configurations share signal lines LAN_CLK, LAN_RSTSYNC, LAN_RXD[0], LAN_TXD[0], RDP, RDN, RXP/Ring, and RXN/Tip.
I/O Controller Hub 2 R 9.10 Intel® ICH2 Routing Guidelines – Four-Layer Motherboard ® Figure 131.
I/O Controller Hub 2 R ® Figure 132.
I/O Controller Hub 2 R 9.11 FWH Guidelines 9.11.1 FWH Decoupling A 0.1 µF capacitor should be placed between the VCC supply pins and the VSS ground pins to decouple high frequency noise, which may affect the programmability of the device. Additionally, a 4.7 µF capacitor should be placed between the VCC supply pins and the VSS ground pins to decouple low frequency noise. The capacitors should be placed no further than 390 mils from the VCC supply pins. 9.11.
I/O Controller Hub 2 R 9.12 Intel® ICH2 Decoupling Recommendations The ICH2 is capable of generating large current swings when switching between logic high and logic low. This condition could cause the component voltage rails to drop below specified limits. To avoid this type of situation, ensure that the appropriate amount of bulk capacitance is added in parallel to the voltage input pins.
I/O Controller Hub 2 R 9.14 SPKR Pin Consideration The effective impedance of the speaker and codec circuitry on the SPKR signal line must be greater than 50 kΩ. Failure to due so will cause the TCO Timer Reboot function to be erroneously disabled. SPKR is used as both the output signal to the system speaker and as a functional strap. The strap function enables or disables the “TCO Timer Reboot function” based on the state of the SPKR pin on the rising edge of POWEROK.
I/O Controller Hub 2 R 9.15 1.8 V and 3.3 V Power Sequence Requirement The ICH2 has two pairs of associated 1.8 V and 3.3 V supplies. These supplies are Vcc1_8, Vcc3_3 and VccSus1_8, VccSus3_3. These pairs are assumed to power up and power down together. The difference between the two associated supplies must never be greater than 2.0 V. The 1.8 V supply may come up before the 3.3 V supply without violating this rule (though this is generally not practical in a desktop environment, since the 1.
I/O Controller Hub 2 R 9.16 PIRQ Routing PCI interrupt request signals E-H are new to the ICH2. These signals have been added to lower the latency caused by having multiple devices on one Interrupt line. With these new signals, each PCI slot can have an individual PCI interrupt request line (Assuming that the system has four PCI slots). Table 43 shows how the ICH2 uses the PCI IRQ when the IOAPIC is active. Table 43.
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Additional Design Considerations R 10 Additional Design Considerations This section documents system design considerations not addressed in previous sections. 10.1.1 Retention Mechanism Placement and Keepouts The RM requires a keepout zone for a limited component height area under the RM. Figure 137 and Figure 138 show the relationship between the RM mounting holes and pin one of the socket. In addition they also document the keepouts. A 0.
Additional Design Considerations R Note: Dimensions are in millimeters with English dimensions in brackets. Figure 137.
Additional Design Considerations R Note: Dimensions are in millimeters with English dimensions in brackets. Figure 138.
Additional Design Considerations R ® Figure 139.
Additional Design Considerations R 10.1.2 Power Header for Active Cooling Solutions The Intel reference-design heatsink includes an integrated fan. The recommended connector for the active cooling solution is a Walden*/Molex 22-01-3037, AMP* 643815-3 or equivalent. The integrated fan requires the system board to supply a minimum of 740 mA at 12 V for proper operation. The fan connector pinout is described in Table 44. Table 44.
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Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines R 11 Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines 11.1 Power Requirements Intel recommends using an Intel® Pentium® 4 Processor VR Down Design Guidelines-compliant regulator for the processor system board designs that meets FMB2 requirements (refer to Section 1.6 for airflow requirements).
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines R 11.1.1 FMB1 VR Component Placement Figure 140.
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines R 11.1.2 FMB2 VR Component Placement Figure 141. Four-Phase VR Component Placement Figure 142.
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines R 11.1.3 FMB1 Decoupling Requirements For the processor voltage regulator circuitry to meet the transient specifications of the processor, proper bulk and high frequency decoupling is required. The decoupling requirements for the processor power delivery in this case are shown in Table 46. Table 46.
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines R Figure 143.
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines R 11.1.4 FMB2 Decoupling Requirements In order for the processor voltage regulator circuitry to meet the transient specifications of the processor, proper bulk and high frequency decoupling is required. The decoupling requirements for the processor power delivery in this case are described in Table 48 and Table 49. Table 48.
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines R Table 51.
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines R Figure 145.
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines R 11.1.5 FMB1 Layout (6-Layer Board) All six layers in the processor area should be used for power delivery. Four layers should be used for VCC_CPU and two layers should be used for ground. Traces are not sufficient for supplying power to the processor due to the high current and low resistance required to meet the processor voltage specifications.
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines R Figure 147.
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines R Figure 148.
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines R Figure 149.
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines R Figure 150.
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines R Figure 151. Bottom Layer Power Delivery Shape (VCC_CPU) The high frequency decoupling capacitors should be placed with alternating VCC_CPU and VSS to provide a better path for power delivery through the capacitor field. An example of this placement is shown in Figure 152.
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines R Figure 152.
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines R 11.1.6 FMB2 Four–Phase Layout (4-Layer Board) All four layers in the processor area should be used for power delivery. Two layers should be used for VCC_CPU and two layers should be used for ground. Traces are not sufficient for supplying power to the processor due to the high current and low resistance required to meet the processor voltage specifications.
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines R Figure 154. Layer 2 Power Delivery Shape (VSS) Figure 155.
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines R Figure 156. Bottom Layer Power Delivery Shape (VCC_CPU) 11.1.7 FMB2 – Three-Phase Layout (4-Layer Board) All four layers in the processor area should be used for power delivery. Two layers should be used for VCC_CPU and two layers should be used for ground.
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines R Figure 157. Top Layer Power Delivery Shape (VCC_CPU) Figure 158.
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines R Figure 159. Layer 3 Power Delivery Shape (Vss) Figure 160.
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines R 11.1.8 FMB1 – Common Layout Issues The processor socket has 478 pins with 50-mil pitch. The routing of the signals, power and ground pins will require creation of many vias. These vias cut up the power and ground planes beneath the processor resulting in increased inductance of these planes.
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines R Figure 162.
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines R 11.1.9 FMB2 - Common Layout Issues The processor socket has 478 pins with 50-mil pitch. The routing of the signals, power and ground pins will require creation of many vias. These vias cut up the power and ground planes beneath the processor resulting in increased inductance of these planes.
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines R Figure 164. Routing of VR Feedback Signal 11.2 Thermal Considerations 11.2.1 FMB1 For a power delivery solution to meet the flexible motherboard (FMB) requirements, it must be able to delivery a fairly high amount of current.
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines R Table 52. Airflow Requirements Design Example Minimum Airflow Notes Three-Phase 110 LFM 1 Four-Phase 0 LFM 2 NOTES: 1. Assumes dedicated fan for Voltage Regulator (VR). 2. Assumes expanded layout area as compared to the three-phase VR design. 11.2.
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines R Figure 165. Example Circuit That Can Be Used As a Thermal Monitor Vccp Vcc Vcc R1 1kΩ 1kΩ 130Ω 680Ω + - LM393 R2 499Ω 130Ω PROCHOT# 3904 7.5kΩ 6.8k THMSTR 0.1uF 3. For this circuit implementation, the thermistor (THMSTR) should be placed in the hottest area of the VR. As the thermistor heats up its resistance goes down.
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines R 11.3 Simulation 11.3.1 FMB1 To completely model the system board, one must include the inductance and resistance that exists in the cables, connectors, PCB planes, pins and body of components (such as resistors and capacitors), processor socket, and the voltage regulator module. More detailed models showing these effects are shown in Figure 166. Figure 166.
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines R 11.3.2 FMB2 To completely model the system board, one must include the inductance and resistance that exists in the cables, connectors, PCB planes, pins and body of components (such as resistors and capacitors), processor socket, and the voltage regulator module. More detailed models showing these effects are shown in Figure 167. Figure 167.
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines R 11.4 Filter Specifications For VCCA, VCCIOPLL, and VSSA VCCA and VCCIOPLL are power sources required by the PLL clock generators on the processor silicon. Since these PLLs are analog in nature they require quiet power supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O timings as well as internal core timings (i.e., maximum frequency).
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines R Figure 169. Filter Recommendation 0.2 dB 0 dB 0.5 dB Forbidden Zone Forbidden Zone -28 dB -34 dB DC 1 Hz fpeak 1 MHz passband 66 MHz fcore high frequency band PLL_Filter_Spec NOTES: 1. Diagram not to scale. 2. No specification for frequencies beyond fcore (core frequency). 3. fpeak, if existent, should be less than 0.05 MHz.
Intel® Pentium® 4 Processor in the 478-Pin Package Processor Power Distribution Guidelines R Figure 170.
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Power Distribution Guidelines R 12 Power Distribution Guidelines 12.1 Definitions 12.2 Suspend-To-RAM (STR) In the STR state, the system state is stored in main memory and all unnecessary system logic is turned off. Only main memory and logic required to wake the system remain powered. Full-power operation: During full-power operation, all components on the motherboard remain powered. Note that full-power operation includes both the fullon operating state and the S1 (CPU stop-grant state) state.
Power Distribution Guidelines R 12.2.1 ACPI Hardware Model The Intel 850 chipset-based desktop supports both legacy and ACPI operations, which involves sequencing the platform between the various global system states (G0–G3). Figure 171 depicts global states and the transitions. For complete detail of the mechanisms involved in transition from any of the global states refer to the ACPI Interface Specification 1.0a, Section 4.5. Figure 171.
Power Distribution Guidelines R ® ® Table 55. Intel 850 Chipset and Intel ICH2 Thermal Design Power Parameter Icc Max Sustainable Current (A) S0) MCH • MCH (UP) Typical Thermal Design Power = 5.8 W • MCH (UP) Maximum Thermal Design Power = 8.0 W 1.8 V Core 3.2 1.5 V VDDQ AGP I/O 0.37 1.6 V VTT 2.2 ICH2 • Max Thermal Design Power = 1.6 W ±15% 1.8 V Main Logic 0.30 1.8 V (Stand By) Resume Logic + 1.8 V LAN 0.040 3.3 V Main I/O 0.41 3.3 V (Stand By) Resume Logic 0.062 RTC .
Power Distribution Guidelines R Simulations and validations indicate that L = 3.3 nH and C1 = 3.3 µF forms an adequate inductorcapacitor filter. The filter must be located within 2-inches the device and the layout of VccRAC connections should follow high-speed design practices. In addition to the low-pass filter, the RAC requires local decoupling capacitors. These decoupling capacitors should be located close to the RAC pins to control self-induced RAC noise.
Power Distribution Guidelines R Figure 174. Customer Reference Board Layout Example Place L-C or Ferrite Bead filter < 2” from edge of the MCH package Decoupling Caps for 1.8V Rac Power Figure 175.
Power Distribution Guidelines R Figure 176. Customer Reference Board Layout Example (Signal 2 – Layer 4) 12.4 Vterm/Vdd Power Sequencing Requirement Power to the RDRAM device termination resistors (Vterm) must follow the power to the RDRAM device Core. A Schottky diode can be placed between the 1.8 V and 2.5 V to ensure this power-up sequence. Figure 177. 1.8 V and 2.5 V Power Sequence (Schottky Diode) 1.8V 2.
Power Distribution Guidelines R 12.5 Intel® 850 Chipset Power Sequencing Requirements The Intel® 850 chipset needs the following power supplies for operation – VCC1_8, VDDQ and VTT. To avoid forward-biasing the ESD protection-diodes from the IO to Core power supplies, it is necessary that the VCC1_8 power supply ramp up ahead (See Figure 178) of the VDDQ and VTT power supplies. For the same reason, it is necessary to have the VCC1_8 power supply ramp down later than the VDDQ and VTT power supplies.
Power Distribution Guidelines R 12.6 Intel® ICH2 V5REF and Vcc3.3 Sequencing Requirement V5REF is the reference voltage for 5 V tolerance on inputs to the ICH2. V5REF must be powered up before Vcc3_3, or after Vcc3_3 within .7 V. Also, V5REF must power down after Vcc3_3, or before Vcc3_3 within 0.7 V. The rule must be followed in order to ensure the safety of the ICH2. If the rule is violated, internal diodes will attempt to draw power sufficient to damage the diodes from the Vcc3_3 rail.
Power Distribution Guidelines R 12.7 CPU / CK00 Power Sequencing Requirement To ensure that the correct processor system bus frequency is set, the CPU BSELx pins must be at an operating state before the CK00 clock chip powers up. An example circuit is shown below. Figure 181. CPU/CK00 Sequencing Circuit VCC3_CLK 47K 5% CLK_PWRDWN CK00 Clock Chip / DRCG MBT3904 DUAL VCCP 4.
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Debug Port Routing Guidelines R 13 Debug Port Routing Guidelines In Pentium 4 processor in the 478-pin package based systems, the debug port should be implemented as an on-board debug port. Refer to the latest revision of the Pentium® 4 Processor in the 478-pin Package Debug Port Design Guide for details on the implementation of the debug port.
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Debug Tools Specifications R 14 Debug Tools Specifications 14.1 Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging the Pentium 4 processor in the 478-pin package systems. Tektronix* and Agilent* should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature. Specific information must be obtained from the logic analyzer vendor.
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Schematic Review Checklist R 15 Schematic Review Checklist 15.1 Processor Checklist (All Signals) All signals of the processor are provided in this section. Checklist Items A[35:3]# Recommendations • Connect A[31:3]# to MCH. Leave A[35:32]# as No Connect. Reason/Impact/Documentation • Chipset does not support extended addressing over 4 GB, leave A[35:32]# unconnected. • AGTL+ source synch I/O signal A20M# • Connect to ICH2. No pull-up required. • Asynch GTL+ Input Signal • Refer to Section 5.4.1.2.
Schematic Review Checklist R Checklist Items Recommendations Reason/Impact/Documentation • Terminate to VCC_CPU with a 51Ω 5% resistor near the processor. Connect to the MCH. BR0# • The Intel 850 chipset contains on-die termination for the BR0# signal. The processor does not contain on-die termination for this particular AGTL+ signal; thus, external termination is required only on the processor end. BR0# termination should equal the resistance value of on die AGTL+ termination resistance (Rtt) value.
Schematic Review Checklist R Checklist Items IERR# Recommendations • Leave as a No Connect Reason/Impact/Documentation • Chipset does not support this signal. • Asynch GTL+ output signal. IGNNE# • Connect to ICH2. • Termination not required. • No pull-up required. • Asynch GTL+ input signal. • Refer to Section 5.4.1.2. INIT# • Connect to ICH2 and Firmware Hub (FWH). • Voltage translation is required for this signal to meet the input threshold levels of the FWH. LINT[1:0] • Connect to ICH2.
Schematic Review Checklist R Checklist Items Recommendations SMI# STPCLK# Reason/Impact/Documentation • Connect to ICH2. • Asynch GTL+ input signal • No pull-up required. • Refer to Section 5.4.1.2. • Connect to ICH2. • Asynch GTL+ input signal • No pull-up required. • Refer to Section 5.4.1.2. Refer to Section 5.4.1.11 for more information. TESTHI • Tying any of the TESTHI pins together will prevent the ability to perform boundary scan testing. • Refer to processor datasheet.
Schematic Review Checklist R Checklist Items ® ® Recommendations Reason/Impact/Documentation TRST# • Debug port signal. Refer to the latest revision of the Intel® Pentium® 4 Processor in the 478-pin Package Debug Port Design Guide for information on the connection and termination of this signal. • Debug port signal. Proper termination is required for the system to function properly. TCK • Debug port signal.
Schematic Review Checklist R 15.2 CK00 Clock Generator Checklist Checklist Items Recommendations Reason/Impact/Documentation • Use 33 Ω series termination resistor for each signal. Ref/MultSel[0:1] • Connect to ICH2 and SIO. • Use 33 Ω series termination resistor for each signal. PCICLK [0:9] • Refer to Section 4.4.2.1. • Connect to PCI slots 0 through 4 • Connect to ICH2, FWH, SIO, Glue Chip and Audio Logic Device. • Use 33 Ω series termination resistor for each signal.
Schematic Review Checklist R Checklist Items Recommendations • Connect a 10 pF capacitor from each signal to GND. XTAL_in XTAL_out 15.3 Reason/Impact/Documentation • Capacitor values may vary slightly from manufacturer to manufacturer. • Connect to 14.318 MHz crystal oscillator. Direct Rambus Clock Generator (DRCG1 and DRCG2) Checklist Checklist Items Recommendations • Connect to 3.
Schematic Review Checklist R Checklist Items Recommendations • Connect to GPIO. Mult[1:0] Reason/Impact • These pins determine the internal PLL divider ratio in the DRCG. Connection to GPIO allows software adjustable PLLCLK and REFCLK multipliers. • The Intel 82850 chipset platform supports 400 MHz (PC800) and 300 MHz (PC600) RAMBUS operation only. • The Intel 82850E chipset platform supports 400 MHz (PC800) or 533 MHz (PC1066) RAMBUS operation only. • Connect a 39 Ω ±5% series resistor near the pins.
Schematic Review Checklist R 15.4 Intel® 850 Chipset Checklist Checklist Items Recommendations • Connect to ICH2 HL_STB HL_STB# Reason/Impact • The length of both hub interface strobe signals must be matched within ±0.1 inches of the HL_STB differential pair. • Refer to Section 8.2.1. • Connect voltage divider to pins. 50 Ω ±1% pull-up to VCC and 100 Ω ±1% pull-down resistor to GND. HDVREF[3:0] HAVREF[3:0] CCVREF • Decouple the voltage divider with a 1 µf capacitor.
Schematic Review Checklist R Checklist Items I/O Decoupling requirements Recommendations Reason/Impact • 4 minimum, 5 preferred 0.1 µf capacitors with 603 packages distributed evenly over the System Bus data lines. • This is to provide clean power delivery to the system bus I/O ring. • Refer to Section 5.5.1. • 2 minimum, 3 preferred 0.1 µf capacitors with 603 packages distributed evenly over the system bus address and control lines.
Schematic Review Checklist R 15.5 AGP Checklist Checklist Items Recommendations Reason/Impact G_FRAME# G_IRDY# G_TRDY# G_DEVSEL# G_STOP# G_SERR# G_PERR# G_RBF# G_PIPE# G_REQ# G_GNT# G_PAR AD_STB[0:1] SB_STB WBF# • These signals require pull-up resistors to VDDQ. • VDDQ = 1.5 V for 1X, 2X and 4X mode • Acceptable values are between 4 kΩ • Pull up to VDDQ ensures that stable values are maintained when agents are not actively driving the bus. AD_STB#[0:1] • These signals require pull-down resistors.
Schematic Review Checklist R Checklist Items Decoupling Capacitors SBA[7:0] 254 ® Recommendations Reason/Impact • Use a 0.01 µF capacitor for each power pin and a bulk 10 µF tantalum capacitor on VDDQ and a 20 µF tantalum capacitor on VCC3_3 plane near the connector. • This is to ensure that the AGP connector is well decoupled. • No extra Pull-up resistors. Connect to AGP connector. • In the MCH, weak pull-ups are integrated for SBA[7:0] signals.
Schematic Review Checklist R 15.6 Rambus RIMM* Connector Checklist Note: • S3 (Suspend To RAM): RDRAM device support Æ 2.5 V (ON), 1.8 V (ON), 3.3 V (N/A) • S5 – 2.5 V (OFF), 1.8 V (OFF), 3.3 V (OFF) Checklist Items Recommendations • 0.8 pF – 1.35 pF compensating capacitance is required on each of these RSL connector pins.
Schematic Review Checklist R Checklist Items Recommendations Reason/Impact • Should be connected to VCC3_3 or GND to set the SMBus address for that RIMM* modules EEPROM. SA Pins • If the SMBus is tied to 3.3VSB, then either: Provide proper isolation on SCL /SDA and pull the HIGH SA pins to 3.3 V • This sets the SMBus address. Each device on the SMBus must have an address to distinguish it from another device of the same type.
Schematic Review Checklist R Checklist Items Recommendations VCMOS decoupling 2.5 V (VDD) decoupling Reason/Impact • PC1066: Minimum of 2 x 0.1 µF capacitors, one near each RIMM input • PC1066 requirement • Low frequency decoupling: • These are EXAMPLES. The exact decoupling requirements are dependent on the voltage regulator design. Refer to the RDRAM device specification for the power delivery requirements. • This needs to be done on the motherboard with bulk capacitors.
Schematic Review Checklist R Checklist Items 1.4 V (RAMREF) decoupling (300/400 MHz RDRAM technology) Recommendations Reason/Impact This plane must be decoupled in the following manner: • Refer to Section 6.1.4. • Each RIMM connector: Locally – A value of 0.1 µF is required for local decoupling. 1.35 V (RAMREF) decoupling (533 MHz RDRAM technology) • RAMREF Generation Circuit: At resistor divider – The RAMREF generation circuitry should be placed near the MCH.
Schematic Review Checklist R 15.7 Intel® ICH2 Checklist 15.7.1 PCI Interface Checklist Items Recommendations Reason/Impact FYI • Inputs to the ICH2 must not be left floating. • Many GPIO signals are fixed inputs that must be pulled up to different sources. See Section 15.7.7 for recommendations PERR# SERR# PLOCK# STOP# DEVSEL# TRDY# IRDY# FRAME# REQ#[0:4] GPIO[0:1] THRM# • These signals require a pull-up resistor. Recommend an 8.2 kΩ pullup resistor to VCC3_3 or a 2.7 kΩ pull-up resistor to VCC5.
Schematic Review Checklist R 15.7.2 Hub Interface Checklist Items 15.7.3 Recommendations HL[11] • No pull-up resistor required • Use a no-stuff or a test point to put the ICH2 into NAND chain mode testing HL_COMP • Tie the COMP pin to a 40 Ω 1% or 2% (or 39 Ω 1%) pull-up resistor (to VCC1_8) via a 10-mil wide, very short (~0.5 inch) trace. • ZCOMP No longer supported. LAN* Interface Checklist Items Recommendations Reason/Impact LAN_CLK • Connect to LAN_CLK on platform LAN connect device.
Schematic Review Checklist R 15.7.5 FWH/LPC Interface Checklist Items Recommendations • No extra pull-ups required. Connect straight to FWH/LPC. FWH[3:0]/ LAD[3:0] LDRQ[1:0] 15.7.6 Reason/Impact • ICH2 integrates 24 kΩ pull-up resistors on these signal lines. Interrupt Interface Checklist Items Recommendations • These signals require a pull-up resistor. Recommend a 2.7 kΩ pullup resistor to VCC5 or 8.2 kΩ to VCC3_3.
Schematic Review Checklist R Checklist Items Recommendations Reason/Impact Pentium 4 processor based systems: APIC • These processors do not have APIC pins so all platforms using this processor should both tie APICCLK to ground and tie APICD[1:0] to ground via a 1 kΩ–10 kΩ pull-down resistor. If the APIC is not used on UP systems: • Use pull downs for each APIC signal. Do not share resistor to pull signals up.
Schematic Review Checklist R 15.7.8 USB Checklist Items Recommendations • See Section 9.4 for circuitry needed on each differential Pair. USBP[3:0]P USBP[3:0]N 15.7.9 Power Management Checklist Items Recommendations • Should not be used for this platform. A pull-up is required on this signal. • Input to ICH2 cannot float. THRM# polarity bit defaults THRM# to active low, so pull up. SLP_S3# • No pull-up/pull-down resistors needed. Signals driven by ICH2.
Schematic Review Checklist R 15.7.11 System Management Checklist Items • Requires external pull-up resistors. See SMBus Architecture and Design Consideration section to determine the appropriate power well to use to tie the pull-up resistors. (Core well, suspend well, or a combination.) SMBDATA SMBCLK 15.7.12 Recommendations • Value of pull-ups resistors determined by line load. Typical value used is 8.2 kΩ.
Schematic Review Checklist R 15.7.13 Intel® AC’97 Checklist Items Recommendations Reason/Impact AC_SDOUT • Requires a jumper to 8.2 kΩ pull-up resistor. Should not be stuffed for default operation. • This pin has a weak internal pulldown. To properly detect a safe_mode condition a strong pullup will be required to over-ride this internal pull-down. AC_SDIN[1], AC_SDIN[0] • Requires pads for weak 10 kΩ pulldowns. Stuff resistor for unused AC_SDIN signal or AC_SDIN signal going to the CNR connector.
Schematic Review Checklist R 15.7.15 Power Checklist Items Recommendations V_CPU_IO[1:0] • The power pins should be connected to the proper power plane for the processor's asynchronous AGTL+ signals. Use one 0.1 µF decoupling capacitor. VccRTC • No clear CMOS jumper on VccRTC. Use a jumper on RTCRST# or a GPI, or use a safemode strapping for Clear CMOS Vcc3_3 • Requires six 0.1 µF decoupling capacitors. VccSus3_3 • Requires one 0.1 µF decoupling capacitor. Vcc1_8 • Requires two 0.
Schematic Review Checklist R 15.7.16 IDE Interface Checklist Items Recommendations PDD[15:0], SDD[15:0] Reason/Impact • No extra series termination resistors or other pull-ups/pull-downs are required. • These signals have integrated series resistors. • PDD7/SDD7 does not require a 10 kΩ pull-down resistor. • Simulation data indicates that the integrated series termination resistors are a nominal 33 Ω but can range from 31 Ω to 43 Ω. • Refer to ATA ATAPI-4 specification.
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Layout Review Checklist R 16 Layout Review Checklist This checklist highlights design considerations that should be reviewed prior to manufacturing a motherboard that implements an Intel 850 chipset. The items contained within this checklist attempt to address important connections to these devices and any critical supporting circuitry. This is not a complete list and does not guarantee that a design will function properly.
Layout Review Checklist R √ Recommendations Reason/Impact/Documentation • Address signal (A[35:3]# and REQ[4:0]#) length should be 2 inches – 10 inches pinto-pin. Address signals of the same source synchronous group should be routed to the same pad-to-pad length ±200 mils. Length must be added to the motherboard to compensate for package length differences. • The length compensation will result in minimizing the source synchronous skew that exists on the system bus.
Layout Review Checklist R 16.1.2 Asynchronous GTL+ and Other Signals √ 16.1.3 Recommendations Reason/Impact/Documentation • FERR# and PROCHOT connects with the “T” topology. Processor to T-junction should be 1 inch–12 inches. Connection to the ICH2 should be made with no stub. T- junction to pull-up should be 3 inches max. A 7 mil spacing is required. Trace impedance should be 60 Ω. • Refer to Section 5.4.
Layout Review Checklist R 16.1.4 Processor Decoupling √ 16.1.5 Recommendations Reason/Impact/Documentation • Place ten 560 µF OS-CON capacitors as close to the processor power and ground pins as the heatsink keepout area will allow. Refer to Chapter 11 for more detailed placement guidelines. • These capacitors are needed to meet the processor voltage transient specifications. • Place 30 1206 package 10 µF capacitors as close to processor ground and power pins as possible.
Layout Review Checklist R 16.1.6 AGTL+ ( VREF HDVREF [3:0], HAVREF [1:0] and CCVREF) √ Recommendations Reason/Impact/Documentation • Processor must have at least one dedicated voltage divider. There are four GTLREF signals on the processor. Keep voltage divider within 1.5 inches of the first VREF pin. • Refer to Section 5.3. • 82850 MCH requires one dedicated voltage divider. Voltage divider must be within 1.5 inches of MCH VREF ball. • Refer to Section 5.5.
Layout Review Checklist R 16.2 CK00 Routing Guidelines 16.2.1 CK00 Clocking √ Recommendations Reason/Impact/Documentation • 20 mil spacing required around all 100 MHz differential clocks • Refer to Section 4.1. • Differential clocks should be routed on same layer. If via is required, then dummy vias need to be placed on other differential clock signals. • This recommendation is to minimize clock skew due to clock pair to clock pair inconsistencies.
Layout Review Checklist R √ Recommendations Reason/Impact/Documentation • Connect individual 33 MHz clock signals to ICH2, FWH, and SIO. Trace length from CK00 chip to series resistor should be 0–0.5 inches and from series resistor to receiver should be Z + (4 – 6 inches). Route singles on a single layer. • This recommendation insures setup and hold times in relation to the other clock signals are maintained. Clock length routing relationships, located in Section 4.4.
Layout Review Checklist R 16.3 RAMBUS Technology Routing Guidelines 16.3.1 RSL Signals √ 276 Recommendations Reason/Impact • MCH to 1st RIMM* connector of Channel A or 1st RIMM connector of Channel B 1 inch– 6 inches • Refer to Section 6.1.1. • RIMM connector to RIMM connector of the same channel 0.4 to 1 inch. • Refer to Section 6.1.1. • RIMM connector to Termination less than 2 inches. • Length matching in this section is not required.
Layout Review Checklist R √ Recommendations • ALL RSL, CMD/SCK and CTM/CTM#/CFM/CFM# signals have CTABs on each RIMM connector pin. Reason/Impact • Compensation for the inductance of the connector. Voltage and timing margins may be reduced with CTABs. • Refer to Section 6.1.2.5. ® ® • CTABs must not cross (or be on top of) power plane splits. They must be ENTIRELY referenced to ground. • Refer to Section 6.1.2.5. • All RSL signals are routed adjacent to a ground reference plane.
Layout Review Checklist R 16.3.2 Ground Isolation √ Recommendations Reason/Impact • Via to ground every ½ inches around edge of isolation island, between RIMM connectors and between RSL signals (from MCH to 1St RIMM connector) In channel Ideal: Acceptable: 5 inches 0 inches At end Ideal: Acceptable: 25 inches 5 inches * If 3/4 inch end of ground plane: shorten ground plane by 1/4 inch to meet ½ inch recommendation.
Layout Review Checklist R 16.3.3 Vterm Layout √ Recommendations Reason/Impact • Solid VTERM island is on top routing layer; do not split this plane • Ground island (for ground side of VTERM capacitors) is on top routing layer • Termination resistors connect directly to the VTERM island on the top routing layer (without vias) • Resistor packs are acceptable; however, discrete resistors are recommended for increase margin and control. • Refer to Section 6.1.3.
Layout Review Checklist R 16.3.4 Rambus DRCG* Clock Routing Recommendation √ Recommendations Reason/Impact/Documentation • 3VMRef trace routed from CK00 must be 6 mils wide and separated by 6 mil space on both sides. A 6 mil wide ground isolation trace should be placed after 6 mil space. Max trace length is 8 inches. • This recommendation is for microstrip applications. • VddiR pin on DRCG* can be connected to 3.3 V plane near the DRCG if the plane extends near the DRCG. However, if a 3.
Layout Review Checklist R √ Recommendations • CTM and CFM pairs routed differentially should be routed: Reason/Impact/Documentation • Refer to Section 4.3.3.1 22 mil ground trace 6 mil spacing 14 mil trace width (clock) 6 mil spacing 14 mil trace width (clock#) 6 mil spacing 22 mil ground trace. • If CTM and CFM pairs routed single-ended, route: • Refer to Section 4.3.3.1. 10 mil ground trace 6 mil spacing 18 mil wide clock trace 6 mil wide spacing 10 mil ground trace.
Layout Review Checklist R 16.3.6 Rambus DRCG* (CTM/CTM# Output Network Layout) √ Recommendations Reason/Impact • Series resistors (39 Ω) should be mounted very near CTM/CTM# pins. Parallel resistors (51 Ω) should be very near series resistors. • Refer to Section 4.3.5. • CTM/CTM# should be 18 mils wide from the CTM/CTM# pins to the resistors • Refer to Section 4.3.3.1. • CTM/CTM# should be 14 on 6 routed differential as soon as possible after the resistor network.
Layout Review Checklist R 16.4.2 2X/4X Signals The 2X/4X signals are: AD[31:0], C/BE[3:0]#, ADSTB[1:0]#, SBA[7:0], SB_STB, SB_STB# 16.4.2.1 AGP Less Than 6 Inches √ Recommendations Reason/Impact • 5 mil trace width 15 mil separation between data to data for 60 Ω ±10%; for 60 Ω ±15%, its 20 mils • Refer to Section 7.1.2.1. • 5 mil trace width 20 mil separation between data (and all other signals) to strobes for 60 Ω ±10% and 60 Ω ±15% • Refer to Section 7.1.2.1.
Layout Review Checklist R 16.4.2.2 AGP Interface Greater Than 6 Inches and Less Than 7.25 Inches √ Recommendations Reason/Impact • Board impedance must be 60 Ω ±10% • Refer to Section 7.1.2.2. • 5 mil trace width 20 mil separation between data to data • Refer to Section 7.1.2.2. • 5 mil trace width 20 mil separation between data (and all other signals) to strobes • Refer to Section 7.1.2.2. • 5 mil trace width 20 mil separation between strobe to strobe • Refer to Section 7.1.2.2.
Layout Review Checklist R 16.4.4 AGP Connector Decoupling √ 16.5 • One 0.01 µF capacitor next to each power pin on connector, VCC1_5, VDDQ, +5, +12, 3.3VAUX. • Refer to Section 7.1.11. • For Bulk decoupling, need one 10 µF tantalum capacitor to VDDQ and a 20 µF tantalum capacitor on VCC3_3 plane near connector. • Refer to Section 7.1.11. Recommendations Reason/Impact • Board impedance needs to be 60 Ω ±15% • Refer to Section 8.2.
Layout Review Checklist R 16.6 IDE Interface √ 16.7 Recommendations • 5 mil wide and 7 mil spaces • Refer to Section 9.1. • Max trace length is 8 inches long • Refer to Section 9.1. • Shortest trace length must be 0.5 inches shorter than the longest trace length. • Refer to Section 9.1. CNR √ 16.8 Recommendations Reason/Impact • 4.5 inches min to 8.5 inches max trace length for LAN* Connect signals • Refer to Section 9.2. • 60 Ω ±15% • Refer to Section 9.2.
Layout Review Checklist R 16.9 USB √ Recommendations Reason/Impact • Characteristic impedance of individual signal lines P+, P- Zo = 45 Ω (90 Ω Differential) • Refer to Section 9.4. • Stack-up: 9 mils wide, 25 mil spacing between Differential pairs • Refer to Section 9.4. • Trace Characteristics: • Refer to Section 9.4. Line Delay = 160.2 ps Capacitance = 3.5 pF Inductance = 7.3 nH Res @ 20o C = 53.
Layout Review Checklist R 16.11 RTC √ 16.12 Recommendations Reason/Impact • RTC LEAD length ≤ 0.25 inches Max • Refer to Section 9.8.3. • Minimize capacitance between Xin and Xout • Refer to Section 9.8.3. • Put GND plane underneath crystal components • Refer to Section 9.8.3. • Do not route switching signals under the external components (unless on other side of board) • Refer to Section 9.8.3.
Layout Review Checklist R √ Recommendations Reason/Impact • Traces should be routed away from board edges by a distance greater than the trace height above the ground plane. • This allows the field around the trace to couple more easily to the ground plane rather than to adjacent wires or boards. • Do not route traces and vias under crystals or oscillators. • This will prevent coupling to or from the clock. • Trace width to height ratio above the ground plane should be between 1:1 and 3:1.
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Appendix A: Reference Schematics R Appendix A: Reference Schematics The following pages contain reference schematics for both 4 layer and 6 layer 82850 platforms.
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INTEL(R) 850 MPGA478 CUSTOMER REFERENCE BOARD 1.
