Debug Port Design Guide for UP/DP Systems June 2006 Order Number: 313373-001
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Contents 1 How to Use this Document............................................................................................. 7 2 Overview..................................................................................................................... 9 2.1 General Guidelines .............................................................................................. 9 2.1.1 Termination Resistors .............................................................................
.6 4.7 4.8 4.9 4.10 4.11 4.5.5 RESET_OUT# (HOOK7) Routing Guidelines.................................................28 I2C* Routing Guidelines .....................................................................................28 Observation Port Routing Guidelines .....................................................................28 4.7.1 OBSFN_A[1:0] .......................................................................................29 4.7.2 OBSDATA_A[3:0] ........................................
Figures 2-1 2-2 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 4-1 5-1 5-2 5-3 End Termination................................................................................................ 11 Middle Termination ............................................................................................ 11 XDP UP Routing Overview................................................................................... 14 XDP DP Routing Overview...................................................................................
Revision History Document Number 313373 Revision Number -001 Description • White Cover Release Date June 2006 § 6 DPDG for UP/DP SystemsOrder Number: 313373-001
How to Use this Document 1 How to Use this Document This document's primary role is to distribute all of the best-known methods relating to the design of a debug port in Product Name processor based target systems. This document provides implementation details specific to these designs only and takes priority over any discrepancies existing between this document and any previous Debug Port Design Guide.
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Overview 2 Overview The debug port is a connection into a target system environment that provides access to JTAG, run control, and in some cases system control resources. Debug ports come in three styles; XDP, XDP-Sinned ITP700Flex. The eXtended Debug Port (XDP) is a 60-pin, small form factor connector, and is the recommended implementation as it provides for additional silicon / system debug resources compared to other debug port implementations and provides for expansion for future capabilities.
Overview Electrical lengths are provided in units of flight-time. Conversion of flight time to board trace lengths is dependent on what layer routing occurs on, and the dielectric constant of the board materials for a specific design. Rule of thumb numbers can be derived by using 140-180ps/inch for outer layers of an FR4 product and 180ps/inch for inner layers. All JTAG and BPM# signals must be routed using 45-65 ohm +/-10% impedance traces.
Overview Figure 2-1. End Termination V Device Device B Receiver Driver A In the case of Figure 2-1 where there is a termination after the last receiver, A must be smaller than any noted maximum routing length. This is the typical way of showing terminations in this document. There is no restriction for the length of B unless otherwise noted. Figure 2-2.
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XDP Design Guide 3 XDP Design Guide 3.1 Conventions Devices in a scan chain are enumerated by tracing TDI and the scan chain’s TCK from the XDP connector to the first device using both these signals. This device is device #0. Then, trace TDO from device #0 to TDI of device #1, etc. The last device in the scan chain is found by tracing TDO from the XDP connector to TDO of the last device.
XDP Design Guide Figure 3-1.
XDP Design Guide Figure 3-2. XDP DP Routing Overview eXtended Debug Port Vtt A Proc 0 A A A VCC_OBS_AB A B A C OBSDATA_A3 C OBSDATA_A2 C OBSDATA_A1 C OBSDATA_A0 C OBSFN_A1 C OBSFN_A0 TMS G TMS TCK E TCK0 TRST# G BPM0 B BPM1 B BPM2 B BPM3 B BPM4(PRDY) B BPM5(PREQ) TRST# F RESET# G 1K 5% G PWRGOOD G 51 5% HOOK0 ClkOut 51 5% Proc 1 E 51 5% TMS Front Panel Reset 1.5-3.
XDP Design Guide 3.3 JTAG Routing Guidelines 3.3.1 TDI - TDO Routing Guidelines Note: TDI is an output of the debug port connector and TDO is an input of the debug port connector despite their nomenclature. The opposite is true of other JTAG devices. TDI is an input of other devices and TDO is an output. For UP systems using a single scan chain only, route TDI and TDO as indicated in Figure 3-3. There is no need for socket bypass capability Figure 3-3.
XDP Design Guide Figure 3-5. TDI - TDO Jumpered Bypass Routing for DP Systems Vtt Vtt Proc0 51 5% TDI XDP Debug Port 51 5% B TDO A 1 2 A 3 4 TDI A B TDO Vtt Proc1 ` A 51 5% TDI B TDO A A 1 2 A 3 4 Notes: A - These traces have no specific routing requirements. B - This routing has no length requirements. The four-pin bypass jumper can completely isolate a processor socket whenever the processor is not installed in the system.
XDP Design Guide Figure 3-6. TDI - TDO Automatic Bypass for DP Systems A 0 Vtt Proc0 1 51 5% A SKTOCC# A B TDI TDO 1 A Vtt Vtt Proc1 A 0 ` 51 5% SKTOCC# TDI B XDP Debug Port 51 5% A A TDO 0 A TDI A B TDO 1 A Notes: A - These traces have no specific routing requirements. B - This routing has no length requirements. 3.3.
XDP Design Guide 3.4 Run Control Routing Guidelines Please see Section 3.7, “Observation Port Routing Guidelines” on page 21. 3.5 System Control Routing Guidelines System Control operations report or manage the system power, scan, and reset states of the target system. These signals are HOOK[0:7] on the XDP debug port. HOOK[1:3] are generally left as no-connects. 3.5.1 PWRGOOD (HOOK0) Routing Guidelines Route a system PWRGOOD signal directly to the XDP HOOK0 pin.
XDP Design Guide 3.5.6 RESET_IN# (HOOK6) Routing Guidelines The RESET_IN# signal is an input to the run control tool from the front-side bus RESET# signal. Run control tools will not drive RESET#; but uses this signal to sense when a system reset has occurred. Route the front-side bus RESET# signal to the RESET_IN# pin through a 1Kohm isolation resistor. Routing of this signal before the isolation resistor is left to the system designers as part of the system design guides and datasheet.
XDP Design Guide 3.7 Observation Port Routing Guidelines There are 4 observation ports on the XDP labeled A through D. Each observation port is made up of 4 OBSData lines and 2 OBSFN control/strobe lines. These lines in the past have had historical names associated with them. The OBS_Port historically has been referred to as the BPM#[0:5] pins. For reference: OBSFN_x0=BPM5#=PREQ#; OBSFN_x1=BPM4#=PRDY#; OBSDATA_x3=BPM0#; OBSDATA_x2=BPM1#; OBSDATA_x1=BPM2#; OBSDATA_x0=BPM3# 3.7.
XDP Design Guide 3.7.4 OBSDATA_A[3:0] 3.7.4.1 Routing Guidelines Route the CPU BPM[3:0]# point-to-point to the XDP OBSDATA_A[0:3] pins (respectively). Designers should take careful note of the connectivity between pins for these signals (see ). These signals should be terminated at the processor socket: 51 Ohm, 5% to Vtt. 3.7.5 OBSDATA_B[3:0] 3.7.5.1 Routing Guidelines Route the CPU BPM[3:0]# point-to-point to the XDP OBSDATA_B[0:3] pins (respectively).
XDP Design Guide Table 3-1.
XDP Design Guide 3.10 Depopulating XDP for Production Units At some point there may be a desire to remove the debug port from production units. It is recommended that the port real-estate and pads remain in place if they need to be populated for a future problem. Depopulate all physical devices (connector, termination resistors, jumpers) except: • Termination of OBSFN_x[0:1] / BPM[4:5]# / PREQ#, PRDY# • Termination of TCK • Termination of TDI • Termination of TMS • Termination of TRSTn 3.
XDP Design Guide Figure 3-8.
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XDP-SSA Design Guide 4 XDP-SSA Design Guide 4.1 Conventions Special Note: TDI is an output of the debug port connector and TDO is an input of the debug port connector despite their nomenclature. The opposite is true of a processor. TDI is an input of a processor and TDO is an output. 4.2 XDP-SSA Routing Overview The XDP-SSA (Second Side Attach) is a 31-pin alternative to the XDP for those customers needing to place the debug port on the non-component side of the board.
XDP-SSA Design Guide 4.3.3 TRSTn Routing Guidelines The XDP-SSA TRSTn routing guidelines are the same as those for the XDP0 TRSTn routing guidelines (see Section 3.3.4, “TRSTn Routing Guidelines” on page 18). There is no trace length requirement for this signal. 4.4 Run Control Routing Guidelines Please see Section 3.7.2, “Observation Port Routing” on page 21. 4.
XDP-SSA Design Guide These lines in the past have had historical names associated with them. The OBS Port historically has been referred to as the BPM#[0:5] pins. Terminations on these signals vary based on processor. Check the documentation on the last device on each signal to see if it has on-die termination (ODT). If it does not, the signal requires a 51 ohm pull-ups to VTAP. Note that no termination is needed on the debug port side of the transmission lines. 4.7.
XDP-SSA Design Guide Table 4-1.
XDP-SSA Design Guide Cap all vias near the XDP-SSA connector pads in compliance with the Intel DFM Guidelines for capped vias. Figure 4-1.
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ITP700Flex Design Guide 5 ITP700Flex Design Guide ITP700Flex is a slightly smaller connector than the XDP connector, however it has a much smaller keep-out volume because of the connection methodology (flex edge connector). As such many users prefer this connection method for systems that are extremely tight on physical space such as mobile systems and blade servers.
ITP700Flex Design Guide Figure 5-1. ITP700Flex Routing Overview Vtt ITP700Flex Debug Port 0.
ITP700Flex Design Guide 5.3 JTAG Routing Guidelines 5.3.1 TDI - TDO Routing Guidelines Note: TDI is an output of the debug port connector and TDO is an input of the debug port connector despite their nomenclature. The opposite is true of a processor. TDI is an input of a processor and TDO is an output. There is no trace length requirement for TDI/TDO. TDI termination resistor of 150 ohms 5% must be located at the processor end of the trace.
ITP700Flex Design Guide 5.4.1 Reserved (HOOK[0:3]) These signals are reserved. No connections to these signals are required. 5.4.2 ITPCLK/ITPCLK# (HOOK[4:5]) Routing Guidelines A copy of the processor Front Side Bus Clock (usually BCLK[0:1]) needs to be delivered to the debug port by a system clock component. ITPCLK and ITPCLK# are used for noise and synchronizer fault survivability, and as a frequency reference for run control operations when enabled by the run control tool.
ITP700Flex Design Guide into the ICH signal SYS_RESET#. A pull-up resistor must be included on this net of 150 to 240 ohms to the Vtt voltage of the receiver. The resistor should be located near the receiving device. The RESET_OUT# signal has a legacy name of DBR# (Debug Port Reset). 5.5 Observation Port Routing Guidelines These lines in the past have had historical names associated with them. For reference: OBSFN0=BPM5=PREQ; OBSFN1=BPM4=PRDY; OBSDATA3=BPM0; OBSDATA2=BPM1; OBSDATA1=BPM2; OBSDATA0=BPM3.
ITP700Flex Design Guide Table 5-1.
ITP700Flex Design Guide The part number of the connector is Molex* 52435-2891 or equivalent. There is a RoHS compliant version with the Molex* PN of 0524352872. Figure 5-2. ITP700Flex Connector System Keepout Diagram Figure 5-3.
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Appendix A – Debug Port Interposer Considerations A Appendix A – Debug Port Interposer Considerations UP systems may be routed to support interposer-based run control tool debug ports. The following pins need to be connected correctly in order for interposer-based debug ports to function. 1. The DBR# pin of the processor must be connected to the same reset circuit as HOOK7. In fact, as both will not be driven at the same time, connect them directly together. 2.
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