R Voltage Regulator-Down (VRD) 10.
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R Contents 1 Introduction.......................................................................................................................... 7 1.1 2 Processor Voltage Requirements ..................................................................................... 11 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 3 Over-Voltage Protection (OVP) (PROPOSED) ................................................... 41 Over-Current Protection (OCP) (PROPOSED) ...........................................
R 8 Motherboard Power Plane Recommendations (EXPECTED) .......................................... 49 8.1 8.2 8.3 8.4 Minimize Power Path DC Resistance................................................................... 49 Minimize Power Delivery Inductance.................................................................... 49 Four-Layer Boards................................................................................................ 49 Six-Layer Boards ................................................
R Tables Table 1. Design Guideline Requirement Categories........................................................... 8 Table 2. Glossary ................................................................................................................ 8 Table 3. Socket Loadline Equations.................................................................................. 11 Table 4. Vcc Regulator Design Parameters...................................................................... 12 Table 5.
R Revision History Revision Number Description Revision Date -001 • Initial Release. April 2003 -002 • Corrected load line formula in Section 2.2. November 2003 -003 • Added Section 1.1 Terminology and Table 2. Glossary. February 2004 • Section 2.2 added Tables 3 – 5, 10; modified Tables 6 – 9 and Figures 1 –4. • Added Section 2.3 TOB: Tolerance Band. • Renumbered Sections 2.4 – 2.10 to Sections 2.5 – 2.11 • Added Section 2.8.1 Validation summary, Figures 10 – 11 • Added Section 2.9.
Introduction R 1 Introduction This document defines the power delivery feature set necessary to support Intel processors’ Vcc power delivery requirements for desktop computer systems using socket 478. This includes design recommendations for DC-to-DC regulators which convert the 12 V supply to the processor consumable Vcc voltage along with specific feature set implementation such as thermal monitoring and Dynamic Voltage Identification.
Introduction R 1.1 Terminology Table 1. Design Guideline Requirement Categories Term Description REQUIRED An essential feature of the design that must be supported to ensure correct processor and VRD functionality. EXPECTED A feature to ensure correct VRD and processor functionality that can be supported using an alternate solution. The feature is necessary for consistency among system and power designs and is traditionally modified only for custom configurations.
Introduction R Term Description RLL Socket loadline impedance. Defined as the ratio: Voltage droop/current step. This is the loadline slope defined across specific nodes at the processor-socket interface. RSS Root Sum Square. A method of adding statistical variables PROCHOT# Under thermal monitoring, the VRD asserts this processor input to indicate an over-temperature condition has occurred. Assertion of this signal places the processor in a low power state, thereby cooling the voltage regulator.
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Processor Voltage Requirements R 2 Processor Voltage Requirements 2.1 Voltage and Current (REQUIRED) A six-bit VID code transmitted by the processor to the VRD determines a reference output voltage as described in Table 18. The loadlines in Section 2.2 define the relationship between Vcc and Icc for the processor at the socket-motherboard interface across pins AC14 and AC15.
Processor Voltage Requirements R Table 4. Vcc Regulator Design Parameters Iccmax VR TDC Dynamic Icc RLL TOB Maximum VID 478_VR_CONFIG_A 91 A 80 A 70 A 1.24 mΩ ±19 mV 1.4 V 478_VR_CONFIG_B 78 A 68 A 55 A 1.3 mΩ ±25 mV 1.4 V 478_VR_CONFIG_C 70 A 63 A 50 A 1.5 mΩ ±25 mV 1.6 V 478_VR_CONFIG_D 91 A 80 A 70 A 1.5 mΩ ±19 mV 1.6 V VR Configuration VRD transient loadline circuits should meet or exceed rated conditions defined in Table 4.
Processor Voltage Requirements R Table 5. Mapping of Intel Processors to VRD Configurations Processor VR Configuration Intel® Pentium® 4 Processor 478_VR_CONFIG_C Intel® Pentium® 4 Processor with 512-KB L2 Cache on 0.13 Micron Process at 3.40 GHz 478_VR_CONFIG_D Intel® Pentium® 4 Processor Extreme Edition Supporting HyperThreading Technology1 Process 478_VR_CONFIG_D Intel® Pentium® 4 Processor on 90 nm Process1 Intel® Celeron® Processor on 0.
Processor Voltage Requirements R Table 6. Socket 478 Loadline Window for Design Configuration 478_VR_CONFIG_A Presented As a Deviation from VID. Socket Loadline = 1.24 mΩ Ω, VR Tolerance Band = ±19 mV. Icc Maximum Typical Minimum 0A 0.000 V -0.019 V -0.038 V 10 A -0.012 V -0.031 V -0.050 V 20 A -0.025 V -0.044 V -0.063 V 30 A -0.037 V -0.056 V -0.075 V 40 A -0.050 V -0.069 V -0.088 V 50 A -0.062 V -0.081 V -0.100 V 60 A -0.074 V -0.093 V -0.112 V 70 A -0.087 V -0.
Processor Voltage Requirements R Table 7. Socket 478 Loadline Window for Design Configuration 478_VR_CONFIG_B Presented As a Deviation from VID. Socket Loadline = 1.30 mΩ Ω, VR Tolerance Band = ±25 mV. Icc Maximum Typical Minimum 0A 0.000 V -0.025 V -0.050 V 10 A -0.013 V -0.038 V -0.063 V 20 A -0.026 V -0.051 V -0.076 V 30 A -0.039 V -0.064 V -0.089 V 40 A -0.052 V -0.077 V -0.102 V 50 A -0.065 V -0.090 V -0.115 V 60 A -0.078 V -0.103 V -0.128 V 70 A -0.091 V -0.
Processor Voltage Requirements R Table 8. Socket 478 Loadline Window for Design Configuration 478_VR_CONFIG_C Presented As a Deviation from VID. Socket Loadline = 1.50 mΩ Ω, VR Tolerance Band = ±25 mV. Icc Maximum Typical Minimum 0A 0.000 V -0.025 V -0.050 V 10 A -0.015 V -0.040 V -0.065 V 20 A -0.030 V -0.055 V -0.080 V 30 A -0.045 V -0.070 V -0.095 V 40 A -0.060 V -0.085 V -0.110 V 50 A -0.075 V -0.100 V -0.125 V 60 A -0.090 V -0.115 V -0.140 V 70 A -0.105 V -0.
Processor Voltage Requirements R Table 9. Socket 478 Loadline Window for Design Configuration 478_VR_CONFIG_D Presented As a Deviation From VID. Socket Loadline = 1.50 mΩ Ω, VR Tolerance Band = ±19 mV. Icc Maximum Typical Minimum 0A 0.000 V -0.019 V -0.038 V 10 A -0.015 V -0.034 V -0.053 V 20 A -0.030 V -0.049 V -0.068 V 30 A -0.045 V -0.064 V -0.083 V 40 A -0.060 V -0.079 V -0.098 V 50 A -0.075 V -0.094 V -0.113 V 60 A -0.090 V -0.109 V -0.128 V 70 A -0.105 V -0.
Processor Voltage Requirements R To properly calibrate the socket loadline parameter, the VR designer must excite the processor socket with a current step that generates a voltage droop which must be checked against the loadline window requirements. The table below identifies the steady state and transient current values to use for this calibration. For additional information, please consult the Loadline Calculator for the appropriate Intel processor. ® Table 10.
Processor Voltage Requirements R Figure 5.
Processor Voltage Requirements R 2.3 TOB: Voltage Tolerance Band (REQUIRED) Processor loadline specifications must be guaranteed across component process variation, system temperature extremes, and age degradation limits. The VRD topology and component selection must maintain a 3-sigma tolerance of The VRD Tolerance Band around the typical loadline (see Section 2.2). The critical parameters include voltage ripple, VRD controller tolerance, and current sense tolerance.
Processor Voltage Requirements R Table 11.
Processor Voltage Requirements R 2.3.2.1 Inductor RDC Current Sense TOB Calculations Inductor sensing is the best general approach to satisfying the tolerance band requirements. TOB can be directly controlled by selecting output inductors and integrating capacitors of sufficient tolerance. Inductor thermal drift will require thermal compensation to keep the loadline linear (see Section 2.4).
Processor Voltage Requirements R 2.3.2.3 FET RDS-ON Current Sense TOB Calculations Current can be determined by sensing the voltage across the VRD switching FET’s drain to source ‘on’ resistance. While this provides a direct method of voltage to current conversion, the standard FET RDS-ON tolerance of ~20% is not acceptable to satisfy tolerance band requirements. If RDSON sensing is to be applied, FET thermal compensation is required (see Section 2.
Processor Voltage Requirements R 2.5 Processor Electrical and Thermal Current Support (EXPECTED) System boards supporting Intel processors in Socket 478 must have voltage regulator designs compliant to applicable processor’s electrical and electrical-thermal standards. This includes full electrical support of Iccmax specifications and robust cooling solutions to support the VRD thermal design current (VR TDC) indefinitely within the envelope of system operating conditions (see Table 4).
Processor Voltage Requirements R Figure 7. Power Sequence Block Diagram VID_[5.0] VCC _PWRGD VCC VR VCC Output Enable Processor VID_PWRGD VCCVID VR VCC VID Figure 8. Power Sequence Timing Diagram VccVID 1ms min 10 ms max VIDPWRGD VID[5:0] Vcc VID Invalid VID Valid VID Invalid 0 ms min 10 ms max Vcc_PWRGD NOTES: • • • VccVID comes up at the application of system power to the VccVID VR.
Processor Voltage Requirements R through the VID table to a new voltage reference which can be any higher VID code, but is generally the original reference VID. Figure 9 illustrates processor-operating states as the VID level is lowered. The diagram assumes steady state, maximum current during the transition for ease of illustration. In this figure, the processor begins in a high-load condition. Upon entering D-VID, the processor will shift to a low power state and stop executing code (sequence 1 => 2).
Processor Voltage Requirements R Figure 9. Processor D-VID Loadline Transition States 2.8.2 D-VID Validation Intel processors are capable of generating numerous D-VID states and the VRD must be designed to properly transition to and function at each possible code. However, exhaustive validation of each state is unnecessary and impractical. Validation can be simplified by verifying the VRD conforms to loadline requirements, tolerance band specifications, and D-VID timing requirements.
Processor Voltage Requirements R During the D-VID test defined in the previous paragraph, Vcc droop and undershoot amplitudes must be limited to avoid processor damage and performance failures. If the processor experiences an undershoot due to D-VID transitions, an application initiated di/dt droop can superimpose with this event and potentially violate minimum voltage specifications. Droop during this D-VID test must be limited to 5 mV.
Processor Voltage Requirements R Figure 10. D-VID Transition Timing States Transition From Min To Max VID Transition From Max To Min VID 1.6V 1.6V 50µs 762.5mV 300µs Vcc Vcc 0.8375V 762.5mV Vcc Voltage Response Vcc Voltage Response 0.8375V 300µs Time (µs) Time (µs) Initial VID Code Final VID Code 50µs Initial VID Code 350µs Maximum Final VID Code 350µs Maximum Figure 11.
Processor Voltage Requirements R Table 12. D-VID Validation Summary Table Parameter Minimum Typical Maximum VID 0.8375 V - 1.6000 V Voltage Transition 0.7575 V 0.7625 V 0.7675 V Transition Time - - 350µs1 Current Load 5A - VR TDC2 NOTES: 1. Time is measured from 0.4V on rising edge of the first D-VID code to the convergent Vcc voltage value after the final D-VID code is transmitted. 2. Consult Table 4 for definition of VR TDC 2.9 Processor Vcc Overshoot 2.9.
Processor Voltage Requirements R Maximum overshoot in socket 478 is validated by monitoring the voltage across the recommended test pins (defined in Section 2.2) while applying a current load release across the socket Vcc and Vss pin field. Amperage values for performing this validation under each VRD design configuration are identified in Table 15.
Processor Voltage Requirements R Figure 12. Graphical Representation of Overshoot Parameters Figure 13.
Processor Voltage Requirements R Figure 14.
Processor Voltage Requirements R 2.9.2 Example: Socket Vcc Overshoot Test To pass the overshoot specification, the amplitude constraint of Equation 1 and time duration requirement of TOS_MAX must be satisfied. This example references Figure 14. Amplitude Test Constraint: Overshoot amplitude, VOS, must be less than Vzc + VOS_MAX Input parameters VOS= 1.325 V – Obtained from direct measurement VZC = 1.285 V – Obtained from direct measurement VOS_Max = 0.
Processor Voltage Requirements R 2.10 Desktop VR Output Filter (REQUIRED) Processor voltage regulators include an output filter to minimize transient noise on the Vcc rail. Design analysis determined that the most cost efficient filter solution, for satisfying loadline requirements, incorporates 680 µF aluminum-poly capacitors with 5 mΩ average ESR. High frequency noise and ripple suppression is best minimized by 22 µF and/or 10 µF multi-layer ceramic capacitors (MLCC’s).
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Control Inputs R 3 Control Inputs 3.1 Output Enable (REQUIRED) The VRD controller is to recognize the Output Enable signal to assert/disable Vcc regulation. When disabled, the VRD output is to function in a high-impedance state and not source current. Once the VRD is operating after power-up, it should respond to a de-asserted Output Enable by turning off Vcc within 500 ms.
Control Inputs R Table 18. Voltage Identification (VID) Table 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0.8375 0.8500 0.8625 0.8750 0.8875 0.9000 0.9125 0.9250 0.9375 0.9500 0.9625 0.9750 0.9875 1.0000 1.0125 1.0250 1.0375 1.0500 1.0625 1.0750 1.0875 1 OFF 1 OFF 1.1000 1.1125 1.1250 1.1375 1.1500 1.1625 1.1750 1.1875 1.
Input Voltage and Current R 4 Input Voltage and Current 4.1 Input Voltages (EXPECTED) The main power source for the VRD is 12 V ±15%. This voltage is supplied by an AC DC power supply through a cable to the motherboard. For input voltages outside the normal operating range, the VRD should either operate properly or shut down. 4.
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Output Protection R 5 Output Protection Output protection features are necessary to prevent damage to the VRD, the processor, and other system components. 5.1 Over-Voltage Protection (OVP) (PROPOSED) An OVP circuit should monitor the output for an over-voltage condition. If the output is more than 200 mV above the maximum VID level, the VRD should shut off the Vcc supply to the processor. 5.
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Output Indicators R 6 Output Indicators 6.1 Processor Power Good Output (Vcc_PWRGD) (PROPOSED) The VRD must provide a power-good signal, which remains in the low state for a maximum of 10 milliseconds after the output voltage reaches the range specified in Section 2.2. The signal should then remain asserted when the VRD is operating, except for fault or shutdown conditions. Vcc_PWRGD must not be de-asserted due to the low voltage functionality of Dynamic Voltage Identification. Table 19.
Output Indicators R Figure 15: Example VRD Thermal Monitor Circuit Design Vtt Vcc(5) R3 1kΩ Vcc(5) R1 1kΩ R2 499Ω Rpu 130Ω 680Ω + - LM393 PROCHOT# Q1 3904 130Ω 7.5kΩ Rtc 6.8k 0.1uF THMSTR Note: Where R2 = R1/R3 * Rtc. Thermister is NTHS0603N02N6801JR or equivalent. Rtc represents the thermister resistance at maximum allowable temperature.
Output Indicators R PROCHOT# is an open-drain, active-low i/o buffer terminated to the system Vtt (FSB termination voltage). To maintain reliable signaling between thermal monitor circuit, processor, and chipset, the bipolar transistor must be selected to operate with a collector bias established using a single, 130 Ω pull-up resistor. Use of additional termination or pull-up resistors may lead to signal integrity or logic threshold failures.
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VccVID Voltage (PROPOSED) R 7 VccVID Voltage (PROPOSED) The VccVID rail powers the processor VID buffers. This rail must power to regulation and assert an active-high VID_PWRGD output according to the timing specified in Figure 8 and Figure 16 under the signaling conditions defined in Table 21. There is no enable function for the VccVID regulator controller Figure 16. VID PWRGD Timing VccVID 90% Vt td1 90% VID PWRGD 10% Vol td2 tr Table 21.
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Motherboard Power Plane Recommendations (EXPECTED) R 8 Motherboard Power Plane Recommendations (EXPECTED) The motherboard layer stack-up should be designed to ensure robust, noise-free power delivery to the processor. Failure to minimize and balance power plane resistance may result in noncompliance to the die loadline specification. A poorly planned stack-up or excessive holes in the power planes may increase system inductance and generate oscillation on the rail at the processor.
Motherboard Power Plane Recommendations (EXPECTED) R 8.4 Six-Layer Boards Six layer boards provide layout engineers with greater design flexibility. Adjacent plane pairs of the same potential are not useful at higher frequencies, so the best approach is to maximize adjacent, closely spaced Vcc/Vss plane pairs. The plane pair separated by the PCB core material is of lesser importance since it is generally an order of magnitude larger in spacing than other plane pairs in the stack-up.
