64-bit Intel® Xeon® Processor MP with up to 8 MB L3 Cache Specification Update May 2009 Notice: The 64-bit Intel® Xeon® processor MP with up to 8 MB L3 cache may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current characterized errata are documented in this specification update.
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Contents Revision History ................................................................................................................. 5 Preface ............................................................................................................................... 6 Identification Information .................................................................................................... 7 Summary Table of Changes .............................................................................
64-bit Intel® Xeon® Processor MP with up to 8 MB L3 Cache Specification Update
Revision History Version Description Intel® Xeon® Date -001 Initial revision of 64-bit Cache Specification Update. -002 Fix trademarking for Hyper-Threading Technology (HT Technology). April 2005 -003 Added erratum U67. July 2005 -004 Added erratum U68. August 2005 -005 Added errata U69-U70. September 2005 -006 Added erratum U71. October 2005 -007 Added erratum U72. November 2005 -008 Added erratum U73-U74. December 2005 -009 Updated erratum U17.
Preface Preface This is an update to the specifications in the documents listed in the “Affected Documents” and tables. It is a compilation of device and document errata and specification clarifications/changes, and is intended for hardware system manufacturers and software developers. Information types defined in the Nomenclature section of this document are consolidated into this document and are no longer published in other documents. This document may also contain previously unpublished information.
Identification Information Identification Information Figure 1. Top-Side Processor Marking Example 2D Matrix Includes ATPO an Serial Number (front end mark) ATPO Serial Number Pin 1 Indicator Figure 2.
Identification Information Table 1. Identification Information Extended Family1 Extended Model2 Type3 Family4 Model5 00000000b 0000b 00b 1111b 0100b NOTES: 1. 2. 3. 4. 5. The Extended Family corresponds to bits [27:20] of the EDX register after RESET, bits [27:20] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan.
Identification Information Mixed Steppings in the Processor Family MP Systems Intel Corporation fully supports mixed steppings of 64-bit Intel® Xeon® processor MP with up to 8 MB L3 Cache. The following list and processor matrix describes the requirements to support mixed steppings: • Mixed steppings are only supported with processors that have identical family numbers as indicated by the CPUID instruction.
Summary Table of Changes Summary Table of Changes The following table indicates the Errata, Documentation Changes, Specification Clarifications, or Specification Changes that apply to Intel processors. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or specification changes as noted.
Summary Table of Changes Intel® Celeron® M processor Intel® Pentium® M processor on 90 nm process with 2 MB L2 cache Intel® Pentium® M processor Mobile Intel® Pentium® 4 processor with 533 MHz system bus Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor on 65nm process AB = Intel® Pentium® 4 processor on 65 nm process AC = Intel® Celeron® processor in 478-pin package AD = Intel® Celeron® D processor on 65nm process AE = Intel® CoreTM Duo Processor and Intel® CoreTM Solo processor on
Summary Table of Changes Errata (Sheet 1 of 3) No.
Summary Table of Changes Errata (Sheet 2 of 3) No.
Summary Table of Changes Errata (Sheet 3 of 3) No.
Summary Table of Changes Specification Changes No. SPECIFICATION CHANGES None for this revision of the Specification Update Specification Clarifications No. U1 SPECIFICATION CLARIFICATIONS Specification Clarification with respect to Time-Stamp Counter Documentation Changes No. DOCUMENTATION CHANGES None for this revision of the Specification Update.
Errata Errata U1 Transaction is not retired after BINIT# Problem: If the first transaction of a locked sequence receives a HITM# and DEFER# during the snoop phase it should be retried and the locked sequence restarted. However, if BINIT# is also asserted during this transaction, the transaction will not be retried. Implication: When this erratum occurs, locked transactions will not be retried. Workaround: None identified. Status: For the steppings affected, see the Summary Table of Changes.
Errata lock operation accesses data that splits across a page boundary with both pages of WB memory type. The use-once protocol activates and the memory type for the split halves get forced to UC. Since use-once does not apply to stores, the store unlock instructions go out as WB memory type. The full sequence on the Bus is: locked partial read (UC), partial read (UC), partial write (WB), locked partial write (WB). The Use-once protocol should not be applied to Load locks.
Errata occurred while the results of a previous error were in the error-reporting bank. The IA32_MC1_STATUS register should also record this event as multiple errors but instead records this event as only one correctable error. • The overflow bit should be set to indicate when more than one error has occurred. The overflow bit being set indicates that more than one error has occurred.
Errata special cycle to be issued to the bus before the processor vectors to the machine check handler. Once the chipset receives its last Stop Grant special cycle it is allowed to ignore any bus activity from the processors. As a result, processor accesses to the machine check handler may not be acknowledged, resulting in a processor hang. Implication: The processor is unable to correctly report and/or recover from certain errors Workaround: None identified.
Errata U8 EMON event counting of x87 loads may not work as expected Problem: If a performance counter is set to count x87 loads and FP exceptions are unmasked, the FPU Operand (Data) Pointer (FDP) may become corrupted. Implication: When this erratum occurs, FPU Operand (Data) Pointer (FDP) may become corrupted. Workaround: This erratum will not occur with FP exceptions masked. If FP exceptions are unmasked, then performance counting of x87 loads should be disabled.
Errata load lock onto the system bus. A subsequent 8 byte store unlock is expected, but instead a 4 byte store unlock occurs. Correct data is provided since only the lower bytes change, however external logic monitoring the data transfer may be expecting an 8-byte store unlock. Implication: No known commercially available chipsets are affected by this erratum. Workaround: None identified. Status: For the steppings affected, see the Summary Table of Changes.
Errata Workaround: System logic should ensure completion of the outstanding transactions. Note that during recovery from a fatal data ECC error, memory image coherency of the BWL with respect to BRL/BRIL transactions is not important. Forward progress is the primary requirement. Status: For the steppings affected, see the Summary Table of Changes. U17.
Errata U21 Incorrect debug exception (#DB) may occur when a data breakpoint is set on an FP instruction Problem: The default microcode FP event handler routine executes a series of loads to obtain data about the FP instruction that is causing the FP event. If a data breakpoint is set on the instruction causing the FP event, the load in the microcode routine will trigger the data breakpoint resulting in a debug exception.
Errata should be unaffected by the halted logical processor. Due to this erratum, the duty cycle is incorrectly chosen to be the higher duty cycle of both logical processors. Implication: Due to this erratum, higher duty cycle may be chosen when the on-demand clock modulation is enabled on both logical processors. Workaround: None identified. Status: For the steppings affected, see the Summary Table of Changes.
Errata U29 Processor provides a 4-byte store unlock after an 8-byte load lock Problem: When the processor is in the Page Address Extension (PAE) mode and detects the need to set the Access and/or Dirty bits in the page directory or page table entries, the processor sends an 8 byte load lock onto the system bus. A subsequent 8 byte store unlock is expected, but instead a 4 byte store unlock occurs.
Errata translation lookaside buffer (TLB) and used for memory operations. This erratum has not been observed with any commercially available software. Workaround: The guidelines in the IA-32 Intel® Architecture Software Developer’s Manual, Volume 3B: System Programming Guide should be followed. Status: For the steppings affected, see the Summary Table of Changes.
Errata U38 Upper 32 bits of FS/GS with null base may not get cleared in Virtual-8086 Mode on processors with Intel® Extended Memory 64 Technology (Intel® EM64T) Enabled Problem: For processors with Intel EM64T enabled, the upper 32 bits of the FS and GS data segment registers corresponding to a null base may not get cleared when segments are loaded in Virtual8086 mode.
Errata U42 A push of ESP that faults may zero the upper 32-bits of RSP Problem: In the event that a push ESP instruction, that faults, is executed in compatibility mode, the processor will incorrectly zero upper 32-bits of RSP. Implication: A Push of ESP in compatibility mode will zero the upper 32-bits of RSP. Due to this erratum, this instruction fault may change the contents of RSP. This erratum has not been observed in commercially available software. Workaround: None identified.
Errata U47 The Execute Disable Bit fault may be reported before other types of page fault when both occur Problem: If the Execute Disable Bit is enabled and both the Execute Disable Bit fault and page faults occur, the Execute Disable Bit fault will be reported prior to other types of page fault being reported. Implication: No impact to properly written code since both types of faults will be generated but in the opposite order.
Errata Status: For the steppings affected, see the Summary Table of Changes. U52 With Trap Flag (TF) asserted, FP instruction that triggers unmasked FP Exception may tank single step trap before retirement of instruction Problem: If an FP instruction generates an unmasked exception with the EFLAGS.TF = 1, it is possible for external events to occur, including a transition to a lower power state.
Errata Implication: Due to this erratum, Intel EM64T-enabled systems may encounter unexpected behavior when accessing an LDT register using the null selector. There may be no #GP fault in response to this access. Workaround: None identified. Status: For the steppings affected, see the Summary Table of Changes.
Errata U59 An REP MOVS or an REP STOS instruction with RCX >= 2^32 may fail to execute to completion or may write to incorrect memory locations on processors supporting Intel® Extended Memory 64 Technology (Intel® EM64T) Problem: In IA-32e mode using Intel EM64T-enabled processors, an REP MOVS or an REP STOS instruction executed with the register RCX >= 2^32, may fail to execute to completion or may write data to incorrect memory locations.
Errata U63 Machine check registers may contain incorrect information if a correctable error is followed by a un-correctable error Problem: If any two machine check errors (correctable or un-correctable) are detected within the same bus clock, the address and miscellaneous register information for IA32_MC4_ADDR and IA32_ MC4_MISC may not be reliable.
Errata Workaround: None identified. Status: For the steppings affected, see the Summary Table of Changes. U67 It is possible that two specific invalid opcodes may cause unexpected memory accesses Problem: A processor is expected to respond with an undefined opcode (#UD) fault when executing either opcode 0F 78 or a Grp 6 opcode with bits 5:3 of the Mod/RM field set to 6, however the processor may respond instead, with a load to an incorrect address.
Errata U71. Writing the Local Vector Table (LVT) when an interrupt is pending may cause an unexpected interrupt Problem: If a local interrupt is pending when the LVT entry is written, an interrupt may be taken on the new interrupt vector even if the mask bit is set. Implication: An interrupt may immediately be generated with the new vector when a LVT entry is written, even if the new LVT entry has the mask bit set.
Errata U75. Using 2M/4M pages when A20M# is asserted may result in incorrect address translations Problem: An external A20M# pin if enabled forces address bit 20 to be masked (forced to zero) to emulates real-address mode address wraparound at 1 MB. However, if all of the following conditions are met, address bit 20 may not be masked.
Errata Workaround: After initialization, do not expect the FPUDataPointer in a floating point state or floating point environment saved memory image to be correct, until at least one non-control FP instruction with a memory operand has been executed. Status: No Fix U79.
Specification Changes Specification Changes There are no new Specification Changes for this revision. The Specification Changes listed in this section apply to the following documents: 1. 64-bit Intel® Xeon® Processor MP with up to 8 MB L3 Cache Datasheet All Specification Changes will be incorporated into a future version of the appropriate Intel Xeon processor documentation.
Specification Clarifications Specification Clarifications There are no new Specification Clarifications for this revision. The Specification Clarifications listed in this section apply to the following documents: 1. IA-32 Intel® Architecture Software Developer’s Manual, Volume 3B: System Programming Guide (Document Number 253668) 2. IA-32 Intel® Architecture Software Developer’s Manual, Volume 3B: System Programming Guide (Document Number 253669) 3.
Specification Clarifications • For Pentium 4 processors, Intel Xeon processors (family [0FH], models [03H and higher]): the time-stamp counter increments at a constant rate. That rate may be set by the maximum coreclock to bus-clock ratio of the processor or may be set by the frequency at which the processor is booted. The specific processor configuration determines the behavior.
Specification Clarifications • Time-stamp counter — Some processor models permit clock cycles to be measured when the physical processor is not in deep sleep (by using the time-stamp counter and the RDTSC instruction). Note that such ticks cannot be measured on a per-logical-processor basis. See Section 10.8 for detail on processor capabilities. The first two methods use performance counters and can be set up to cause an interrupt upon overflow (for sampling).
Documentation Changes Documentation Changes Note: Documentation changes for IA-32 Intel® Architecture Software Developer’s Manual volumes 1, 2A, 2B, 3A and 3B will be posted in the separate document IA-32 Intel® Architecture Software Developer’s Manual Documentation Changes. Follow the link below to become familiar with this file. http://developer.intel.com/design/pentium4/specupdt/252046.htm There are no new Documentation Changes for this revision.
