Embedded Voltage Regulator-Down (EmVRD) 11.0 Design Guidelines for Embedded Implementations Supporting PGA478

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Order Number: 311395-005

Embedded Voltage Regulator-Down

(EmVRD) 11.0

Design Guidelines for Embedded Implementations

Supporting PGA478

January 2007

Summary of content (48 pages)

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Embedded Voltage Regulator-Down (EmVRD) 11.
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND/OR USE OF INTEL PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT.
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—EmVRD 11.0 Contents 1.0 Introduction.................................................................................................................7 1.1 About This Document........................................................................................... 7 1.2 Terminology ....................................................................................................... 8 1.3 Related Documentation ...................................................................................... 10 2.
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EmVRD 11.0— 10.0 Mother Board Power Plane Layout .................................................................................43 10.1 Minimize Power Path DC Resistance......................................................................43 10.2 Minimize Power Delivery Inductance.....................................................................43 10.3 Ten Layer Board ................................................................................................43 10.3.1 Power Shape Example .........
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—EmVRD 11.0 Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Processor Load Line.................................................................................................. 12 Processor Load Transient Limits ................................................................................. 13 Examples of High Volume Manufacturing Load Line Violations......................................... 15 Examples of High Volume Manufacturing Compliant Load Lines.......................................
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EmVRD 11.0— Revision History Date Revision January 2007 005 Description November 2006 004 • Added support for Intel® Celeron® Processor 1.66 GHz information August 2006 003 • • • Added support for Dual-Core Intel® Xeon® Processor ULV Revised wording on VR11 PWM controller support for 10.x VID table Revised Table 9 to include values April 2006 002 Grammatical edits. March 2006 001 Initial Public Release • Added support for Intel® Celeron® Processor 1.
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1.0—EmVRD 11.0 1.0 Introduction 1.1 About This Document This design guide defines the power delivery features necessary to support Intel processors’ power delivery requirements for embedded computer applications using the following family of processors: • Dual-Core Intel® Xeon® Processor LV • Dual-Core Intel® Xeon® Processor ULV • Intel® Celeron® Processor 1.66 GHz / 1.83 GHz All references to “processor(s)” include all of the above processors unless specific exclusions are mentioned.
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EmVRD 11.0—1.0 This document describes the following areas of implementation in support of the processor: • Processor Load-Line • Tolerance Band (TOB) • Voltage and Current Requirements • Bypass Capacitor Details • Layout Considerations • EmVRD Controller Details This document does not describe the implementation of a enterprise/server VRM/EVRD 10.x or desktop VRD10.x compatible voltage regulator, because they are not compatible with this family of processors. 1.2 Terminology Table 1.
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1.0—EmVRD 11.0 Table 1. Glossary (Sheet 2 of 2) Term Description EMTS A document that defines the processor electrical, mechanical, and thermal specifications. See your Intel representative for access to EMTS documents. Processor Load Line The ratio of voltage drop/current load as measured across the processor Vccsense and Vsssense pins.
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EmVRD 11.0—1.0 1.3 Related Documentation Table 2. Related Documentation Title Location Dual-Core Intel ® Xeon® Processor LV and ULV Thermal Design Guide for Embedded Systems http://www.intel.com/design/intarch/designgd/ 311374.htm Dual-Core Intel ® Xeon® Processor LV and ULV Datasheet http://www.intel.com/design/intarch/datashts/ 311391.htm Intel® Celeron® Processor 1.66 GHz / 1.83 GHz http://developer.intel.com/design/intarch/datashts/ 315876.
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2.0—EmVRD 11.0 2.0 Processor VCC Requirements 2.1 Voltage and Current A six-bit VID code supplied by the processor to the EmVRD controller determines the reference output voltage as described in Section 6.1. The processor load lines in Section 2.2 show the relationship between VCC and ICC for the processor at the processor cores. Intel performs exhaustive testing against multiple software applications and software test vectors to identify valid processor VCC operating ranges.
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EmVRD 11.0—2.0 Table 4. Figure 1. VCC Regulator Design Parameters VR Configuration ICCMAX Dynamic ICC RLL TOB Maximum VID Minimum VID Dual-Core Intel® Xeon® Processor LV 36 A 12.4 A 2.1 mΩ 19 mV 1.25 1.1125 Dual-Core Intel® Xeon® Processor ULV 19 A 5.7A 2.1 mΩ 19 mV 1.2125 1.0 Intel® Celeron® Processor 1.66 GHz / 1.83 GHz 36 A 12.4 A 2.1 mΩ 19 mV 1.275 1.1125 Processor Load Line Offset from VID (V) Processor Load Line 0.04 Vccmax (V)-VID 0.
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2.0—EmVRD 11.0 Figure 2. Processor Load Transient Limits Vcc minus VID (V) Processor Load Line 0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 -0.12 Vccmax (V)-VID Vcctyp (V)-VID Vccmin (V)-VID Vcc Transient Response 0 5 10 15 20 25 Output Current, Icc (A) 30 35 Current Step Operating at a low load-line resistance results in higher processor operating temperature, which can result in damage or a reduced processor life span.
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EmVRD 11.0—2.0 Table 5. Processor Load-Line Window ICC (A) V CCMAX (V) 0 0.019 0.000 -0.019 5 0.009 -0.011 -0.030 10 -0.002 -0.021 -0.040 15 -0.013 -0.032 -0.051 20 -0.023 -0.042 -0.061 25 -0.034 -0.053 -0.072 30 -0.044 -0.063 -0.082 35 -0.055 -0.074 -0.093 40 -0.065 -0.084 -0.103 45 -0.076 -0.095 -0.114 Notes: 1. 2. 3. 4. VCCTYP (V) VCCMIN (V) Presented as a deviation from VID Processor load line slope = 2.
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2.0—EmVRD 11.0 Example A in Figure 3 shows a load line that is contained in the specification window and in this instance, complies with VCCMIN and VCCMAX specifications. The positioning of this processor load line will shift up and down as the tolerance drifts from typical to the design limits. Example B in Figure 3 shows that VCCMAX limits will be violated as the component tolerances shift the load line to the upper tolerance band limits.
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EmVRD 11.0—2.0 Figure 4. Examples of High Volume Manufacturing Compliant Load Lines 3-σ Manufacturing LL Measured Load Line Vccmax LL 2.
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2.0—EmVRD 11.0 • The controller should support voltage amplitudes read across sense elements with a DCR of 0.1 – 2.0 mΩ. Controller vendors should define the minimum sense signal voltage necessary to satisfy their controller signal to noise ratio requirements. These requirements are to be published by the vendor in their controller datasheet. • Vendors should establish an inductor DCR sense topology that supports a ±19 mV TOB @ 1.25 VID, 36 A ICCMAX, 2.
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EmVRD 11.0—2.0 2.3.5 Error Amp Specification The EmVRD controller chosen should provide an error amp with a sufficient gain BW product to ensure duty cycle saturation does not occur with large signal current transients. Typical target closed loop VR bandwidths of 30-200 kHz (20% of switching frequency target) are expected in EmVRD 11.0 system designs. The output of the error amp should also have high slew rates to avoid duty cycle saturation.
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2.0—EmVRD 11.0 During a D-VID event, the processor load may not be capable of absorbing output capacitor energy when the VID reference is lowered. As a result, reverse current may flow into the AC-DC regulator’s input filter, potentially charging the input filter to a voltage above the over voltage value. Upon detection of this condition, the AC-DC regulator will react by shutting down the AC-DC regulator supply voltage. The EmVRD and AC-DC filter must be designed to ensure this condition does not occur.
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EmVRD 11.0—2.0 2.5.2 D-VID Validation Note: Performance tests and ratings are measured using specific computer systems and/or components and reflect the approximate performance of Intel products as measured by those tests. Any difference in system hardware or software design or configuration may affect actual performance. Buyers should consult other sources of information to evaluate the performance of systems or components they are considering purchasing.
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2.0—EmVRD 11.0 d. Undershoot during maximum to minimum VID transition must be limited to 5 mV. This 5 mV is included within the +/-5 mV tolerance on the final VID value defined under test condition A. e. Overshoot observed when transitioning from minimum to maximum VID must conform to overshoot specifications. Specifically, superposition of the dynamic VID overshoot event and the overshoot resulting from the transient test defined in Section 2.
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EmVRD 11.0—2.0 Figure 7. Overshoot and Undershoot During Dynamic VID Validation Transition From Min To Max VID Transition From Max To Min VID 1.5 V Limit undershoot of DC transition to 5mV 1.5 V Vcc Vcc 0.8375 V 0.8375 V Must be compliant to overshoot specifications Time (μs) Table 7. Time (μs) D-VID Validation Summary Table Parameter Minimum Typical Maximum VID 0.8375 V - 1.5000 V 1 Voltage Transition 0.6575 V 0.6625 V 0.
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2.0—EmVRD 11.0 Table 8. VCC Overshoot Terminology Parameter Table 9.
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EmVRD 11.0—2.0 same voltage level. Since waveform A has zero overshoot amplitude margin, this increase in Vzc due to manufacturing drift will yield a 20 mV overshoot violation which will reduce the processor life span. To address this issue in validation, a voltage margining technique can be employed to ensure overshoot amplitudes stay below a safe value.
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2.0—EmVRD 11.0 Figure 9. Example Processor VCC Overshoot Waveform 2.6.2 Example: Processor VCC Overshoot Test To pass the overshoot specification, the amplitude constraint of Equation 4 and time duration requirement of TOS_MAX must be satisfied. This example references Figure 9. Amplitude Test Constraint: Overshoot amplitude, VOS, must be less than Vzc + VOS_MAX Input parameters: • VOS= 1.325V: Obtained from direct measurement • VZC = 1.285V: Obtained from direct measurement • VOS_MAX = 0.
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EmVRD 11.0—2.0 2.7 EmVRD Output Filter Embedded processor voltage regulators include an output filter consisting of large bulk decoupling capacitors to compensate for large transient voltage swings and small value ceramic capacitors to provide high frequency decoupling. This filter must be designed to stay within load line specifications (Figure 1 and Table 3) across tolerances due to age degradation, manufacturing variation, and temperature drift. 2.7.
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2.0—EmVRD 11.0 Note: EmVRD processor load line calibration with the VTT does not guarantee adequate high frequency decoupling to reduce package noise. This noise is directly dependent upon the processor core frequency, so the filter must guarantee adequate decoupling to support all frequencies the board is to support. Table 11.
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EmVRD 11.0—3.0 3.0 VCCP Requirements The VCCP regulator provides power to the processor VID pull-up resistors, the chipset processor front side bus, and miscellaneous buffer signals. This rail voltage must converge to the amplitude defined in Table 9 to begin power sequencing. The EmVRD controller will sense the amplitude of the VCCP rail and initiate power sequencing upon crossing a defined threshold voltage.
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3.0—EmVRD 11.0 Table 12. VCCP Specifications Number of CPU Sockets Processor VCCP Min VCCP Typ VCCP Max Itt Min1 Itt Max2 Itt Max3 One Socket Design2 Dual-Core Intel ® Xeon® Processor LV, and Dual-Core Intel® Xeon® Processor ULV and Intel® Celeron® Processor 1.66 GHz / 1.83 GHz 0.9975 V 1.05 V 1.1025 V 0.15 A 6A 2.5 A Two Socket Design2 Dual-Core Intel ® Xeon® Processor LV and Dual-Core Intel® Xeon® Processor ULV and Intel® Celeron® Processor 1.66 GHz / 1.83 GHz 0.9975 V 1.05 V 1.
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EmVRD 11.0—4.0 4.0 Power Sequencing EmVRD 11.0 features a power sequence that is compatible with both VR11 and VR10 processors. To avoid compatibility problems with VR11 architecture, EmVRD 11.0 systems must not use the legacy VR10 start sequence. Embedded VR11 systems can use a pull-up resistor tied to the VCCP supply as an enable signal or provide additional sequencing or check circuits before enabling.
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4.0—EmVRD 11.0 input rails. If either the Vcc or power conversion rail fall below the UVLO thresholds, the controller should shut down in an orderly manner and restart the start up sequence. 4.4 Soft Start (SS) The EmVRD controller will have a soft start function to limit inrush current into the output capacitor bank and prevent false over current protection (OCP) trips. The soft start should have a ramp of 500 s as an internally programmed default.
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EmVRD 11.0—4.0 Figure 11. Power-Off Timing Sequence TD7 PWM Vcc VTT A N D VR_READY Vcc VID [5:0] VIDSELECT Note: Timing is not to scale. Table 15. Start-Up and Power-Off Sequence Timing Start up Delay Parameters Parameter Minimum Typical, Default Maximum TD1 TD2 1 ms - 5 ms 0 ms 500 µs 5 ms TD3 50 µs - 3 ms TD4 0 µs 250 µs 2.5 ms TD5 0 ms - 3 ms TD6 500 µs TD7 0 ms - 1 ms Embedded Voltage Regulator-Down (EmVRD) 11.
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4.0—EmVRD 11.0 Figure 12. Start-Up Sequence Functional Block Diagram ++ ' () % "# %* ") # + % , +" " , + +- % "# ! & $ %% $ # " January 2007 Embedded Voltage Regulator-Down (EmVRD) 11.
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EmVRD 11.0—5.0 5.0 EmVRD Current Support System boards supporting processors must have voltage regulator designs compliant to electrical and thermal standards defined in Table 4. This includes full electrical support of Iccmax specifications and regulator layout, processor fan selection, ambient temperature, chassis configuration, etc. Consult Table 4 and Table 9 for processor VCC and VCCP current limits.
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6.0—EmVRD 11.0 6.0 Control Inputs 6.1 Voltage Identification (CPU VID [5:0], EmVRD [6:1]) The EmVRD controller must accept an 8-bit code transmitted by the processor to establish the reference VCC operating voltage. VR 11.0 based controllers support both VR10.x and VR11.0 VID tables, only the VR11.0 will be used by the processors and will be discussed in this document. The processors use six VID pins.
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EmVRD 11.0—6.0 Figure 13. D-VID Bus Topology Processor PWM Controller L1 L2 RTT Table 16. VID Buffer And VID Bus Electrical Parameters Design Parameter Minimum Typical Maximum - Vccp1 - - 0.100 - Vccp2 VIH 0.8 V - - VIL - - 0.3 V L1, VID trace length 0.5 inch - 15 inches L2, Vccp Stub Length 0 inch - 1 inch VID trace length skew - 1.
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6.0—EmVRD 11.0 Table 17. VR11 VID Table from 1.5 V to 0.81875 V (Sheet 1 of 2) VR 7 CPU 0 January 2007 6 5 4 3 2 1 0 VID<7-0> 5 4 3 2 1 0 0 0 0 0 0 0 0 0 1 0 0 1 1.50000 0 0 1 0 1 0 1.48750 0 0 1 0 1 1 1.47500 0 0 1 1 0 0 1.46250 0 0 1 1 0 1 1.45000 0 0 1 1 1 0 1.43750 0 0 1 1 1 1 1.42500 0 1 0 0 0 0 1.41250 0 1 0 0 0 1 1.40000 0 1 0 0 1 0 1.38750 0 1 0 0 1 1 1.37500 0 1 0 1 0 0 1.
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EmVRD 11.0—6.0 Table 17. VR11 VID Table from 1.5 V to 0.81875 V (Sheet 2 of 2) VR CPU 6.2 7 6 5 4 3 2 1 0 VID<7-0> 5 4 3 2 1 0 VID<5-0> 1 0 1 1 1 0 1.03750 1 0 1 1 1 1 1.02500 1 1 0 0 0 0 1.01250 1 1 0 0 0 1 1.00000 1 1 0 0 1 0 0.98750 1 1 0 0 1 1 0.97500 1 1 0 1 0 0 0.96250 1 1 0 1 0 1 0.95000 1 1 0 1 1 0 0.93750 1 1 0 1 1 1 0.92500 1 1 1 0 0 0 0.91250 1 1 1 0 0 1 0.90000 1 1 1 0 1 0 0.
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7.0—EmVRD 11.0 7.0 Input Voltage and Current 7.1 Input Voltages EmVRD output voltage is supplied via DC-to-DC power conversion. To ensure proper operation, the input supplies to these regulators must satisfy the following conditions. 7.1.1 Platform Input Voltages The most common power source for the Vcc EmVRD is 12 V ±15% and 3.3 V or 5 V for the VCCP supply. These voltages are supplied by an AC-DC power supply through cabling to the motherboard inputs.
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EmVRD 11.0—8.0 8.0 Output Protection This section describes features that are built into the EmVRD controller to prevent damage to itself, the processor, validation tools, or other system components. Intel highly recommends that system designers choose a VR11 controller that supports these features. 8.1 Over-Voltage Protection (OVP) OVP is intended to protect the processor from high voltage damage that may lead to failure, or a reduced processor life span.
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9.0—EmVRD 11.0 9.0 Output Indicators 9.1 VR_READY: VCC Regulator Is ‘ON’ VR_READY is an active high output that indicates the start-up sequence is complete and the output voltage has moved to the programmed VID value. This signal is used for start-up sequencing for other voltage regulators, the clock, and microprocessor reset. It is tied to processor PWRGOOD input pin. This signal should not be de-asserted during D-VID operation.
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EmVRD 11.0—9.0 To avoid performance degradation resulting from EmVRD over-temperature conditions, VR11 PWM controllers include a signal called VR_FAN. This signal is activated at 90% of the max VR_HOT trip point. It provides the system designer with options to perform thermal management activities, such as fan speed control, in order to avoid initiating performance degradation. The controller is located away from the EmVRD ‘hot spot’; therefore, external thermistors are needed to sense temperature.
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10.0—EmVRD 11.0 10.0 Mother Board Power Plane Layout The motherboard layer stack-up must be designed to ensure robust, noise-free power delivery to the processor. Failure to minimize and balance power plane resistance may result in non-compliance to the processor load line specification. A poorly planned stack-up or excessive holes in the power planes may increase system inductance and generate oscillation on the Vcc voltage rail at the processor.
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EmVRD 11.0—10.0 path to the processors. Using the bottom and internal layers where possible to provide CPU core planes is also recommended. A complete stack-up example of processor reference board is provided in Table 20. Table 20. Reference Board Layer Stack-up Layers L1 (Top-PWR) L2 (Plane-GND) L3 (Signal) L4 (Plane-GND) L5 (Signal) L6 (Signal) L7 (Plane-GND) L8 (Signal) L9 (Plane-GND) L10 (Bottom-PWR) Note: Material Thickness (mils) Soldermask 1.0 Plating 1.4 Copper 0.6 Prepreg 4.
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10.0—EmVRD 11.0 Figure 15. Layer 1 VCC Shape For Intel’s Reference Ten Layer Motherboard Bulk Bypass MLCC Bypass PGA 478 Socket 3 Phase VR (Inductors) Note: Eight Bulk Bypass Capacitors are shown, two are extra for testing purposes, six are recommended. January 2007 Embedded Voltage Regulator-Down (EmVRD) 11.
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EmVRD 11.0—10.0 Figure 16. Layer 10 VCC Shape For Intel’s Reference Ten Layer Motherboard MLCC Bypass VCCP Shape PGA 478 Socket VCC Core Shape 10.3.2 Ganging Common Pins To maximize the benefit of using the top layer for VCC delivery, the power shape should directly capture all possible socket VCC pads. Using the pattern shown in Figure 17 allows the VCC shape to flow through both sides of the CPU socket and make direct connection with the mid-frequency decoupling capacitors in the socket cavity.
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10.0—EmVRD 11.0 Figure 17. Note: Layer 1 CPU Socket VCC/GND Routing For Intel’s Reference Ten Layer Motherboard The copper pour and black pins denotes VCC , the gray denotes VSS 10.4 Resonance Suppression VCC power delivery designs can be susceptible to resonance phenomena capable of creating droop amplitudes in violation of load line specifications. This is due to the interleaved levels of inductively-separated decoupling capacitance.
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EmVRD 11.0—10.0 are strongly recommended to identify and resolve power delivery resonances before boards are actually built. Careful modeling and validation can help avoid voltage violations responsible for data corruption, system lock-up, or system ‘blue-screening’. Embedded Voltage Regulator-Down (EmVRD) 11.