Intel® Xeon™ Processor MultiProcessor Platform Design Guide November 2002 Document Number: 250397-002
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Contents 1 Introduction ................................................................................................................11 1.1 1.2 2 Related Documentation.......................................................................................11 Conventions and Terminology.............................................................................13 System Overview......................................................................................................17 2.1 2.
6.4.3 7 Mechanical and EMI Design Considerations ................................................ 51 7.1 7.2 8 Retention Mechanism Placement and Keep-Outs .............................................. 51 Electromagnetic Interference Considerations ..................................................... 54 7.2.1 Introduction ............................................................................................ 54 7.2.2 Terminology .....................................................................
8.12 8.13 9 Methodology for Determining Topology and Routing Guidelines .......91 9.1 9.2 10 Timing Methodology ............................................................................................92 9.1.1 Source Synchronous ..............................................................................92 9.1.1.1 Setup Time ................................................................................93 9.1.1.2 Hold Time ..........................................................................
Figures 3-1 3-2 4-1 4-2 4-3 5-1 5-2 5-3 5-4 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13 8-14 8-15 6 Top View - Intel® Xeon™ Processor MP Socket Quadrant Layout..................... 19 Top View - Intel® Xeon™ Processor MP with up to 2-MB L3 Cache on the 0.13 Micron Process Socket Quadrant Layout....................................................
8-16 8-17 8-18 8-19 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 10-1 10-2 10-3 10-4 10-5 Filter Specifications .............................................................................................87 Implementation 1 Using Discrete R.....................................................................88 Implementation 2 No Discrete R .........................................................................89 Example of Decoupling for a Microstrip Baseboard Design ........................
Tables 1-1 1-2 2-1 2-2 4-1 5-1 6-1 6-2 6-3 6-4 8-1 8-2 8-3 8-4 8-5 8-6 8-7 9-1 10-1 11-1 8 References.......................................................................................................... 11 Platform Conventions and Terminology .............................................................. 13 Intel® Xeon™ Processor MP Feature Set Overview ........................................... 18 Platform Bandwidth Summary............................................................................
Revision History Revision -001 -002 Draft/Changes Initial version ® Added Intel Xeon™ Processor MP with up to 2-MB L3 Cache on the 0.13 Micron Process information.
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Introduction 1 Introduction This design guide documents Intel's design recommendations for systems based on the Intel® Xeon™ processor MP and Intel® Xeon™ processor MP with up to 2-MB L3 Cache on the 0.13 Micron Process using non-Intel designed chipsets.
Introduction Table 1-1. References (Sheet 2 of 2) Intel® Xeon™ Processor Multiprocessor (MP) Thermal Design Guidelines 298650 603 Pin Socket Design Guidelines 249672 Intel® Xeon™ Processor Thermal Solution Functional Specification 249673 ® Intel Xeon™ Processor Signal Integrity Model (IBIS format) ® Intel Xeon™ Processor Overshoot Checker Tool developer.intel.com ® 12 developer.intel.com Mechanical Drawings in Pro-E* Format for the Intel Xeon™ Processor Enabled Solutions developer.intel.
Introduction 1.2 Conventions and Terminology This section defines conventions and terminology that will be used throughout this document. Table 1-2. Platform Conventions and Terminology (Sheet 1 of 3) Convention/ Terminology Definition 4-way Used to specify a system configuration using four processors. Aggressor A network that transmits a coupled signal to another network is called the aggressor network.
Introduction Table 1-2. Platform Conventions and Terminology (Sheet 2 of 3) Convention/ Terminology Definition Flight time is a term in the timing equation that includes the signal propagation delay, any effects the system has on the TCO of the driver, plus any adjustments to the signal at the receiver needed to guarantee the setup time of the receiver.
Introduction Table 1-2. Platform Conventions and Terminology (Sheet 3 of 3) Convention/ Terminology SSO Definition Simultaneous Switching Output (SSO) Effects refers to the difference in electrical timing parameters and degradation in signal quality caused by multiple signal outputs simultaneously switching voltage levels (e.g., high-to-low) in the opposite direction from a single signal (e.g., low-to-high) or in the same direction (e.g., high-to-low).
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System Overview System Overview 2.1 2 The Intel® Xeon™ Processor MP and the Intel® Xeon™ Processor MP with up to 2-MB L3 Cache on the 0.13 Micron Process The Intel Xeon processor MP is the next generation IA-32 microprocessor for servers. The processor is based on Intel® NetBurst™ microarchitecture but maintains the tradition of complete compatibility with IA-32 software.
System Overview processor family system bus, but is not compatible with the P6 processor family system bus. The system bus uses Source-Synchronous Transfer (SST) of address and data to improve performance. Whereas the P6 processor family data transfer is once per bus clock, the Intel Xeon processor MP and Intel Xeon processor MP with up to 2-MB L3 cache on the 0.13 micron process transfer data four times per bus clock (4X data transfer rate, as in AGP 4X).
Processor Quadrant Layout 3 Processor Quadrant Layout Figure 3-1 illustrates the quadrant layout of the Intel Xeon processor MP. Figure 3-2 illustrates the quadrant layout of the Intel Xeon processor MP with up to 2-MB L3 cache on the 0.13 micron process. In the event that this layout conflicts with the respective Intel Xeon Processor MP Datasheets, the datasheets supersede. The quadrant layout figures below do not show the exact component ball count, only the general quadrant information.
Processor Quadrant Layout Figure 3-2. Top View - Intel® Xeon™ Processor MP with up to 2-MB L3 Cache on the 0.13 Micron Process Socket Quadrant Layout COM M ON CLOCK 3 5 7 9 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE 11 13 15 19 21 23 25 27 29 31 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE Up to 2-MB L3 Cache on 0.
Platform Stack-Up and Placement Overview Platform Stack-Up and Placement Overview 4.1 4 Platform Component Placement The figures below illustrate general component placement for server systems. The assumptions used for the component placement are documented in Table 4-1. Figure 4-1.
Platform Stack-Up and Placement Overview Table 4-1. Placement Assumptions for Server Configurations Assumptions System Configuration Form Factor Server (4-way) 4.2 Midrange SSI Number of Total PCB Layers 12 Layers Assembly Double Sided 4-Way System Stack-Up Design recommendations will be presented first followed by design considerations. 4.2.1 Design Recommendations Figure 4-2 shows the recommended Intel Xeon processor MP and Intel Xeon processor MP with up to 2-MB L3 cache on the 0.
Platform Stack-Up and Placement Overview 4.2.2 Design Considerations The following design considerations are based on Intel's intentions for validation systems. These validation systems are targeted to provide a high quality platform with optimized signal integrity, timing margins, and power distribution. They therefore represent Intel's recommended platform design for the Intel Xeon processor MP and Intel Xeon processor MP with up to 2-MB L3 cache on the 0.13 micron process.
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Clock Routing Guidelines Clock Routing Guidelines 5.1 System Bus Clocking Guidelines 5.1.1 Routing Guidelines for BCLK[1:0] Note: 5 For designs using non-Intel chipsets please contact the corresponding chipset vendor for specific information regarding clock driver and baseboard design requirements. To minimize jitter and improve routing, the 4-way Intel Xeon processor MP and Intel Xeon processor MP with up to 2-MB L3 cache on the 0.13 micron process system may use a dual-chip clock solution.
Clock Routing Guidelines Figure 5-1. 4-Way Processor BCLK Topology Processor 0 RT Rs Clock Driver Rs RT Processor 1 RT Rs Rs RT RT Rs CKx_WBY Processor 2 Rs RT RT R s R s RT Processor 3 R T Rs Rs RT Chipset RT Rs Rs RT Debug port The CK00 clock driver differential bus output structure is a “Current Mode Current Steering” output which develops a clock signal by alternately steering a programmable constant current to the external termination resistors RT.
Clock Routing Guidelines Figure 5-2. Source Shunt Termination Differential Bus Clock Topology. (one pair h ) L2 L1 L1' L2’ RS CLOCK DRIVER CPU or CS L4 L4 L3 L3 RT LT = L1+L2+L4 Ck00 pin Cpu or CS pin The goal of constraining all bus clocks to one physical routing layer is to minimize the impact on skew due to variations in Er and the impedance variations due to physical tolerances of circuit board material. Routing on internal layers provides the least amount of Er and impedance variation.
Clock Routing Guidelines Table 5-1. BCLK[1:0]# Routing Guidelines (Sheet 2 of 2) Maintain a minimum S/h ratio of > 5/1 Serpentine spacing Keep parallel serpentine sections as short as possible Figure 5-4 Minimize 90 degree bends. Make 45 degree bends if possible. Motherboard Impedance – Differential 100 Ω typical 6 Motherboard Impedance – single ended 50 Ω ± 10% 7 Processor routing length – L1: CK_WBY/CK_SKS to RS 0.
Clock Routing Guidelines 10.RS values between 20 Ω – 33 Ω have shown to be effective. The value specified is the recommended value. 11. RT values should match the motherboard trace impedance for BCLK. 12.Minimize the trace lengths from the clock driver pin to RS, from RS to RT stub and the length of the RT stub. Figure 5-3. Agent-to-Agent BCLK Skew BCLK1 Agent 0 BCLK0 Agent 0 BCLK1 Agent 1 BCLK0 Agent 1 Tclkskw Figure 5-4.
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System Bus Routing System Bus Routing 6 Table 6-1 summarizes the layout recommendations for 4-way processor-based configurations. It should be used for quick reference only. The following sections provide more detailed information about the different system configurations. Table 6-1. System Bus Routing Summary for 4-Way Processor Configurations (Sheet 1 of 2) Parameter 4-Way: Intel® Xeon™ Processor MP and Intel® Xeon™ Processor MP with up to 2-MB L3 Cache on the 0.
System Bus Routing Table 6-1. System Bus Routing Summary for 4-Way Processor Configurations (Sheet 2 of 2) Parameter Reference plane requirements 4-Way: Intel® Xeon™ Processor MP Signals should be routed in a symmetric stripline configuration. Avoid changing layers when routing system bus signals. If a layer change must occur, use vias connecting the VCC planes and/or VSS planes to provide a low impedance path for the return current. Vias should be as close as possible to the signal via.
System Bus Routing • For symmetric stripline, return path vias for both VSS and VCC must be provided. • Do not switch reference from VCC to VSS or vice versa. 6.2 Serpentine Routing A serpentine net is a transmission line that is routed in such a manner so that sections of the net double back and couple to another segment of the same net. A serpentining transmission line is sometimes necessary to properly match lengths between nets.
System Bus Routing 6.3.1 Processor I/O Decoupling Requirements The primary objective of the processor I/O decoupling guidelines is to minimize the impact of return path discontinuities. The processor power delivery guidelines help insure the processor I/O has adequate power decoupling. The worst-case return path discontinuity anticipated is for systems that use microstrip structures on the motherboard.
System Bus Routing 6.3.2 Chipset System Bus I/O Decoupling Recommendations The primary objective of the I/O decoupling recommendations for the chipset is to provide clean power delivery to the system bus I/O buffers. The split power-plane nature of chipsets creates this power delivery concern. A noisy or starved power supply will negatively impact the signal quality and/or drive strength seen on the system bus signals.
System Bus Routing The following recommendations are Intel's best guidelines based on extensive simulation and experimentation based on our reference platform. It is therefore strongly recommended to perform a simulation analysis based on your platform. Table 6-2 presents all signals interfacing with the processors. This table is included for reference purposes only. Refer to the processor datasheet for current signal interfacing details. Table 6-2.
System Bus Routing 6.4.1 Topology and Routing Design recommendations will be presented first followed by design considerations. The layout guidelines given in this section are based on specific chipset (I/O buffer, package, and loading) and motherboard properties. Complete simulation and hardware validation is necessary to ensure a robust design. 6.4.1.1 Design Recommendations Below are the design recommendations for the data, address, strobes, and common clock signals. Figure 6-4.
System Bus Routing Figure 6-5. Cross-Sectional View of 3:1 Ratio for Symmetric Stripline (Edge-to-Edge Trace Spacing vs. Trace to Reference Plane Height) reference plane x trace trace 3x x reference plane For partially populated systems, the end processor must be populated first. The end processor is that furthest from the chipset. This effectively leaves only the socket as a stub on the bus for the unpopulated agents. Also, the on-die termination must be enabled on the end processor.
System Bus Routing distance from the package pin of one agent to the package pin of the next should be between 3.0 inches and 6.1 inches. There is an “island” of failing solution space based on L1 and L2 lengths. Refer to Figure 6-6 for a diagram of acceptable routing lengths. The island in Figure 6-6 represents a configuration where the ringback on the system bus violates specification. This ringback is also a factor of ISI buildup over multiple cycles.
System Bus Routing Equation 6-1. Processor Package Length Compensation to Be Added to Motherboard Trace PD = deltanet , group = max_ cpu _ pkglengroup − cpu _ pkglennet Compensating for the chipset package lengths on the motherboard is also necessary. The amount that should be added can be calculated using Equation 6-2. This length is compensated for on L4. Equation 6-2.
System Bus Routing Signals of the same source synchronous group should match the compensated lengths within 25 mils agent-to-agent and 100 mils over the entire length of the bus. It is not necessary to match lengths of one 4X signal group to other 4X signal groups. All signals must meet their setup and hold timing requirements. In addition, strobes should maintain a 25-mil spacing from all other signals, including other strobes (DSTBn# and DSTBp#).
System Bus Routing Figure 6-7. Wired-OR Topology Vcc_CPU Vcc_CPU 143 Ω Chipset L4 143 Ω L3 Proc 3 Proc 4 Vcc_CPU L2 143 Ω L1 Proc 1 6.4.1.6 Proc 2 Design Considerations Intel has found that the following recommendations provide one method of designing a 4-way processor platform. This is a baseline configuration only. Modify this baseline as needed while adhering to the above Design Recommendations. • Maintain a trace width of 4.0 mil to provide a 47 Ω trace impedance.
System Bus Routing Figure 6-8. 0.025" Via Pad with 50% of Trace over Reference Plane Assumptions: Inner signal layers: 10 mil via hole 5 mil clearance Inner plane layers: 35 mil antipad Outer plane layers: 25 mil surface anti-pad 30 mil routing path 15 mil power plane Top View Cross-sectional View 4 mil Signal Trace 4 mil Signal Trace 15 mil power plane 5 mils 15 mil power plane 2.5 mils 5 mils 2.
System Bus Routing Table 6-4.
System Bus Routing To protect the processors from damage in over-temperature situations, motherboard and/or chipset logic must ensure that power to the processor core is removed within 0.5 seconds after the assertion of THERMTRIP#. If power is applied to a processor when no thermal solution is attached, normal leakage currents will cause the die temperature to rapidly rise to levels at which permanent silicon damage is possible. This high temperature will cause THERMTRIP# to go active.
System Bus Routing 6.4.2.2 Topology 2: Asynchronous GTL+ Signals Driven by the Chipset; A20M#, IGNNE#, INIT#, LINT[1:0], PWRGOOD, SLP#, SMI#, and STPCLK# These signals should adhere to the following routing and layout recommendations. Figure 6-11 illustrates the recommended topology. When routing to middle agents connect in true daisy chain topology. Do not create a stub to connect to the socket pins.
System Bus Routing The SM_TS_A[1:0] signals set the SMBus address for the thermal device on the processor. These signals need to be set at power up with a unique address per bus. The SM_TS_A[1:0] can be set to a logic high, a logic low, or a high impedance state giving nine possible combinations of addresses. Refer to the section on SMBus Device Addressing in the datasheet for addressing details.
System Bus Routing 6.4.2.6 Topology 6: COMP[1:0] Signals For details regarding termination of COMP[1:0] pins, please refer to the processor datasheet. Do not wire COMP pins together; connect each pin to its own termination resistor. 6.4.2.7 Topology 7: ODTEN Signal The end processor in a 4-way processor system must have its on-die termination enabled. The middle agent should disable the on-die termination. To enable, pull the ODTEN pin to a high state by terminating it to VCC_CPU through a resistor.
System Bus Routing scan test will not be functional if these pins are connected together. TESTHI4 must always be pulled up independently from the other TESTHI pins. 6.4.2.9 Topology 9: SKTOCC# Signal The SKTOCC# signal is an output from the processor used as an indication of whether a processor is installed or not. It will be asserted low when a processor is installed in the socket and will float when there is no processor present.
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Mechanical and EMI Design Considerations Mechanical and EMI Design Considerations 7.1 7 Retention Mechanism Placement and Keep-Outs The retention mechanism (RM) requires two keep-out zones, one for the EMI ground pads and another for a limited component height area under the RM as shown in Figure 7-1. Figure 7-2 shows the relationship between the RM mounting holes and pin one of the socket. In addition it also documents the ground pads and keep-out zones.
Mechanical and EMI Design Considerations Figure 7-1.
Mechanical and EMI Design Considerations Figure 7-2.
Mechanical and EMI Design Considerations Intel recommends the following for constructing the mounting holes for the enabled retention mechanism. • All four RM mounting holes must have ground pad rings. • Ground pad annular ring should be no less than 125 mils wide. Try to cover the entire keep-out zone, if possible. See the following illustration for better dimensions. • Place 8-12 vias in the annular ring, which connects the pad to internal ground planes.
Mechanical and EMI Design Considerations 7.2.2 Terminology Electromagnetic Interference (EMI) - electromagnetic radiation from an electrical source that interrupts the normal function of an electronic device. Electromagnetic Compatibility (EMC) - the successful operation of electronic equipment in its intended electromagnetic environment. 7.2.
Mechanical and EMI Design Considerations 7.2.5 EMI Design Considerations The following sections discuss design techniques that may be applied to minimize EMI emissions. Some ideas have been incorporated into Intel-enabled designs (differential clock drivers, selective clock gating, etc.) and some must be implemented by motherboard designers (trace routing, clocking schemes, etc.). 7.2.
Mechanical and EMI Design Considerations Figure 7-5. Impact of Spread Spectrum Clocking on Radiated Emissions ∆ non-SCC SCC (1-δ)fnom fnom ssc.vsd 7.2.7 Differential Clocking Differential clocking requires that the clock generator supply both clock and clock-bar traces. Clock-bar has equal and opposite current as the primary clock and is also 180 degrees out of phase. To maximize the benefit of differential clocking, both clock lines must be routed parallel to each other for their entire length.
Mechanical and EMI Design Considerations Differential clocking can also reduce the amount of noise coupled to other traces, which improves signal quality and reduces EMI. I/O signals are particularly important because they often leave the system chassis (serial and parallel ports, keyboards, mouse, etc.) and will radiate noise that has been induced onto them. A single-ended clock's return path is usually a reference plane, which is shared by other signals/traces.
Mechanical and EMI Design Considerations A true Faraday cage would completely surround the source of radiation and contain all radiated energy. Within the limitations of processor packaging and motherboard assembly it is not possible to create a true Faraday cage around the processor. By using the heatsink and motherboard ground plane as two sides of the cage and a metal frame to enclose the remaining four sides, a reasonable approximation of a Faraday cage can be achieved.
Mechanical and EMI Design Considerations Figure 7-8.
Mechanical and EMI Design Considerations 7.2.10 EMI Test Capabilities FCC regulations in the United States specify the maximum test frequency for products with clocks in excess of 1 GHz is 5 times the highest clock frequency or 40 GHz, which ever is lower. OEMs are advised to inquire into the capabilities of their preferred EMC test lab to ensure they are able to scan up to the required frequency range. History indicates that processor performance and frequency double approximately every two years.
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Processor Power Distribution Guidelines Processor Power Distribution Guidelines Note: 8.1 8 Intel recommends systems utilize modules based on VRM 9.1 DC-DC Converter Design Guidelines for Intel Xeon processor MP and Intel Xeon processor MP with up to 2-MB L3 cache on the 0.13 micron process-based designs. These recommendations are required to meet the current requirements of the processor.
Processor Power Distribution Guidelines “VCC” in this 000, refers to the appropriate processor core VCC, cache supply voltage and Assisted Gunning Transceiver Logic + (AGTL+) supply voltage. With Intel Xeon processors MP and Intel Xeon processor MP with up to 2-MB L3 cache on the 0.13 micron process, the core and cache are on the same silicon and are powered from the same power plane unlike Pentium II Xeon and Pentium III Xeon processors, which required different power planes. “VRM 9.
Processor Power Distribution Guidelines 8.5 System Design 8.5.1 Multiple Voltages The voltage regulator modules that provide VCC supply to processor and have the capability of supplying voltages from +1.1 V to +1.85 V. The VCCA supplies power to the processor core and on-die termination used for AGTL+ bus. Multiple voltages required for Intel Xeon processor MP based systems are VCC_MAX = 1.7 V and SM_VCC = 3.3 V. Similarly, for and Intel Xeon processor MP with up to 2-MB L3 cache on the 0.
Processor Power Distribution Guidelines Figure 8-1. Power Distribution Block Diagram for 4- Way System Motherboard with Voltage Regulator Modules Voltage Regulator Module 1 Processor 1 Voltage Regulator Module 2 Processor 2 Voltage Regulator Module 3 Processor 3 Voltage Regulator Module 4 Processor 4 Power Supply OUTEN VIDx[4:0] VIDx[4:0] PWR OK Output Enable Logic 8.6 Processor Load 8.6.
Processor Power Distribution Guidelines 8.7 Voltage Regulator Intel recommends that the processor power provided by a voltage regulator module (one per processor) meets the specifications as described by the VRM 9.1 DC-DC Converter Design Guidelines. The voltage regulator definition includes Remote-Sense, Current Share and Output Enable features. Voltage regulator designers must provide these features as well as meeting voltage and current requirements set forth in the regulator design guidelines.
Processor Power Distribution Guidelines 8.7.2.4 Voltage Regulator Remote Sense Connection The system board is to include a positive and a negative SENSE input for each voltage regulator module. The round trip trace resistance should not be greater than one ohm. These voltage sense lines draw little current and there should be only a minute voltage drop from the remote sense connection and the voltage regulators.
Processor Power Distribution Guidelines Figure 8-2. Suggested Twelve Layer Stack-Up for Four Processor Systems Gnd plane Layer 0 (1.5 oz.) Pwr plane Layer 1 (1 oz.) Signal Layer 2 Gnd plane Layer 3 (1 oz.) Signal Layer 4 Pwr plane Layer 5 (1 oz.) Gnd plane Layer 6 (1 oz.) Signal Layer 7 Pwr plane 8.8.2 Layer 8 (1 oz.) Signal Layer 9 Gnd plane Layer 10 (1 oz.) Pwr plane Layer 11 (1.5 oz.
Processor Power Distribution Guidelines Where N is the number of VCC/VSS planes. To minimize parasitic layer inductance, it is important to reduce the distance from decoupling capacitors to the processor socket (reducing l) and to use islands for power distribution (increasing w). To reduce h, it is recommended to select the VCC/VSS planes in the layer stack up that are interleaved and have small spacing in between.
Processor Power Distribution Guidelines 8.9 Decoupling Capacitors 8.9.1 Decoupling Technology and Transient Response The inductance of the system due to cables and power planes slows the power supply's ability to respond quickly to a current transient. Decoupling a power plane can be broken into several independent parts. The closer to the load the capacitor is placed, the more inductance that is bypassed. By bypassing the inductance of leads, power planes, etc., less capacitance is required.
Processor Power Distribution Guidelines feasible. Possibly one or both ends of the capacitor can be connected directly to the pin of the processor without the use of via. Even if simulation results look good, these practical suggestions can be used to create an even better decoupling situation where they can be applied in layout. Figure 8-3 illustrates these concepts. Figure 8-3.
Processor Power Distribution Guidelines 8.10 Component Placement and Modeling Intel recommends using simulation to design and verify Intel Xeon processor MP and Intel Xeon processor MP with up to 2-MB L3 cache on the 0.13 micron process-based systems. The models in the following sections can be used to piece together a complete base board spice circuit. The maximum distance between each processor and its voltage regulator module should not be greater than 1.5 inches.
Processor Power Distribution Guidelines inductance and resistance of the power plane between voltage regulator and bulk capacitors and the processor is shown as L1 and L7. A current step from 0 A to 55 A should be applied with a rise time of 308 ns or use the PWL values. Figure 8-5.
Processor Power Distribution Guidelines Table 8-2. Processor Lump Model Component Values Component Description Value Resistance Inductance Capacitance 1206s North/South Five 22 µF MLCC 10 mΩ / 5 1.1 nH / 5 5 * 22 µF 1206s North/South Cavity Five 22 µF MLCC 10 mΩ / 5 1.1 nH / 5 5 * 22 µF 1206s int Interposer MLCC 833 µΩ 45 pH 120 µF DIP Capacitors Package Capacitors 270 µΩ 2.
Processor Power Distribution Guidelines Figure 8-7.
Processor Power Distribution Guidelines Figure 8-8. “Row” Pattern with Voltage Regulator Module Schematic Voltage Regulator Remote Sense L1 Proc A South Side Input Proc A North Side Input L2 L3 Proc B South Side Input Inside OSCONs Outside OSCONs L4 Proc B North Side Input Outside OSCONs Voltage Regulator Module B Voltage Regulator Module A Table 8-3. “Row” Pattern with Voltage Regulator Module Schematic Values Component 8.10.
Processor Power Distribution Guidelines Figure 8-9.
Processor Power Distribution Guidelines Figure 8-10.
Processor Power Distribution Guidelines Table 8-4. “Square” Pattern with Voltage Regulator Module Schematic Values Component 80 Description Values Resistance Inductance Capacitance Outside OSCONs Bulk Capacitors 12 mΩ / 6 3.1 nH / 6 6 × 560 µF Inside OSCONs Bulk Capacitors 12 mΩ / 8 3.
Processor Power Distribution Guidelines Figure 8-11.
Processor Power Distribution Guidelines Figure 8-12.
Processor Power Distribution Guidelines 8.11 Validation Testing The processor VCCSENSE and VSSSENSE pins should be routed to vias. The vias should be as close to the socket pins as possible and should be connected with a low impedance trace. As these signals provide measurement points to verify adherence to the processor's VCC specifications, the vias need to be accessible to measurement equipment. Intel recommends the following guideline when measuring the transients on the processor VCC.
Processor Power Distribution Guidelines A complete analysis of this circuit's currents into and out of the center node, as in Equation 11, will provide the final GTLREF of the circuit. n is the number of IREF inputs supplied by the divider. Equation 8-2. Node Analysis I ( R2 ) = I ( R1 ) + n × I REF Plugging in for the currents and rearranging gives: Equation 8-3. Node Analysis in Terms of Voltage VCC − GTLREF GTLREF − = n × I REF R2 R1 Which leads to: Equation 8-4.
Processor Power Distribution Guidelines Since the target of 2/3 of VCC is 1.133 V, this setting is within 0.7% of the 2/3 point and satisfies the 2% specification. A spreadsheet program allows the reader to easily verify the other corners. Varying over its tolerance range has minimal effect. These values chosen for R1 and R2 have additional benefits: The parallel combination terminates the GTLREF line to 33 Ω. These generally available resistance values reduce resistor cost.
Processor Power Distribution Guidelines Figure 8-15. Filter Topology VCC L R VCCA PLL C Processor VSSA Core C R VCCIOPLL L The function of the filter is two-fold. It protects the PLL from external noise through low-pass attenuation. It also protects the PLL from internal noise through high-pass filtering. In general, the low-pass description forms an adequate description for the filter. For simplicity we are addressing the recommendation for VCCA filter design.
Processor Power Distribution Guidelines Figure 8-16. Filter Specifications 0.2dB 0dB -0.5dB forbidden zone -28dB forbidden zone -34dB DC fpeak 1Hz 1MHz fcore 66MHz high frequency band passband NOTES: 1. Diagram not to scale. 2. No specification for frequencies beyond fcore. 3. Fpeak, if existent, should be less than 0.05 MHz. Other requirements: • Use shielded type inductor to minimize magnetic pickup. • Filter should support at least 30 mA DC current.
Processor Power Distribution Guidelines Table 8-7. Component Recommendations - Capacitor Part Number Value Tolerance ESL ESR Kemet T495D336M016AS 33 µF 20% 2.5 nH 0.225 Ω AVX TPSD336M020S0200 33 µF 20% TBD 0.2 Ω To satisfy damping requirements, total series resistance in the filter (from VCC_CPU to the top plate of the capacitor) must be at least 0.35 Ω. It includes the DCR of the inductor and any resistance (routing or discrete components) between VCC_CPU and capacitor top plate.
Processor Power Distribution Guidelines Figure 8-18. Implementation 2 No Discrete R Trace < 0.02 Ω VCC L1/L2 R-Socket 603 R-Trace C Baseboard v ia that connects f ilter to VCC plane Socket 603 pin Processor interposer "pin" VCCA PLL R-Socket 603 Processor VSSA C R-Socket 603 R-Trace VCCIOPLL L1/L2 In addition, high-frequency decoupling may be required for signal integrity.
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Methodology for Determining Topology and Routing Guidelines Methodology for Determining Topology and Routing Guidelines 9 This section documents the simulation methodology that was used to derive the topology and routing guidelines presented in this design guide. Figure 9-1.
Methodology for Determining Topology and Routing Guidelines The design process should begin with an initial timing analysis and topology definition. Pre-layout analog simulations should be performed. These pre-layout simulations will help define routing rules prior to placement and routing. After routing, the interconnect database can be extracted and post-layout simulations can be performed to refine the timing and signal integrity analysis.
Methodology for Determining Topology and Routing Guidelines 9.1.1.1 Setup Time Figure 9-2 shows the setup timing diagram for a source synchronous bus design. Equation 9-1 gives the total loop equation derived from the timing diagram. Equation 9-1.
Methodology for Determining Topology and Routing Guidelines Figure 9-2. Source Synchronous Timing Diagram for Setup Time CLK Tco(data) DRIVER STROBE DRIVER STROBE Tco(strobe) Tflight(strobe) DRIVER RECEIVER DATA STROBE Tflight(data) 9.1.1.2 RECEIVER STROBE RECEIVER DATA Tsetup Tmargin Hold Time The hold timing diagram for a source synchronous bus design is shown in Figure 9-3. The total loop equation is derived from the hold timing diagram. Equation 9-5.
Methodology for Determining Topology and Routing Guidelines Equation 9-8. Source Synchronous, Hold Margin Tm arg in _ setup = −Tvb,min − Tskew,max − Tsetup Figure 9-3. Source Synchronous Timing Diagram for Hold Time CLK Tco(data) DRIVER STROBE DRIVER STROBE Tco(strobe) Tflight(strobe) DRIVER RECEIVER DATA STROBE Tflight(data) 9.1.
Methodology for Determining Topology and Routing Guidelines Figure 9-4. Circuit Used to Develop the Common Clock Timing Equations CLK T drv_clk (A) T drv_clk (B) T prop_clk (A) T T F R O M C O R E CLK Q D A T drv Processor 9.1.2.1 (B) flight CLK D prop_clk Q TO B T C O R E setup Chipset Setup Margin Figure 9-5 shows the setup timing diagram that was used to develop the final timing equations for the setup margin. Equation 9-9.
Methodology for Determining Topology and Routing Guidelines Figure 9-5. Timing Diagram Used to Determine the Common Clock Setup Timing Equations T CLK CLK In T CLK drv_clk (A) CLK Out A T CLK cycle prop_clk (A) A T drv T DATA A T DATA (B) prop B T CLK drv_clk setup CLK Out B T CLK prop_clk (B) B T jitter Tsetup_margin Equation 9-8 can be simplified by defining the clock delay and the clock skew as shown in Equation 9-9 and Equation 9-10.
Methodology for Determining Topology and Routing Guidelines 9.1.2.2 Hold Margin Figure 9-6 illustrates the timing diagram that was used to develop the final timing equations. Equation 9-13. Common Clock Hold Margin Tm arg in _ hold = Tdrv + T prop − Thold − Tskew _ hold Figure 9-6.
Methodology for Determining Topology and Routing Guidelines • Each timing component has an owner and revision date • Rising and falling edges should be tracked separately 9.2 Simulation Methodology This sections outlines the simulation methodology used to determine the topology and routing guidelines. 9.2.1 Design Optimization The layout for a high-speed bus design can be complex.
Methodology for Determining Topology and Routing Guidelines Table 9-1. System Variables to Consider for Sensitivity Analysis System Variable 9.2.4 Impact on Timings and/or Signal Integrity Trace/stub lengths High Trace impedance variations High Buffer impedance variations High Buffer capacitance variations Moderate Er variations Low (variation is usually small for stripline.
Methodology for Determining Topology and Routing Guidelines An edge is defined to be linear if it exhibits a linear shape between VIH and VIL. Figure 9-7 depicts a linear edge. Figure 9-9 depicts a nonlinear edge. For non-clock and non-strobe signals, the signal seen at the receiver should be linear between VIH and VIL. On a case-by-case basis where it can be shown that the timing can be met with no potential data corruption, it may not be necessary for the signal to be linear between VIH and VIL. 9.2.4.
Methodology for Determining Topology and Routing Guidelines Figure 9-7.
Methodology for Determining Topology and Routing Guidelines Figure 9-9. Traditional Method of Calculating Flight Time Assuming a Nonlinear Edge from VIL Through VIH at the Receiver Extrapolate the Vih crossing at the minimum edge rate back to the switching threshold Reference driver into reference load min edge rate Vih Threshold Ta Tb(extrapolated) Vil Signal at at receiver Flight Time = Tb(extrapolated)-Ta (Assuming a non-linear edge throughVil and Vih) Figure 9-10.
Methodology for Determining Topology and Routing Guidelines 9.2.6.1 Parameter Sweeps The bulk of the sensitivity analysis consists of parameter sweeps. During a parameter sweep all parameters are held constant except for one or two. The system performance is then observed as the specific variables are being swept. Surface plots can be generated from the results of the parameter sweep.
Methodology for Determining Topology and Routing Guidelines Figure 9-11. Example of Sweeps Used to Evaluate the Length Limits of Trace L2 and L3 Min Tflight = 1.0 ns Undershoot [V] Tflight [ns] 3 2 1 0 0 2 L3 3 6 L2 [in] 9 12 0 Spec = - 0.7 V 0.3 0.2 0.1 2 0.0 0 3 L2 [in] [in] 6 9 1 2 L3 [in] 0 Tflight [ns] Max Tflight = 2.45 ns 2 3 2 1 L3 [in] 1 0 0 2 3 6 L2 [in] 9 0 L3 [in] 0 2 12 4 L2 [in] 6 0 Figure 9-12.
Methodology for Determining Topology and Routing Guidelines Figure 9-13. Results of Targeted Monte Carlo (TMC) Analysis and the Resultant Phase 2 Solution Space for Variables L2 and L3 Pass Fail 2 L3 1 [in] New Solution Space 0 9.2.6.2 2 L2 [in] 4 6 0 Final Solution Space The final solution space will be referred to as the “phase 3 solution space.” This phase incorporates effects that are too computationally demanding to easily include in the phase 1 or phase 2 solution spaces.
System Theory System Theory 10 This section provides in-depth information about signal technology and system signal interference. 10.1 AGTL+ Logic AGTL+ is the electrical system bus technology. It is an incident wave switching, open-drain bus with integrated pull-up resistors (p-channel FETs) that provide both the high logic level and the termination. The end agents on the system bus will always have their termination on.
System Theory then the phase 2 solution space is acceptable. If timing violations do occur then steps should be taken to minimize reflections on the bus, which will reduce the ISI. Typically, the best way to limit reflections is to reduce impedance variations and minimize discontinuities (e.g., by shortening stubs and connectors, matching impedance between packages and motherboard traces, etc.).
System Theory 10.3 Crosstalk Crosstalk is caused through capacitive and inductive coupling between networks. Crosstalk can be backward or forward. Backward crosstalk creates an induced signal on a victim network that travels in a direction opposite that of the aggressor's signal. Forward crosstalk creates a signal that travels in the same direction as the aggressor's signal. On an AGTL+ bus a driver on the aggressor network is not necessarily at the end of the network.
System Theory Figure 10-4. Transmission Line Geometry of Microstrip and Stripline SIGNAL LINES SIGNAL LINES w Sp DIELECTRIC,εr DIELECTRIC,εr t AC GROUND PLANE A. MICROSTRIP B. STRIPLINE Backward crosstalk is present in both stripline and microstrip geometry. The backward-coupled amplitude is proportional to the backward crosstalk coefficient, the aggressor's signal amplitude, and the coupled length of the network.
System Theory To minimize crosstalk: • Route adjacent trace layers in different directions (orthogonal preferred) to minimize the forward and backward crosstalk that can occur from parallel traces on adjacent layers. This reduces the source of crosstalk. • Maximize the spacing between traces. Where traces have to be close and parallel to one another, the distance that they are close together should be minimized, and the distance between sections that have close spacing should be maximized.
System Theory Crosstalk will be incorporated in the processor system bus analysis methodology in two ways. Initially, for the sensitivity analysis sweeps, the SLEM model will be utilized. This method allows quick computation and is well-suited to the bulk of the sensitivity analysis. After the initial solution space is found using the SLEM method to account for crosstalk, fully coupled simulations will be performed as a final check. 10.3.
System Theory Figure 10-5. Cross-Section of a 3-Conductor System Used to Create a SLEM Model A B C FR4 ABC Even mode = ABC Odd mode = Using equations Equation 10-2 through Equation 10-5 a 3-conductor system can be replaced with a single transmission line model. The odd and even modes will be the worst-case patterns for mode dependent signal integrity and velocity differences. The SLEM method has some drawbacks. The SLEM method will only model the impedance and velocity differences due to crosstalk.
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Design Checklist 11 Design Checklist Use the following checklists as a final check to ensure the motherboard incorporates solid design practices. These lists are only a reference. For correct operation, all of the design guidelines within this document must be followed. The following tables are quick checklists for platform design. They are created to provide a reminder for key design points or easily forgotten items.
Design Checklist Table 11-1. Processor Connection Checklist (Sheet 2 of 5) Processor Pin 116 Signal Type Pin Connection Section No. BNR# Common Clock Connect to all system bus agents, and the chipset if supported. Wired-OR signal. All wired-OR signals should have AC termination to VCC_CPU at the middle agents (see Figure 6-7). The termination should be located as close as possible to the processor pins with no stubs. BPRI# Common Clock Connect to all system bus agents. Section 6.4.
Design Checklist Table 11-1. Processor Connection Checklist (Sheet 3 of 5) Processor Pin Signal Type Pin Connection Section No. DSTBN[3:0]# Source synch AGTL+ Connect to all system bus agents. Balance signal lengths within strobe group. Maintain 25 mil spacing from other signals. Section 6.4.1 DSTBP[3:0]# Source synch AGTL+ Connect to all system bus agents. Balance signal lengths within strobe group. Maintain 25 mil spacing from other signals. Section 6.4.
Design Checklist Table 11-1. Processor Connection Checklist (Sheet 4 of 5) Processor Pin Signal Type Section No. ODTEN Power/Other Option 1 (preferred): Enable ODT (on-die termination) on Processor 0 (end processor) by pulling up to VCC_CPU with a resistor that falls within the range of 50 Ω ± 20%. Disable ODT for middle agent processors (Processors 1-3) by pulling down to VSS with a resistor that falls in the range of 50 Ω ± 20%.
Design Checklist Table 11-1. Processor Connection Checklist (Sheet 5 of 5) Processor Pin Signal Type Pin Connection Section No. SM_TS_A[1:0] 1 Power/Other Pull-up to VCC_SMBus with < 1 kΩ resistors to set bit high. Pull-down to VSS through < 1 kΩ resistors to set bit low. Use these address bits to set a unique SMBus address for the processor thermal sensing device. See the processor datasheet for more details. SM_VCC Power/Other Must be connected to 3.
