VRM 9.1 DC-DC Converter Design Guidelines

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Table Of Contents

VRM 9.1 DC-DC Converter

Design Guidelines

March 2005

Document Number: 306826-001

Summary of content (24 pages)

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VRM 9.
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
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Contents 1 Electrical Specifications...................................................................................................... 7 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 Module Layout Guidelines................................................................................................ 19 2.1 2.2 3 Output Requirements ...........................................................................................................7 1.1.1 Voltage and Current - REQUIRED ........................
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Figures 2-1 VRM 9.1 Regulation Requirement for Intel® Xeon™ Processor (VID = 1.7 V) ................... 9 VRM 9.1 Regulation Requirement for Intel® Xeon™ Processor with 512 KByte L2 Cache (VID = 1.5 V) ..................................................................................... 9 VRM 9.1 Regulation Requirement for 64-bit Intel® Xeon™ Processor MP Cache (VID = 1.125 V) ...................................................................................................... 10 VRM 9.
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Revision History Document Number Revision Number 306826 001 Description • Initial release of this document Date March 2005 NOTE: Not all revisions may be published. Applications and Terminology This document defines one or more DC-to-DC converters to meet the power requirements of computer systems using Intel microprocessors. It does not attempt to define a specific voltage regulator module (VRM) implementation.
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VRM 9.
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1 Electrical Specifications 1.1 Output Requirements 1.1.1 Voltage and Current - REQUIRED The VRM 9.1 Voltage Regulator Module is a DC-DC converter that supplies the correct voltage and current to a single processor, or when paralleled with other like converters, supplies the required voltage and current to multiple processors, whose Vcc and Vss or VCACHE and Vss are also connected in parallel.
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Electrical Specifications 1.1.3 Output Voltage Tolerance - REQUIRED The remote sense lines of each VRM should be routed on the system board to a remote sense point at the geometric center of the processors, where they are connected to each other and to the Vcc and Vss planes for Intel Xeon processors using the 603 socket.
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Electrical Specifications Figure 1-1. VRM 9.1 Regulation Requirement for Intel® Xeon™ Processor (VID = 1.7 V) 1.70 V 1.68 V 1.66 V VvrmMAX VvrmMIN 1.64 V 1.62 V 1.60 V 1.58 V 0A 20 A 40 A 60 A 80 A 100 A Figure 1-2. VRM 9.1 Regulation Requirement for Intel® Xeon™ Processor with 512 KByte L2 Cache (VID = 1.5 V) 1.52 V 1.50 V 1.48 V VvrmMAX VvrmMIN 1.46 V 1.44 V 1.42 V 1.40 V 1.38 V 0A 20 A VRM 9.
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Electrical Specifications Figure 1-3. VRM 9.1 Regulation Requirement for 64-bit Intel® Xeon™ Processor MP Cache (VID = 1.125 V) Vcc (V) 1.140 1.120 VvrmMAX 1.100 VvrmMIN 1.080 1.060 1.040 1.020 1.000 0 20 40 60 80 100 Icc (A) Figure 1-4. VRM 9.1 Regulation Requirement for 64-bit Intel® Xeon™ Processor MP Cache (VID = 1.1275 V) Vcc (V) 1.300 1.280 VvrmMAX 1.260 VvrmMIN 1.240 1.220 1.200 1.180 1.160 0 20 40 60 80 100 Icc (A) 10 VRM 9.
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Electrical Specifications Table 1-2. Intel® Xeon™ Processor VRM Regulation Requirements Intel® Xeon™ Processor with 512 KByte L2 Cache (VID = 1.5V) Remote Sense Voltage Intel® Xeon™ Processor (VID = 1.7V) Remote Sense Voltage Intel® Xeon™ Processor with 512 KByte L2 Cache (VID = 1.5V) Remote Sense Voltage Intel® Xeon™ Processor (VID = 1.7V) Remote Sense Voltage VvrmMAX VvrmMin VvrmMAX VvrmMin VvrmMAX VvrmMin VvrmMAX VvrmMin 0 1.500 1.470 1.700 1.666 42 1.460 1.430 1.660 1.626 2 1.
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Electrical Specifications Table 1-3. 64-bit Intel® Xeon™ Processor MP, VRM Regulation Requirements 64-bit Intel® Xeon™ Processor Cache (VID = 1.125V) Remote Sense Voltage 64-bit Intel® Xeon™ Processor Cache (VID = 1.275V) Remote Sense Voltage VvrmMAX VvrmMin VvrmMAX VvrmMin 0 1.125 1.103 1.275 1.250 2 1.123 1.101 1.273 4 1.121 1.099 6 1.119 8 1.117 10 VRM Output Current, Amperes 64-bit Intel® Xeon™ Processor Cache (VID = 1.
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Electrical Specifications 1.1.5 Turn-on Response Time - EXPECTED The output voltage should reach its specified range within 15 ms after the input power reaches its minimum voltage and the OUTEN signal is asserted. 1.1.6 Overshoot and Undershoot at Turn-On or Turn-Off - REQUIRED Overshoot must be less than 2% above the Voltage Identification (VID) code. No negative voltage below −0.1 V may be present at the output at any time. 1.1.
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Electrical Specifications 1.1.8.3 Negative Current Limit - EXPECTED Because the output of the VRM will be connected in parallel with other voltage sources (other VRMs) the VRM should incorporate negative current limiting or equivalent functionality to protect the VRM from current from external voltage sources. 1.1.8.4 Current Sharing Methodology - PROPOSED The method used to accomplish current sharing will depend upon the VRM design.
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Electrical Specifications When disabled, the VRM should sink less than 100 mA from the 12 V Input and less than 1 A from shared VRMs that remain on. 1.3.2 Voltage Identification—(VID[4:0]) - REQUIRED The VRM must accept five lines to set the nominal (maximum) voltage as defined by the table below. Five processor package pins will have a high-low pattern corresponding to the voltage required by the individual processor. When all five VID inputs are high (11111), the VRM should disable its output.
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Electrical Specifications 1.5 Power Good Output (PWRGD) - REQUIRED The VRM must provide an open collector or equivalent Power Good signal consistent with TTL DC levels. This signal should transition to the open (>100 kΩ) state within 10 ms of the output voltage stabilizing within the range specified in Section 1.1.1.
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Electrical Specifications 1.8 Isolation - PROPOSED Isolation from input to output is optional. A transformer-based topology may have advantages over a non-isolated buck converter: Over-voltage due to a shorted FET is eliminated, and duty cycles can be optimized to simplify control or improve efficiency. A common ground between input and output is required with an isolated topology. 1.9 Fault Protection These features are built into the VRM to prevent damage to the VRM or the circuits it powers. 1.9.
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Electrical Specifications 1.9.4 Reset After Shutdown - PROPOSED If the VRM goes into a shutdown state due to a fault condition on its output (not an internal failure) it should return to normal operation after the fault has been removed, or after the fault has been removed and power has been cycled off and on. § 18 VRM 9.
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2 Module Layout Guidelines 2.1 VRM Connector - EXPECTED The VRM interface with the system board is a 100 mil-pitch, 62-pin edge connector, with an overall 3.95” length. The connector uses a retention clip or side latches to hold the VRM in place. The connector has a maximum rated temperature of 90°C, based on 2-oz. minimum copper lands on the VRM PCB and 19 contact pairs carrying 4.26 A each. Table 2-1. Connector Part Numbers and Descriptions VRM 9.0 VRM 9.1 VRM 9.
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Module Layout Guidelines Table 2-2.
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7 .6 2 [.3 0 0 ] VRM 9.1 DC-DC Converter Design Guidelines 1 .2 7 ± .0 5 [.0 5 0 ± .0 0 2 ] 11 SPAC ES @ 2 .5 4 [.1 0 0 ] 3 1 .5 7 ± .0 5 [1 .2 4 3 ± .0 0 2 ] T Y P E A C H S ID E Ø 1 .0 2 ± .0 8 [.0 4 0 ± .0 0 3 ] 61 PL 4 9 .3 5 ± .0 5 [1 .9 4 3 ± .0 0 2 ] 18 SPACES @ 2 .5 4 = 7 6 .2 0 [3 .0 0 0 ] [.1 0 0 ] 1 .2 7 [.0 5 0 ] T Y P 30 S PAC ES @ 1 .0 7 ± .0 5 [.0 4 2 ± .0 0 2 ] 9 6 .5 2 [3 .8 0 ] 2 .5 4 [.1 0 0 ] 5 .0 8 [.2 0 0 ] 5 .0 8 [.2 0 0 ] M IN 5 8 .4 2 [2 .3 0 ] 1 0 .8 0 [.
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Module Layout Guidelines 22 VRM 9.
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3 Environmental Conditions The VRM design, including materials, should be consistent with the manufacture of units that meet the environmental requirements specified below. 3.1 Operating Temperature - PROPOSED The VRM should meet all electrical requirements when operated over an ambient temperature of 0oC to +60oC at full load with a minimum airflow of 400 LFM.
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Environmental Conditions 3.5 Altitude - PROPOSED • 10 k feet – operating • 50 k feet – non-operating 3.6 Electrostatic Discharge - PROPOSED Testing should be in accordance with IEC 61000-4-2. Operating – 15 kV initialization level. The direct ESD event should cause no out-of-regulation conditions – including overshoot, undershoot and nuisance trips of over-voltage protection, overcurrent protection or remote shutdown circuitry. Non-operating - 25 kV initialization level.