64-bit Intel® Xeon® Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Specification Update August 2009 Notice: The 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache versions) may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.
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—Intel ® Xeon™ Processor with 800 MHz System Bus Contents Preface ...................................................................................................................... 6 Identification Information .........................................................................................7 Summary Table of Changes ..................................................................................... 13 Errata .....................................................................................
Intel® Xeon™ Processor with 800 MHz System Bus— Revision History Version Description Date -001 • Initial release of the document. July 2004 -002 • Removed erratum P18 and renumbered existing errata. July 2004 -003 • Added errata S32-S35. Renamed errata numbering from P to S. August 2004 • Removed erratum S29 and renumbered existing errata. • Added errata S35-S65. • Added E0 step processor information to Table 2-1, “Identification Information”.
—Intel ® Xeon™ Processor with 800 MHz System Bus -022 • Added erratum S93. June 2006 -023 • Added erratum S94. Updated Summary of Changes Table. August 2008 • Updated Summary of Changes table. -024 • Added Documentation Change S1. August 2009 • Updated links to related documentation throughout this document.
Intel® Xeon™ Processor with 800 MHz System Bus— 1 Preface This document is an update to the specifications contained in the following documents: 1. 64-bit Intel® Xeon® Processor with 2 MB L2 Cache Datasheet (Document Number 306249) Link: http://www.intel.com/Assets/PDF/datasheet/306249.pdf 2. Low Voltage Intel® Xeon® Processor with 800 MHz System Bus Datasheet (Document Number 302355) Link: http://www.intel.com/design/intarch/datashts/304097.htm 3.
—Intel ® Xeon™ Processor with 800 MHz System Bus 2 Identification Information 2.1 64-bit Intel® Xeon® Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Package Markings (604-pin FC-mPGA4 Package) Figure 2-1. Top-Side Processor Marking Example Intel Confidential 2D Matrix Includes ATPO and Serial Number (front end mark) Pin 1 Indicator Figure 2-2.
Intel® Xeon™ Processor with 800 MHz System Bus— The 64-bit Intel® Xeon® Processor with 800 MHz System Bus (1 MB and 2 MB L2 cache versions) can be identified by the following values: Table 2-1. Identification Information Family 1 Model2 Brand ID3 1111b 0011b 0000b 1111b 0100b 0000b 1. 2. 3.
—Intel ® Xeon™ Processor with 800 MHz System Bus Table 2-2. 64-bit Intel® Xeon® Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Identification Information (Sheet 2 of 3) S-Spec Core Stepping CPUI D Core Freq (GHz) Data Bus Freq (MHz) L2 Cache Size Processor Package Revision E-0 0F41h 2.80 800 1 MB 01 SL7PD SL7TB SL7PE E-0 0F41h 3 800 1 MB 01 SL7TC SL7PF E-0 0F41h 3.20 800 1 MB 01 SL7TD SL7PG E-0 0F41h 3.
Intel® Xeon™ Processor with 800 MHz System Bus— Table 2-2. 64-bit Intel® Xeon® Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Identification Information (Sheet 3 of 3) S-Spec Core Stepping CPUI D Core Freq (GHz) Data Bus Freq (MHz) L2 Cache Size Processor Package Revision SL7ZD N-0 0F43h 3.40 800 2 MB 01 604-pin micro-PGA with 42.5 x 42.5 mm FC-PGA4 package 2, 3, 4, 6 SL7ZE N-0 0F43h 3.20 800 2 MB 01 604-pin micro-PGA with 42.5 x 42.
—Intel ® Xeon™ Processor with 800 MHz System Bus 2.2 Mixed Steppings in DP Systems Intel Corporation fully supports mixed steppings of the 64-bit Intel Xeon processor with 800 MHz system bus as well as mixed steppings of the 64-bit Intel Xeon processor with 2 MB L2 cache. The following list and processor matrix describes the requirements to support mixed steppings: • Mixed steppings are only supported with processors that have identical family numbers as indicated by the CPUID instruction.
Intel® Xeon™ Processor with 800 MHz System Bus— Table 2-3. DP Platform Population Matrix for the 64-bit Intel® Xeon® Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) FC-PGA4 Package Processor Signature / Core Stepping 0F34h / D-0 0F41h / E-0 0F49h / G-1 0F43h / N-0 0F4Ah / R-0 0F43h / N-0 X X X NI NI 0F4Ah / R-0 X X X NI NI NOTES: 1. X = Mixing processors of different steppings is not supported. This stepping/frequency is not supported in DP. 2.
—Intel ® Xeon™ Processor with 800 MHz System Bus Summary Table of Changes 3 The following table indicates the Errata, Documentation Changes, Specification Clarifications, or Specification Changes that apply to Intel processors. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or specification changes as noted. This table uses the following notation: 3.
Intel® Xeon™ Processor with 800 MHz System Bus— R = Intel® Pentium® 4 processor on 90 nm process S = 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache versions) T = Mobile Intel® Pentium® 4 processor-M U = 64-bit Intel® Xeon® processor MP with up to 8MB L3 cache V = Mobile Intel® Celeron® processor on .
—Intel ® Xeon™ Processor with 800 MHz System Bus AAD = Intel® Core™2 Extreme Processor QX9775? AAE = Intel® Atom™ processor Z5xx series AAF = Intel® Atom™ processor 200 series AAG = Intel® Atom™ processor N series AAI = Intel® Xeon® Processor 7400 Series AAJ = Intel® Core™ i7 and Intel® Core™ i7 Extreme Edition AAK = Intel® Xeon® Processor 5500 Series AAL = Intel® Pentium® Dual-Core Processor E5000 Series AAM = Intel® Xeon® Processor 3500 Series The Specification Updates for the Pen
Intel® Xeon™ Processor with 800 MHz System Bus— 3.2 Errata (Sheet 2 of 6) D-0/ 0F34 h E-0/ 0F41 h G-1/ 0F49 h N-0/ 0F43 h R-0/ 0F4A h 15 X X X X X No Fix Processor may hang under certain frequencies and 12.
—Intel ® Xeon™ Processor with 800 MHz System Bus 3.
Intel® Xeon™ Processor with 800 MHz System Bus— 3.2 No.
—Intel ® Xeon™ Processor with 800 MHz System Bus 3.2 No.
Intel® Xeon™ Processor with 800 MHz System Bus— 3.2 No.
—Intel ® Xeon™ Processor with 800 MHz System Bus 3.3 Specification Changes No. SPECIFICATION CHANGES None for this revision of the Specification Update. 3.4 Specification Clarifications No. SPECIFICATION CLARIFICATIONS None for this revision of the Specification Update. 3.5 Documentation Changes No.
Intel® Xeon™ Processor with 800 MHz System Bus— 4 Errata S1 Transaction is not retired after BINIT# Problem: If the first transaction of a locked sequence receives a HITM# and DEFER# during the snoop phase it should be retried and the locked sequence restarted. However, if BINIT# is also asserted during this transaction, the transaction will not be retried. Implication: When this erratum occurs, locked transactions will not be retried. Workaround:None at this time.
—Intel ® Xeon™ Processor with 800 MHz System Bus Workaround:Page directories and page tables in UC memory space must point to system memory that exists. Status: For the steppings affected, see the Summary Table of Changes.
Intel® Xeon™ Processor with 800 MHz System Bus— error, the processor will attempt to correct the correctable error but cannot proceed due to the uncorrectable error. When this occurs the processor will hang. • When an L1 cache parity error occurs, the cache controller logic should write the physical address of the data memory location that produced that error into the IA32_MC1_ADDR REGISTER (MC1_ADDR).
—Intel ® Xeon™ Processor with 800 MHz System Bus • The processor should only log the address for L1 parity errors in the IA32_MC1_Status register if a valid address is available. If a valid address is not available, the Address Valid bit in the IA32_MC1_Status register should not be set.
Intel® Xeon™ Processor with 800 MHz System Bus— Status: For the steppings affected, see the Summary Table of Changes. S7 Cascading of performance counters does not work correctly when forced overflow is enabled Problem: The performance counters are organized into pairs. When the CASCADE bit of the Counter Configuration Control Register (CCCR) is set, a counter that overflows will continue to count in the other counter of the pair.
—Intel ® Xeon™ Processor with 800 MHz System Bus Workaround:Remove the software’s dependency on #AC having precedence over #PF. Alternately, correct the page fault in the page fault handler and then restart the faulting instruction. Status: For the steppings affected, see the Summary Table of Changes.
Intel® Xeon™ Processor with 800 MHz System Bus— S14 Shutdown and IERR# may result due to a machine check exception on a Hyper-Threading Technology enabled processor Problem: When a MCE occurs due to an internal error, both logical processors on a Hyper-Threading (HT) Technology enabled processor normally vector to the MCE handler. However, if one of the logical processors is in the “Wait for SIPI” state, that logical processor will not have a MCE handler and will shut down and assert IERR#.
—Intel ® Xeon™ Processor with 800 MHz System Bus uncacheable write to the task priority register (TPR) that lowers the APIC priority the interrupt masking operation may take effect before the actual priority has been lowered. This may cause interrupts whose priority is lower than the initial TPR but higher than the final TPR to not be serviced until the interrupt flag is finally cleared (for example STI).
Intel® Xeon™ Processor with 800 MHz System Bus— S21 Bus locks and SMC detection may cause the processor to temporarily hang Problem: The processor may temporarily hang in an HT Technology enabled system, if one logical processor executes a synchronization loop that includes one or more bus locks and is waiting for release by the other logical processor.
—Intel ® Xeon™ Processor with 800 MHz System Bus Workaround:None at this time. Status: For the steppings affected, see the Summary Table of Changes.
Intel® Xeon™ Processor with 800 MHz System Bus— Workaround:BIOS should initialize the second thread of the processor supporting HT Technology prior to STPCLK# assertion. Status: For the steppings affected, see the Summary Table of Changes.
—Intel ® Xeon™ Processor with 800 MHz System Bus S32 Processor provides a 4-byte store unlock after an 8-byte load lock Problem: When the processor is in the Page Address Extension (PAE) mode and detects the need to set the Access and/or Dirty bits in the page directory or page table entries, the processor sends an 8 byte load lock onto the system bus. A subsequent 8 byte store unlock is expected, but instead a 4 byte store unlock occurs.
Intel® Xeon™ Processor with 800 MHz System Bus— S37 MOV CR3 performs incorrect reserved bit checking when in PAE paging Problem: The MOV CR3 instruction should perform reserved bit checking on the upper unimplemented address bits. This checking range should match the address width reported by CPUID instruction 0x8000008. This erratum applies whenever PAE is enabled. Implication: Software that sets the upper address bits on a MOV CR3 instruction and expects a fault may fail.
—Intel ® Xeon™ Processor with 800 MHz System Bus S41 Writing the Echo TPR disable bit in IA32_MISC_ENABLE may cause a #GP fault Problem: Writing a ‘1’ to the Echo TPR disable bit (bit 23) in IA32_MISC_ENABLE may incorrectly cause a #GP fault. Implication: A #GP fault may occur if the bit is set to a ‘1’. Workaround:It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Table of Changes.
Intel® Xeon™ Processor with 800 MHz System Bus— Implication: Operating systems or drivers that reference a selector in non-canonical space may experience an unexpected #GP fault. Intel has not observed this erratum with any commercially available software. Workaround:None at this time. Status: For the steppings affected, see the Summary Table of Changes.
—Intel ® Xeon™ Processor with 800 MHz System Bus Status: For the steppings affected, see the Summary Table of Changes. S50 Processor may fault when the upper 8 bytes of segment selector is loaded from a far jump through a call gate via the Local Descriptor Table Problem: In IA-32e mode of the Intel EM64T processor, control transfers through a call gate via the Local Descriptor Table (LDT) that uses a 16-byte descriptor, the upper 8-byte access may wrap and access an incorrect descriptor in the LDT.
Intel® Xeon™ Processor with 800 MHz System Bus— Workaround:None identified. Status: For the steppings affected, see the Summary Table of Changes.
—Intel ® Xeon™ Processor with 800 MHz System Bus Status: For the steppings affected, see the Summary Table of Changes. S58 Enhanced halt state (C1E) voltage transition may affect a system’s power management in a Hyper-Threading Technology enabled processor Problem: In an HT Technology enabled system, the second logical Processor may fail to wake up from “Wait-for-SIPI” state during a C1E voltage transition.
Intel® Xeon™ Processor with 800 MHz System Bus— Implication: No impact to properly written code since both types of faults will be generated but in the opposite order. Workaround:It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Table of Changes.
—Intel ® Xeon™ Processor with 800 MHz System Bus Workaround:Ensure that BIOS provides only valid physical address ranges to the operating system. Status: For the steppings affected, see the Summary Table of Changes.
Intel® Xeon™ Processor with 800 MHz System Bus— Status: For the steppings affected, see the Summary Table of Changes. S71 Branch Trace Store (BTS) and Precise Event-Based Sampling (PEBS) may update memory outside the BTS/PEBS buffer Problem: If the BTS/PEBS buffer is defined such that: 1.The difference between the BTS/PEBS buffer base and the BTS/PEBS absolute maximum is not an integer multiple of the corresponding record sizes, 2.
—Intel ® Xeon™ Processor with 800 MHz System Bus S73 The base of an LDT (Local Descriptor Table) register may be non-zero on a processor supporting Intel® Extended Memory 64 Technology (Intel® EM64T) Problem: In IA-32e mode of an Intel EM64T-enabled processor, the base of an LDT register may be non-zero. Implication: Due to this erratum, Intel EM64T-enabled systems may encounter unexpected behavior when accessing an LDT register using the null selector.
Intel® Xeon™ Processor with 800 MHz System Bus— b.Update the associated cache line state information to shared state on the originating bus (rather than invalid state) in reaction to a BWIL or BLW. Status: For the steppings affected, see the Summary Table of Changes.
—Intel ® Xeon™ Processor with 800 MHz System Bus S79 An REP LODSB or an REP LODSD or an REP LODSQ instruction with RCX >= 2^32 may cause a system hang on processors supporting Intel® Extended Memory 64 Technology (Intel® EM64T) Problem: In IA-32e mode using Intel EM64T-enabled processors, a REP LOSDB or an REP LODSD or an REP LODSQ instruction executed with the register RCX >= 2^32 may fail to complete execution causing a system hang.
Intel® Xeon™ Processor with 800 MHz System Bus— •If an instruction fetch wraps around the 4G boundary in Compatibility mode, the 64-bit value of LIP in the BTS memory record will be incorrect (upper 32 bits will be set to FFFFFFFFh when they should be 0). •If a PEBS event occurs on an instruction whose last byte is at memory location FFFFFFFFh, the 64-bit value of LIP in the PEBS record will be incorrect (upper 32 bits will be set to FFFFFFFFh when they should be 0).
—Intel ® Xeon™ Processor with 800 MHz System Bus Status: For the steppings affected, see the Summary Table of Changes. S86 Front Side Bus machine checks may be reported as a result of on-going transactions during warm reset Problem: Processor Front Side Bus (FSB) protocol/signal integrity machine checks may be reported if the transactions are initiated or in-progress during a warm reset. A warm reset is where the chipset asserts RESET# when the system is running.
Intel® Xeon™ Processor with 800 MHz System Bus— instructions are supported and able to be executed without an Invalid Opcode exception. Implication: The CPUID feature flag incorrectly reports LAHF/SAHF instructions as unavailable in 64-bit mode, though they can be executed normally. Workaround:It is possible for BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Table of Changes.
—Intel ® Xeon™ Processor with 800 MHz System Bus S93 The IA32_MC0_STATUS/ IA32_MC1_STATUS Overflow Bit is not set when multiple un-correctable machine check errors occur at the same time. Problem: When two MC0/MC1 enabled un-correctable machine check errors are detected in the same internal clock cycle, the highest priority error will be logged in IA32_MC0_STATUS / IA32_MC1_STATUS register, but the overflow bit may not be set.
Intel® Xeon™ Processor with 800 MHz System Bus— 5 Specification Changes There are no new Specification Changes for this revision of the Intel® Xeon™ Processor with 800 MHz System Bus. The Specification Changes listed in this section apply to the following documents: 1. 64-bit Intel® Xeon® Processor with 2 MB L2 Cache Datasheet (Document Number 306249) Link: http://www.intel.com/Assets/PDF/datasheet/306249.pdf 2.
—Intel ® Xeon™ Processor with 800 MHz System Bus Specification Clarifications 6 There are no new Specification Clarifications for this revision of the Intel® Xeon™ Processor with 800 MHz System Bus. The Specification Clarifications listed in this section apply to the following documents: 1. 64-bit Intel® Xeon® Processor with 2 MB L2 Cache Datasheet (Document Number 306249) Link: http://developer.intel.com/design/xeon/datashts/306249.htm 2.
Intel® Xeon™ Processor with 800 MHz System Bus— 7 Documentation Changes Note: Documentation changes for IA-32 Intel® Architecture Software Developer’s Manual, Volumes 1, 2A, 2B, and 3 will be posted in the separate document IA32 Intel® Architecture Software Developer’s Manual Documentation Changes. Follow the link below to become familiar with this file. http://www.intel.com/design/processor/specupdt/252046.
—Intel ® Xeon™ Processor with 800 MHz System Bus August 2009 Order Number: 302402-024 64-bit Intel® Xeon® Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Specification Update 53
