Intel® Xeon™ Processor with 512 KB L2 Cache System Compatibility Guidelines Order Number: 298645-001 January 2002
Intel® Xeon™ Processor with 512 KB L2 Cache System Compatibility Guidelines Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
Intel® Xeon™ Processor with 512 KB L2 Cache System Compatibility Guidelines Table of Contents 1.0 Revision History .................................................................................. 4 2.0 Introduction ......................................................................................... 5 1.1 Audience.......................................................................................... 5 1.2 References ..................................................................................
Intel® Xeon™ Processor with 512 KB L2 Cache System Compatibility Guidelines 1.
Intel® Xeon™ Processor with 512 KB L2 Cache System Compatibility Guidelines 2.0 Introduction This document describes the required changes to Intel® Xeon™ processor-based platforms in order to provide Intel® Xeon™ processor with 512 KB L2 cache compatibility. The information in this document should be used in conjunction with specifications presented in the latest version of the Intel® Xeon™ Processor with 512 KB L2 Cache at 1.80 GHz, 2 GHz, and 2.20 GHz Datasheet and Intel® Xeon™ Processor at 1.40 GHz, 1.
Intel® Xeon™ Processor with 512 KB L2 Cache System Compatibility Guidelines 3.0 Compatibility Implementing the changes outlined in this document will help assure that an Intel® Xeon™ processor-based system design will be compatible with the Intel Xeon processor with 512 KB L2 cache. Compatibility is likely to be ultimately limited by the ability of the system to supply the required current and to adequately cool the processor. 4.0 SM_VCC SM_VCC must be connected to the system 3.
Intel® Xeon™ Processor with 512 KB L2 Cache System Compatibility Guidelines Table 1.
Intel® Xeon™ Processor with 512 KB L2 Cache System Compatibility Guidelines Table 1. 6.
Intel® Xeon™ Processor with 512 KB L2 Cache System Compatibility Guidelines PWRGOOD input to the processor. PWR_OK will be deasserted when any output of an ATX12V-compliant or SSI-compliant power supply falls below regulation limits. It is important to maintain SM_VCC at any time the output of the VRM is enabled. Driving the VRM’s OUTEN with the PWR_OK signal will ensure correct sequencing at both power up and power down. Figure 1. Voltage Sequence Timing Requirements Power Up T0 = 95% 3.3 volt level 3.
Intel® Xeon™ Processor with 512 KB L2 Cache System Compatibility Guidelines 7.0 Power and Signal Levels The VID for the Intel® Xeon™ processor with 512 KB L2 cache is 1.500 volts compared to a VID level of 1.700 volts for the Intel Xeon processor. The Intel Xeon processor with 512 KB L2 cache still uses a single core voltage supply (VCC) to supply the termination voltage (VTT).
Intel® Xeon™ Processor with 512 KB L2 Cache System Compatibility Guidelines Xeon processor with 512 KB L2 cache operates at its tested frequency at initial power-on. If the processor needs to run at a lower core frequency, as must be done when a higher speed processor is added to a system that contains a lower frequency processor, the system BIOS is able to effect the change in the core to system bus ratio.
