R ITP700 Debug Port Design Guide February 2004 Document Number: 249679-014
R INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
R Contents 1 Uniprocessor ITP Debug Port Implementation Guidelines................................................ 11 1.1 General Description.............................................................................................. 11 1.1.1 ITP Features ......................................................................................... 11 Recommended Signal Terminations .................................................................... 12 ITP Signal Layout Guidelines .........................
R ® 7.1.1 8 ® ® Intel Itanium 2 Processor System Implementation Guidelines ...................................... 65 ® 8.1 ® ITP DC and AC Electrical Specifications for Intel Itanium 2 Processor Systems ................................................................................................................ 65 8.1.1 DC Electrical Specifications .................................................................. 65 8.1.2 AC Electrical Specifications ............................................
R Figures Figure 1. PWR Routing and Usage................................................................................... 13 Figure 2. Recommended Layout Topology ....................................................................... 17 Figure 3. ITP700 Flex Required Layout of Reset .............................................................. 20 Figure 4. ITP700 Flex Required Layout of BPM[5:0]#....................................................... 21 Figure 5. PWR Routing and Usage.................
R Table 20. ITP700 DPA System Signal AC Electrical Characteristics ................................ 38 Table 21. ITP700 DPA JTAG Signal AC Electrical Characteristics................................... 39 Table 22. ITP700 DPA Execution Signal AC Electrical Characteristics ............................ 40 Table 23. P700 DPA Pin Absolute Maximums.................................................................. 40 Table 24. ITP700 LVDPA System Signal Descriptions ...............................................
R Revision History Revision Description Revision Date Rev 1.0 Initial Release with Intel® Xeon™ Processor May 2001 Rev 1.03 Correction of +/- TCLK May 2001 Rev 1.10 ® ® Addition of Chapter 5: Intel Pentium 4 Processor in the 478 Pin Package System Implementation Guidelines August 2001 Addition of termination information for BPM[5:0]# and Reset# signals Rev 1.15 Append to Chapter 5: Intel® Pentium® 4 Processor in the 478 Pin Package / Intel® Pentium® 4 Processor with 512KB L2 Cache on 0.
R Definitions Term 8 Definition DPA Debug Port Adapter. Section of ITP hardware that plugs into the target system Debug Port. ITP The acronym “ITP” as used within this document refers to an In-Target Probe run-time control tool as produced by Intel as well as third party vendors. This specification is not meant to imply that any vendor’s debug tool is preferred over any other.
R How to Use This Document This document has two primary roles in the design process. First and foremost, this document is a location for recording all of the best-known methods relating to the design of an ITP700 based scan chain in a target. Second, this document serves as the Intel Corporation communication of Design Guide and In Target Probe (ITP) signal specifications for a given processor. The document is structured to serve both purposes.
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R 1 Uniprocessor ITP Debug Port Implementation Guidelines The signals involved in the ITP debug system are high-speed signals and must be routed with highspeed design considerations in mind. The implementation offers some flexibility in areas such as scan chain routing, addition of non-ITP TAP master to the local scan chain, and clock rate of the scan chain. However, the implementation is not flexible in system bus BPM[5:0]# , RESET#, or BCLK(p/n) connections.
R • Hot-plug support for the debug port adapter (DPA) into a target system. • Supports arbitration with a local TAP Master (e.g. manufacturing test chain) through a simple handshake. 1.2 Recommended Signal Terminations Table 1. Recommended Debug Port Signal Terminations Signal PWR Termination Value 1.5 kΩ 1% Termination Voltage VTERM of BPM[5:0]# and RESET# Termination Location Notes Within 1 ns of debug port BCLK(p/n) 1 2 DBA# 150 – 240 Ω 5% VCC of target system recovery circuit.
R Figure 1. PWR Routing and Usage Vterm Reset# + BPM0# - 1.5 K 1% Vpwr Debug Port Pin PWR + - 3.0 K 1% Platform MB + BPM1# . Vpwr . ITP 700 BPM[5:0]#/Reset# Signals BPM5# Recovery Point NOTE: By varying the platform 1.5-K resistor, the recovery point could be increased or decreased. 1.3 ITP Signal Layout Guidelines This section contains the layout guidelines for the debug port signals. Please refer to the specification chapter for the debug port electrical and mechanical specifications.
R datasheets. VTAP should be used for the pull-up resistors on all JTAG signals in the scan chain that operates directly from the ITP. If a bus translator is used to translate an ITP scan chain to a higher voltage, VTAP on the opposite side of the translator from the ITP shall change as well. Note: All termination locations indicated are referenced to the target system. 1.3.1 System Signal Layout Guidelines Table 2.
R DBA# and DBR# are output signals from the ITP. The ITP provides an open drain FET closure to GND as the drive of DBA# and DBR#. The target system should provide the pull-up for both of these signals. The pull-up can be to any voltage up to five volts that is consistent with the input specifications of the component used to receive these signals on the target system. DBR# is the ITP debug port reset signal that should always be routed to the system reset controller.
R 1.3.3 Execution Signal Layout Guidelines Table 4. Execution Signal Layout Guidelines Debug Port Signal Layout Guideline BPM[5:0]# These signals are extremely routing critical. The debug port recovers these signals relative to BCLK at the debug port pins. Therefore, the signals must be routed with closely matched electrical lengths (within ±50 ps) and no greater than 1.0 ns from the processor to the debug port.
R Figure 2. Recommended Layout Topology Debug Port TCK@TTCK 27 Ohms System Bus Agent System FBO@(TTCK+TBPM) BPMn@(TT1+TBPM) BLCK@T0 BMMn@T1 Clock Driver BLCK@(TT0+TBPM) NOTES: 1. All of the above routes must be simulated to ensure signal integrity. Failure to do so may result in non functional ITP. 2. All combination timings in the above drawing are ±50 ps in routing length maximum. The figure above defines propagation delays of various ITP signals from the driver to the receiver.
R The advantages of this ITP700 Flex are a significantly reduced footprint and keepout volume. Please refer to the ITP700Flex specifications chapter for the mechanical specifications. 1.4.1 Signal Descriptions The pinout of the debug port connector at the end of the ITP700 Flex is identical to that of the standard debug port connector. See Figure 4 for details. The pinout of the target system surface mount connector for ITP700 Flex is below. Table 5.
R 1.4.2 Termination and Routing Guidelines Table 6. Recommended Debug Port Signal Terminations Signal Termination Value Termination Voltage Termination Location BCLK(p/n) Notes 1 DBA# 150 – 240 Ω 5% VCC of target system recovery circuit.
R is possible to terminate these signals using resistances equal to the characteristic impedance of the motherboard using short (100 ps or less) stubs after the trace meets the ITP700 Flex surface mount connector on the motherboard. BPM[5:0]# lengths must still be matched on the motherboard to within 50 ps of one another and with RESET# length D1 (see Figure 4 and Figure 5). Note that BPM5DR# is completely removed form the ITP700 Flex design. Its functionality is integrated on the ITP700 Flex hardware.
R Figure 4. ITP700 Flex Required Layout of BPM[5:0]# Vcc uProcessor Rt Rt Rt Rt Rt BPM# 0 1 2 3 4 5 Rt Debug Port Connector BPM[0]# Signal BPM[1]# Signal BPM[2]# Signal BPM[3]# Signal BPM[4]# Signal BPM[5]# Signal D1 Table 8. BPM[5:0]# Definitions Parameter Min D1 Rt Nominal Max Notes 1 ns 1,2 3 NOTES: 1. This signal must be length matched to RESET# to within 50 ps. 2. D1 is defined as the total length from the processor driver to the corresponding BPM at the connector. 3.
R Table 9. ITP700 Flex Deltas from Standard ITP AC/DC Specifications Signal Specification Standard ITP ITP700 Flex BCLK(p/n) VPTP 300 mV 320 mV DBA#, DBR# Resistance from pin to ground when active 6Ω 10 Ω TCK VOH MIN 2 1.25 V 1.20 V TMS VOL MAX 3 0.30 V 0.32 V BPM[5:0]#, RESET# VIH MIN PWR+(0.15*VTERM) PWR+(0.16*VTERM) BPM[5:0]#, RESET# VIL MAX PWR -(0.15*VTERM) PWR -(0.
R 2 Multiprocessor ITP Debug Port Implementation Guidelines The ITP scan chain of multiprocessor systems with multiple chipset components requires that the debug port and associated scan chain be designed into the system board. An interposer debug port solution will not provide visibility to a multiple load scan chain because an interposer has no physical way to break the scan chain without losing access to the remainder of the processors and chipset.
R 2.1.1 ITP Features • Operation at up to 16 MHz. • Ability to drive up to one EXECUTION signal (BPM5#). • Ability to monitor up to six EXECUTION signals (BPM[5-0]#). • Accepts a differential system BCLK. • Synchronous TAP operations. • Hot-plug support for the debug port adapter (DPA) into a target system. • Supports arbitration with a local TAP Master (e.g., manufacturing test chain) through a simple handshake. 2.2 Recommended Signal Terminations Table 10.
R Signal BPM5DR# Termination Value Connect to BPM[5]# at the debug port Termination Voltage Termination Location NA Notes NA NOTES: 1. The target system resistor connected between VTERM and the PWR pin is part of a voltage division circuit (see below). The voltage derived from the voltage divider is used as a reference for recovery of the BPM[5:0]# and RESET# signals on the ITP. The recovery point of the BPM[5:0]# and RESET# signals can be modified by scaling the target system resistor.
R There are three signal groups within the debug port. Each group has a different set of layout requirements: • System - The system signal group indicates the access state of the entire system • JTAG - The JTAG signal group consists of the five standard JTAG pins. The JTAG signals are to be designed to run up to 16 MHz. • Execution - The execution signal group contains the reset and run control signals used to indicate operational conditions.
R Debug Port Signal Layout Guideline FBI FBI is a fast edge copy of TCK that can optionally be used as the source of scan chain TCK when TCK buffers are implemented on a system board. FBI should be loaded with no greater than 40 pF and have a DC load of no less than 200 Ω to GND. If used, this is a critical clock for the scan chain and must be analyzed for signal quality and timing with respect to the specifications of the intended receiver of the FBI signal. DBR# This is a non-critical route.
R Debug Port Signal Layout Guideline TDI, TDO JTAG scan data signals. These signals require minor timing and signal integrity analysis / simulation, These signals are routed point-to-point, possibly through device bypass mechanisms. The terminations should be located within 300 ps to each load. TDI is driven on the falling edge of TCK at the ITP and recovered on the following rising edge of TCK at the processor. TRST# Non-critical JTAG reset signal routed to all scan chain devices.
R Figure 7. Recommended Bypass Jumper Configuration VTAP Debug Port 150 Ohm Bypass Header TDI VTAP Scan Agent 1 2 1 4 3 150 Ohm Bypass Header TDI TDO Scan Agent 2 2 1 4 3 TDI TDO VTAP 75 Ohm TDO When well designed, Quickswitches can be used to replace bypass jumpers/headers.
R The debug port should be placed as close as is physically reasonable to the processor and no further than 1.0 ns flight time (as measured by trace length of the BPM[5:0]#) from the processor. System designers should record the flight time of the BPM[5:0]# signals from the processor to the debug port. This value will be important during the routing of several other debug port signals. Ideally BPM[5]# will be routed from the processor to the debug port BPM[5]# pin matched with the other BPM# s.
R Figure 8. Recommended Layout Topology T0 T0 BCLK System Bus Agent System Bus Agent TCK Debug Port BCLK TCK TTCK TTCK TCK TTCK 27 Ohms TTCK TCK TCK System Bus Agent FBO BPMn BCLK BPMn (TTCK+TBPM) (T1+TBPM) System Bus Agent BCLK T0 BCLK T0 System Clock Driver T1 (T0+TBPM) NOTES: 1. All of the above routes must be simulated to ensure signal integrity. Failure to do so may result in nonfunctional ITP. 2.
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R 3 ITP700 DPA Specifications 3.1 ITP700 DPA Specifications The signals used by the ITP are divided into three categories: system, JTAG, and execution. The system signal group indicates the access state of the entire system. The JTAG signal group indicates the IEEE* 1149.1 control signals. The execution signal group contains the reset and run control signals used to coordinate debug activities. The signals in the execution group are system bus signals and are recovered on BCLK.
R The following tables identify the signals that make up the ITP debug port connector definition. The I/O direction indicated for each signal is with respect to the debug port. Local TAP refers to a resident TAP master system that has been installed as part of a system designer’s manufacturing process. Values of required pull up and pull down resistors are documented in the recommended termination table in this chapter. Table 14.
R Table 15. JTAG Signal Descriptions Debug Port Signal Pin # I/O Description TCK 16 Output Standard source of TAP master clock. TCK must have a pull down resistor provided on the target system. The debug port drives TCK at up to 16 MHz if so enabled. TCK can be skewed with respect to BCLK(p/n). TCK is optional for ITP implementation only if FBI is used as the TAP master clock. TDI 10 Output TAP data input signal.
R 3.2 ITP700 DPA DC Electrical Characteristics Table 17. ITP700 DPA System Signal DC Characteristics Min Signal FBI VOH 1.00 VOL IOH 0.40 -5 IOL FBO V 1 V 1 mA 5 mA 1.70 V VIL 0.00 0.55 V IIH -150 VIH RPWR 0.30 2.95 VIH µA 300 µA 2.80 V 2 0.10 V 3 3.05 kΩ 4 1.70 V VIL 0.10 V VPTP 300 mV -1 mA IIH DBA#, DBR# Note 0.90 VIL BCLK(p/n) Unit VIH IIL PWR Max 5 IIL 300 µA CIN 10 pF 6 Ω 6 Ω 7 120 mA 8 IDBX NOTES: 1.
R Table 18. ITP700 DPA JTAG Signal DC Electrical Characteristics Signal TCK Min VOH Typ 1.25 VOL IOH 0.3 -47 0 ZTCK VOH 20 1.30 VOL IOH 0.30 -10 TDI, TRST# VOH 35 20 1.3 VOL IOH 0.3 -5 IOL TDO Note V 1 V 2 mA Ω 3 V 4 V 4 mA IOL ZTMS Unit mA IOL TMS Max mA Ω 3 V 1 V 1 mA 5 mA VIH 0.90 1.7 V VIL 0 0.55 V IIH -150 IIH µA 300 µA NOTES: 1. At maximum current specified. 2. As measured into a 27 Ω 1% resistor to GND. 3. AC Impedance of the driver. 4.
R Table 19. ITP700 DPA Execution Signal DC Electrical Characteristics Min Max Unit IOL 120 mA 1 ROL 18 Ω 2 CIN 4 pF 3 3.00 V 4 PWR (0.15*VTERM) V 4 Signal BPM5DR# BPM[5:0]#, RESET# VIH PWR + (0.15*VTERM) VIL IIH -150 Note uA IIL 300 uA CIN 3 pF 3 NOTES: 1. Maximum sink current of the ITP. 2. Series resistance to GND when output is low. 3. Includes capacitive effects of mated connector. 4. Over valid range of VIH of PWR. 3.
R Table 21. ITP700 DPA JTAG Signal AC Electrical Characteristics Signal TDO Parameter Min TMS TDI TRST# Unit Note Setup 5 ns 1 Hold 0.5 ns 1 15 ns 2 13 ns 2, 3 Rise/Fall Time TCK Max Rise/Fall Time 9 Period 58 ns 4 Time High 25 ns 5 Time Low 25 ns 5 Rise/Fall Time 7 16 ns 2, 6 Clock to Out -5 0 ns 7 Rise Time 0.5 2.0 ns 2, 8 Fall Time 0.5 2.0 ns 2, 8 Clock to Out -8 0 ns 7 Assert Time 300 ns NOTES: 1.
R Table 22. ITP700 DPA Execution Signal AC Electrical Characteristics Signal BPM[5:0]#, RESET BCLK(p/n) Min Parameter Unit Note Setup 400 ps 1 Hold 200 ps 1 Rise Time 5 ns 2 Fall Time 5 ns 2 15 ns 3 Period BPM5DR# Max 5 Time High 2.2 ns Time Low 2.2 ns Rise Time 1 4 ns 2, 4 Fall Time 8 15 ns 2, 4 NOTES: 1. With respect to BCLK(p/n). 2. Measured from 20% to 80% of transition. 3. Specification for valid synchronous operation of the ITP.
R 3.5 Mechanical Requirements The ITP debug port adapter (DPA) plugs into the target system’s onboard debug port connector. The ITP cable connects the DPA hardware to the ITP hardware located on a host system. The host system runs the ITP software. In order for the ITP cabling to egress the system under test, an aperture of two inches minimum width by one-inch minimum height must be available. Please contact your run-control tool vendor for complete mechanical constraints for other tools.
R Figure 11.
R Figure 12.
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R 4 ITP700 LVDPA Specifications 4.1 ITP700 LVDPA Signal Descriptions The signals used by the ITP700 LVDPA are divided into three categories: system, JTAG, and execution. The system signal group indicates the access state of the entire system. The JTAG signal group indicates the IEEE 1149.1 control signals. The execution signal group contains the reset and run control signals used to coordinate debug activities. The signals in the execution group are system bus signals and are recovered on BCLK.
R The following tables identify the signals that make up the ITP debug port connector definition. The I/O direction indicated for each signal is with respect to the debug port. Local TAP refers to a resident TAP master system that has been installed as part of a system designer’s manufacturing process. Values of required pull up and pull down resistors are documented in the recommended termination table in this chapter. Table 24.
R Table 25. JTAG Signal Descriptions Debug Port Signal Pin # I/O Description TCK 16 Output Standard source of TAP master clock. TCK must have a pull down resistor provided on the target system. The debug port drives TCK at up to 16 MHz if so enabled. TCK can be skewed with respect to BCLK(p/n). TCK is optional for ITP implementation only if FBI is used as the TAP master clock. TDI 10 Output TAP data input signal.
R 4.2 ITP700 LVDPA DC Electrical Characteristics Table 27. ITP LVDPA System Signal DC Characteristics Min Signal FBI VTAP+0.250 V 1, 9. VOL 0 0.1*VTAP V 1 IOH -8 VIH IIH VIH DBA#, DBR# mA 0.5*VTAP +0.150 V 0.5*VTAP -0.150 -100 0.30 VIL RPWR mA 16 IIL BCLK(p/n) Note 0.9*VTAP VIL PWR Unit VOH IOL FBO Max 2.95 VIH V µA 100 µA 2.80 V 2 0.10 V 3 3.05 kΩ 4 1.70 V VIL 0.
R Table 28. ITP700 LVDPA JTAG Signal DC Electrical Characteristics Signal TCK Min Typ VTAP + 0.250 V 2 VOL 0 0.1*VTAP V 2 IOH -60mA mA 0 20 Ω 3 0.9*VTAP VTAP + 0.250 V 4 VOL 0 0.1*VTAP V 4 IOH -16 mA 36 ZTMS 20 VOH VOL 0 IOH 0 IOL 0.1*VTAP mA Ω 3 V 5 V 1 mA 8 mA VOH 0.9*VTAP VTAP + 0.250 V 1 VOL 0 0.1*VTAP V 1 IOH -8 VIH 0.5*VTAP +0.150 VIL IIH mA 8 IOL TDO mA VOH IOL TRST# Note 0.9*VTAP ZTCK TDI Unit VOH IOL TMS Max V 0.5*VTAP -0.
R Table 29. ITP700 LVDPA Execution Signal DC Electrical Characteristics Min Signal BPM5DR# BPM[5:0]#, RESET# Max Unit Note IOL 120 mA 1 ROL 18 Ω 2 CIN 4 pF 3 3.00 V 4 PWR (0.15*VTERM) V 4 VIH PWR + (0.15*VTERM) VIL IIH -150 µA IIL 300 µA CIN 3 pF 3 NOTES: 1. Maximum sink current of the ITP. 2. Series resistance to GND when output is low. 3. Includes capacitive effects of mated connector. 4. Over valid range of VIH of PWR. 4.
R Table 31. ITP700 LVDPA JTAG Signal AC Electrical Characteristics Signal TDO Parameter Min TMS TDI TRST# Unit Note Setup 5 ns 1 Hold 0.5 ns 1 15 ns 2 13 ns 2, 3 Rise/Fall Time TCK Max Rise/Fall Time 9 Period 58 ns 4 Time High 25 ns 5 Time Low 25 ns 5 Rise/Fall Time 7 16 ns 2, 6 Clock to Out -5 0 ns 7 Rise Time 0.5 2.0 ns 2, 8 Fall Time 0.5 2.0 ns 2, 8 Clock to Out -8 0 ns 7 Assert Time 300 ns NOTES: 1.
R Table 32. ITP700 LVDPA Execution Signal AC Electrical Characteristics Signal BPM[5:0]#, RESET BCLK(p/n) Parameter Max Unit Note Setup 400 ps 1 Hold 200 ps 1 Rise Time 5 ns 2 Fall Time 5 ns 2 15 ns 3 Period BPM5DR# Min 5 Time High 2.2 ns Time Low 2.2 ns Rise Time 1 4 ns 2, 4 Fall Time 8 15 ns 2, 4 NOTES: 1. With respect to BCLK(p/n). 2. Measured from 20% to 80% of transition. 3. Specification for valid synchronous operation of the ITP.
R 5 ITP700 Flex Mechanical Requirements The pinout of the debug port connector at the end of the ITP700 Flex is identical to that of the standard debug port connector. The surface mount device is a Molex #52499-001 or equivalent. This connector does not need to be included on the BOM for production motherboards. It is expected that the connector footprint be included on the baseboard in a location that will allow the connector to be reworked onto the board.
R Figure 14.
R Figure 15. Top View of Surface Mount ITP700 Flex Connector on the Target System Flex Cable Enters This Side of Connector Pin 1 Pin 28 NOTES: 1. Keying of flex cable is the note “This Side Up” on the flex cable. 2. There is no physical keying.
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R 6 Intel® Xeon™ Processor with 512KB L2 Cache at 2.20, 2.0, and 1.80 GHz DP / Intel® Xeon™ Processor MP Server System Implementation Guidelines 6.1 Termination and Routing Guidelines The following specifications are for an ITP700 implementation that is terminated according to the content in the Multi-processor ITP debug port Implementation Guidelines chapter of this document adjusted for Intel® Xeon™ processor specific implementation guidelines dictated in section 4.3 of this document.
R Table 33. BPM[5:0]# Figure Definitions Parameter LBPM Min Nominal Max Notes 1 ns 1 NOTES: 1. BPM[5:0]# must be length matched to within 50 ps of themselves and RESET#. 2. Refer to the Platform Design Guide for BPM parameters between other components. Clarification 1. The BPM[5:0]# and RESET# traces should be terminated to the processor VCC voltage on both ends of the transmission line, similar to that of the system bus.
R 7 Intel® Pentium® 4 Processor / Mobile Intel® Pentium® 4 Processor-M / Intel® Centrino™ Mobile Technology System Implementation Guidelines 7.
R ® ® ® ® Figure 17 – BPM[5:0]# Connectivity for Intel Pentium 4 Processor, Intel Pentium 4 ® ™ Processor-M, and Systems Based on Intel Centrino Mobile Technology Vcc Vcc Chipset Rt Rt Rt Rt Rt Rt uProcessor BPM# 0 1 2 3 4 5 BPM# 0 1 2 3 4 5 Rt Rt Rt Rt Rt Rt Debug Port Connector BPM[0]# Signal BPM[1]# Signal BPM[2]# Signal BPM[3]# Signal LBP M Table 34. BPM[5:0]# Figure Definitions Parameter LBPM Min Nominal Max Notes 1 ns 1 NOTES: 1.
R pairs from the system clock source. One pair is for the motherboard debug port, and the other is for the ITP_BCLK(p/n) pins on the processor socket. The routing guidelines for the motherboard based debug port are defined in Chapter 1. The processor socket ITP_BCLK(p/n) pins have the same routing and termination requirements as a processor clock pair.
R Figure 18 – ITP Clock Routing options using System Clock Driver 1K ITPCLKOUT[1] 1K ITPCLKOUT[0] Intel® Pentium® 4 Processor ITPCLK[1:0] 2 System Clock Driver BCLK[p:n] ITP Debug Port 7.1.1.2 Option B) Using the ITPCLKOUT[1:0] Pins: (For B0 Silicon or Greater) 1. Route the ITPCLKOUT[1:0] pins directly from the processor to the ITP connector pins BCLK[n:p] using 33 Ω series resistors, 33 Ω pull-down source termination resistors at the processor, and 1 kΩ pull-ups to VCC_CORE.2 2.
R Figure 19 – ITP Clock Routing Options Using ITPCLKOUT[1:0] Pins 1K ITPCLKOUT[1:0] BCLK[p/n] Intel® Pentium® 4 Processor 33 ITP Debug Port 33 ITPCLK[1:0] NOTES: 1. There was an error in the WW41 Message of the Week (MOW) recommendation. The recommendation stated to use individual matched resistors to terminate ITPCLKOUT[1:0] when these signals are not in use, to provide better immunity to ESD for processor inputs.
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R 8 Intel® Itanium® 2 Processor System Implementation Guidelines There are three classes of ITP debug tool connections to Intel® Itanium® 2 processor platforms: • ITP debug port for each processor node for register access and run-time control. A processor node consists of at least one Itanium 2 processor and may contain other TAP devices. • ITP debug port for each I/O domain for register access and event line monitoring.
R ® ® Table 35. ITP System Signal DC Characteristics for the Intel Itanium 2 Processor DPA Type Signal FBI VOH VOL FBO Min ITP700DPA 1.00 LVDPA 0.9*VTAP ITP700DPA VTAP+0.250 V 1, 9. 0.40 V 1 0.1*VTAP V 1 ITP700DPA -5 LVDPA -8 IOL ITP700DPA 5 mA LVDPA 16 mA 1.70 V ITP700DPA 0.90 LVDPA 0.5*VTAP +0.150 ITP700DPA 0.00 mA mA V 0.55 V 0.5*VTAP 0.150 V IIH ITP700DPA -150 LVDPA -100 IIL ITP700DPA 300 µA LVDPA 100 µA 0.30 2.80 V 0.10 V 3 2.95 3.
R ® ® Table 36 - ITP JTAG Signal DC Electrical Characteristics for the Intel Itanium 2 Processor Signal TCK DPA Type VOH VOL IOH IOL Min ITP700DPA 1.25 LVDPA 0.9*VTAP ITP700DPA VOH VOL IOH IOL VOH 1 VTAP + 0.250 V 2 0.3 V 2 0.1*VTAP V 2 ITP700DPA -47 mA LVDPA -60 mA mA ITP700DPA 0 mA LVDPA 0 mA Ω 3 V 4 VTAP + 0.250 V 4 0.30 V 4 0.1*VTAP V 4 20 ITP700DPA 1.30 LVDPA 0.
R Signal TRST# (cont.) DPA Type IOH IOL TDO VIH VIL Min Typ IIL Unit LVDPA 0 0.1*VTAP ITP700DPA -5 mA LVDPA -8 mA V ITP700DPA 5 mA LVDPA 8 mA 1.7 V ITP700DPA 0.90 LVDPA 0.5*VTAP +0.150 ITP700DPA 0 Note 1 V LVDPA IIH Max 0.55 V 0.5*VTAP 0.150 V ITP700DPA -150 µA LVDPA -100 µA ITP700DPA 300 µA LVDPA 100 µA NOTES: 1. At maximum current specified. 2. As measured into a 27 Ω 1% resistor to GND. 3. AC Impedance of the driver. 4.
R 8.1.2 AC Electrical Specifications ® ® Table 38 - ITP System Signal AC Electrical Characteristics for the Intel Itanium 2 Processor Signal Min Parameter Max Unit Note PWR PWR VIL Max to Tristate 150 FBI Rise Time 0.5 2 ns 1, 2, 3 Fall Time 0.5 2 ns 1, 2, 3 Skew -9 -6 ns 4 DBA#↓ to first TCK↑ 75 ns 5 ns 6 DBA# µs DBA#↑ to last TCK↓ DBR# 100 DBR# Assertion Period 150 µs NOTES: 1. Measured from 20% to 80% of transition. 2.
R 5. 6. 7. 8. Measured from 50% of first edge to 50% of second edge. As measured into a 39 Ω load to VTAP and 35 pF to GND. With respect to falling edge of TCK at the debug port using 50% of transition for both signals. As measured into a 1500 Ω load to VTAP and 10 pF to GND. ® ® Table 40.
R 8.2.1 System Signal Layout Guidelines The following are additions to the ITP700 Debug Port Design Guide’s System Signal Layout Guidelines. BCLK(p/n) In addition to the generic MP guidelines in this guide, the BCLK for I/O domain debug ports should be routed with the same length as the clocks to the Intel® Itanium® 2 processor chipset components within that domain. BCLK routing rules for miscellaneous debug ports depend on the use of the debug port.
R 8.2.3 BPM Connectivity for I/O Domain Debug Ports The Itanium 2 processor-based chipset has the capability to attach an ITP to the chipset components within each IO Domain to provide debug hooks to the IO subsystem and Scalability Port Switch components. IO Domain debug ports must follow the following guidelines: • For single-domain systems, all SNCs, SPSs and IOHs should be connected to a single wiredOR EV[3:0]# bus. This will support inter-device communication for performance and debugging operations.
R 8.3 Intel® Itanium® 2 Processor Routing Guidelines All of the termination and routing guidelines defined in the multiprocessor chapter of the ITP700 Debug Port Design Guide (found on developer.intel.com) must be adhered to for an ITP700 debug port implementation with an Itanium 2 processor-based platform with the following clarifications: Clarification 1. The BPM[5:0]# and RESET# traces should be terminated to the system bus termination voltage of 1.2V on both ends of the transmission line.
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R 9 Intel® E8870 Chipset System Implementation Guidelines This chapter describes the I/O domain and the miscellaneous auxiliary scan chain debug port implementation specific to systems utilizing the E8870 chipset. As such, system designers should first familiarize themselves with the general implementation, routing, and termination rules as defined in the Intel® Itanium® 2 Processor System Implementation Guidelines chapter of this document.
R • The RESET# will only be necessary where a reset, unique and independent from the processor node debug port, is required for devices in the I/O domain. Note: Timing of debug port TAP signals (to and from the components) must be verified to meet the setup and hold times after component timing, debug port timing, trace delays, and any intermediate buffers are considered.
R 10 Appendix A – Alternate Bypass Methods Sections 1.5.2 and 2.5.2 of the attached document describes the recommended bypass method for the ITP scan chain using a four-pin header. The four-pin header is preferred due to the characteristic it has of completely removing the TDO pin from the TDI/TDO path to the next scan chain agent. There are other methods possible for completely bypassing populated scan chain agents.
R If the customer is sure that bypassed agents in the scan chain will always be depopulated, a threepin header bypass scheme will be adequate. As long as the bypassed agent is not on the system board, there is no possibility of double-driving the net. Figure 23 illustrates a possible three-pin bypass configuration. Note that when pins one and two are connected, TDO of P0 and TDO of the ITP are connected. It is assumed that the TDO driver of P1 will not be present on this TDO net. Figure 23.
R Quickswitches can be used to replace bypass jumpers/headers if the circuit is well designed. Many quickswitch packages contain a low resistance (~7- Ω), low capacitance (~5 pF) analog bypass switch (FET). Both the jumpers and the quickswitches designs add capacitance and resistance to the TDI/TDO line for each device bypassed. RC delay can slow down the rise time significantly when multiple devices are being bypassed.
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R 11 Appendix B – Buffering TCK While Intel strongly recommends implementing TCK for the scan chain using TCK and a matched star topology, there are situations that require buffers to be placed in the TCK path. Assure that the buffers chosen to drive TCK will be able to operate in the voltage range appropriate to the target TAP interfaces. There have been several successful buffer implementations using a 74VCX style part such as a 74VCX 244.
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R 12 Appendix C – Recovering a Single-Ended BCLK The ITP uses a differential ECL receiver to recover the system BCLK. It is possible to modify the target system hardware to accept a single-ended system clock. This is accomplished through the creation of a stable reference voltage on the target system. This voltage should equal to the center of the swing of BCLKn as seen at the debug port. Use relatively low resistance values (such as 200 Ω or less) between the BCLK high-side drive voltage and GND.
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R 13 Appendix D – Arbitration of the Scan Chain With a Local TAP Master The basic handshaking mechanism is predicated on the notion that when an alternate local TAP master has requested access to the target system, the debug tool will behave as though it has been unplugged. This suggests that when control is regained, the debug tool must regain the state information needed to operate properly. The protocol is as follows: 1. The ITP de-asserts the DBA# signal when the current task is complete.
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R 14 Appendix E – Designer’s Checklist for Schematic and Layout Reviews The following tables serve as a guide for a designer to review a generic ITP700 debug port implementation in detail. These guidelines are in no means comprehensive nor serve to replace the recommended design guidelines in this document. Table 41.
R Table 42. Part 2: TDI/TDO Connectivity PASS FAIL Don’t Care ISSUE Is the connectivity of TDI/TDO around the scan chain correct? Table 43.
R Table 45. Buffered TCK / TMS Implementation Issues PASS FAIL Don’t’ Care ISSUE FBI must be used as the clock input for the buffer. Is there an individual buffer for each TCK Load? If there is an extra buffer in the package, FBO should be driven from that spare buffer. Otherwise, FBO should be connected to an output of the TCK buffer.
R PASS FAIL Don’t Care ISSUE Are the Resistance Values and Termination Voltages Listed in the table above adhered to? No bypass condition should allow the Pull-up resistance on TDI to be less than 150 Ω. Part 5 – Layout Issues Below is a list of basic rules to keep in mind when routing the schematics. These guidelines are in no means comprehensive or serve to replace the recommended layout guidelines in this document. 1.
R 15 Appendix F – ITP700 DPA Spice Models Intel has a behavioral spice model of the ITP hardware available for simulation of critical routes and topography. Intel strongly recommends that these models be used to simulate at the very least, TCK, BCLK and Execution signal integrity and timing. The models are created and packaged as single signal models.
R * MINITEK* = ITP DPA HEADER MODEL * * ADDITIONAL MODELS THAT MAY BE ADDED: * VCX16374 = TOSHIBA* VCX BUFFER/DRIVER * qs3vh125 = QUALITY SEMICONDUCTOR* QUICKSWITCH * **************************************************** .SUBCKT TCKDR GNDREF DRV M2 * Declare VCX (Created on DPI/DPA) VINIT1 VCX GNDREF DC 1.65 * Load Elements L2 DRV M1 100Nh C13 M1 TCKN1 100pF R16 TCKN1 GNDREF 10 R13 M1 EVCCQS 17.4 * * The following is a generalization of the qs3vh125.
R X2 VCX INT2 GNDREF QSOP *************************************************** * Setup Minitek* connector nodes * MINITEK* PAD CAPACITANCE CMT1 M1 GNDREF 5.00E-13 CMT2 M2 GNDREF 5.
R * * PINS: * GNDREF = GROUND * DRV = DRIVE FROM TWO VCX OUTPUTS * M2 = MINITEK* CONNECTOR AT TARGET * * ADDITIONAL REQUIRED SUBCIRCUIT INCLUDED IN PACKAGES.TXT: * MINITEK* = ITP DPA HEADER MODEL * * ADDITIONAL MODELS THAT MAY BE ADDED: * VCX16374 = TOSHIBA* VCX BUFFER/DRIVER * *************************************************** .SUBCKT TMSDR GNDREF DRV M2 * Load elements L1 DRV M1 100Nh C3 M1 GNDREF 100Pf * Setup Minitek* connector nodes * Minitek* pad capacitance CMT1 M1 GNDREF 5.
R RMT8 M9 GNDREF 250 RMT9 M10 GNDREF 250 RMT10 M11 GNDREF 250 RMT11 M12 GNDREF 250 RMT12 M13 GNDREF 250 RMT13 M14 GNDREF 250 RMT14 M15 GNDREF 250 RMT15 M16 GNDREF 250 * Include Minitek* connector model X1 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 MINITEK* .
R * qs3vh125 = QUALITY SEMICONDUCTOR* QUICKSWITCH * *************************************************** .SUBCKT DBADBR GNDREF M2 * * The following is a generalization of the qs3vh125. * A true spice model of the quickswitch may be * added between pins M1 and GNDREF. * Be sure to remove the following generalization * if the true spice model is used.
R RMT6 M7 GNDREF 250 RMT7 M8 GNDREF 250 RMT8 M9 GNDREF 250 RMT9 M10 GNDREF 250 RMT10 M11 GNDREF 250 RMT11 M12 GNDREF 250 RMT12 M13 GNDREF 250 RMT13 M14 GNDREF 250 RMT14 M15 GNDREF 250 RMT15 M16 GNDREF 250 * Include Minitek* connector model. X3 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 MINITEK* .
R * ADDITIONAL MODEL THAT MAY BE ADDED: * qs3vh125 = QUALITY SEMICONDUCTOR* QUICKSWITCH * **************************************************** .SUBCKT BPM5DR GNDREF M2 * Declare VCX (produced on DPI/DPA) VINIT1 VCX GNDREF DC 1.65 * * The following is a generalization of the qs3vh125. * A true spice model of the quickswitch may be * added between pins BPM5QS and GNDREF. * Be sure to remove the following generalization * if the true spice model is used.
R CMT1 M1 GNDREF 5.00E-13 CMT2 M2 GNDREF 5.00E-13 * Tie all other Minitek* Model Pins to Ground RMT2 M3 GNDREF 250 RMT3 M4 GNDREF 250 RMT4 M5 GNDREF 250 RMT5 M6 GNDREF 250 RMT6 M7 GNDREF 250 RMT7 M8 GNDREF 250 RMT8 M9 GNDREF 250 RMT9 M10 GNDREF 250 RMT10 M11 GNDREF 250 RMT11 M12 GNDREF 250 RMT12 M13 GNDREF 250 RMT13 M14 GNDREF 250 RMT14 M15 GNDREF 250 RMT15 M16 GNDREF 250 * Include Minitek* connector model. X3 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 MINITEK* .
R Receive Pins: *************************************************** * BCK * BCLK(pn), LOAD MODEL LEVEL 1 * CREATED: NOVEMBER 22, 1999 * EXPANDED DOCUMENTATION: AUGUST 18, 2000 * * PINS: * M2=MINITEK* BCKP CONN AT TARGET * M4=MINITEK* BCKN CONN AT TARGET * ECLP=BCKP ECL INPUT * ECLN=BCKN ECL INPUT * * ADDITIONAL REQUIRED SUBCIRCUITS INCLUDED IN PACKAGES.
R * * The following is a generalization of the qs3vh125. * A true spice model of the quickswitch may be * added between pins M1 and BCLKQSP and pins * M3 and BCLKQSN.
R RP11C GNDREF ECLN 5600 RP11D GNDREF ECLN 5600 R21 ECLN ECLP 100 * Setup of Minitek* connector nodes * Minitek* pad capacitance CMT1 M1 GNDREF 5.00E-13 CMT2 M2 GNDREF 5.00E-13 CMT3 M3 GNDREF 5.00E-13 CMT4 M4 GNDREF 5.
R * UPDATED: NOVEMBER 22, 1999 * EXTENDED DOCUMENTATION: AUGUST 18, 2000 * * PINS: * GNDREF=GR0UND * M2 = MINITEK* AT TARGET * ECL = OUTPUT OF ATTENUATOR AT INPUT OF ECL RECEIVER * * ADDITIONAL REQUIRED SUBCIRCUIT INCLUDED IN ITP700_PACKAGES.TXT: * MINITEK* = ITP DPA HEADER MODEL * * ADDITIONAL MODEL THAT MAY BE ADDED: * mc100lvel17 = MOTOROLA* ECL RECEIVER * *************************************************** .SUBCKT BPMRESET GNDREF M2 ECL * ATTENUATOR MODEL C3 M1 ATTX 3.30E-12 C4 ATTX GNDREF 1.
R RMT2 M3 GNDREF 250 RMT3 M4 GNDREF 250 RMT4 M5 GNDREF 250 RMT5 M6 GNDREF 250 RMT6 M7 GNDREF 250 RMT7 M8 GNDREF 250 RMT8 M9 GNDREF 250 RMT9 M10 GNDREF 250 RMT10 M11 GNDREF 250 RMT11 M12 GNDREF 250 RMT12 M13 GNDREF 250 RMT13 M14 GNDREF 250 RMT14 M15 GNDREF 250 RMT15 M16 GNDREF 250 * Include Minitek* connector model X1 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 MINITEK* .
R * ADDITIONAL REQUIRED SUBCIRCUITS INCLUDED IN ITP700_PACKAGES.TXT: * QSOP = QSOP PIN MODEL, PACKAGE APPROXIMATION * MINITEK* = ITP DPA HEADER MODEL * * ADDITIONAL MODELS THAT MAY BE ADDED: * mc100lvel17 = MOTOROLA* ECL RECEIVER * qs3vh125 = QUALITY SEMICONDUCTOR* QUICKSWITCH * *************************************************** * .SUBCKT FBO GNDREF M2 ECL POW *THE FOLLOWING SETS UP VREF AS .66 POW NODE EM1 VREF GNDREF POW GNDREF .
R * Load elements R8 FBOQS ECL 24.9 R20 ECL VREF 51 C21 VREF GNDREF .1E-6 * Set up Minitek* connector nodes * Minitek* pad capacitance CMT1 M1 GNDREF 5.00E-13 CMT2 M2 GNDREF 5.
R * PWR LOAD MODEL LEVEL 1 * CREATED: NOVEMBER 22, 1999 * EXPANDED DOCUMENTATION: AUGUST 18, 2000 * * PINS: * GNDREF=GROUND * M2=MINITEK* BCKP CONN AT TARGET * * ADDITIONAL REQUIRED SUBCIRCUIT INCLUDED IN ITP700_PACKAGES.TXT * MINITEK* = ITP DPA HEADER MODEL * *************************************************** .SUBCKT PWR GNDREF M2 * Load elements RDIV M1 GNDREF 3000 * Setup Minitek* connector nodes * Minitek* pad capacitance CMT1 M1 GNDREF 5.00E-13 CMT2 M2 GNDREF 5.
R RMT10 M11 GNDREF 250 RMT11 M12 GNDREF 250 RMT12 M13 GNDREF 250 RMT13 M14 GNDREF 250 RMT14 M15 GNDREF 250 RMT15 M16 GNDREF 250 * Include Minitek* connector model X1 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 MINITEK* .ENDS PWR Package: **************************************************************** * Minitek* SPICE Subcircuit * BERG Electronics* * DCG1092* **************************************************************** .
R L33 5 6 4.116146E-10 L44 7 8 3.936342E-10 L55 9 10 3.936342E-10 L66 11 12 4.116146E-10 L77 13 14 4.116146E-10 L88 15 16 3.936342E-10 C11 2 0 4.240507E-14 C22 4 0 2.854559E-15 C33 6 0 2.854480E-15 C44 8 0 4.240475E-14 C55 10 0 4.240512E-14 C66 12 0 2.854593E-15 C77 14 0 2.854605E-15 C88 16 0 4.240524E-14 K12 L11 L22 6.355457E-01 C12 2 4 1.071086E-13 K13 L11 L33 4.534765E-01 C13 2 6 1.729760E-15 K14 L11 L44 3.313096E-01 C14 2 8 7.302546E-16 K15 L11 L55 5.582538E-01 C15 2 10 7.375378E-14 K16 L11 L66 5.
R K23 L22 L33 6.472215E-01 C23 4 6 1.065396E-13 K24 L22 L44 4.534765E-01 C24 4 8 1.735450E-15 K25 L22 L55 5.069099E-01 C25 4 10 7.892030E-15 K26 L22 L66 6.010506E-01 C26 4 12 6.228274E-14 K27 L22 L77 5.275090E-01 C27 4 14 7.815784E-15 K28 L22 L88 4.102210E-01 C28 4 16 1.065168E-16 K34 L33 L44 6.355457E-01 C34 6 8 1.071086E-13 K35 L33 L55 4.102210E-01 C35 6 10 1.065965E-16 K36 L33 L66 5.275090E-01 C36 6 12 7.815784E-15 K37 L33 L77 6.010506E-01 C37 6 14 6.228274E-14 K38 L33 L88 5.069099E-01 C38 6 16 7.
R K48 L44 L88 5.582538E-01 C48 8 16 7.375378E-14 K56 L55 L66 6.355457E-01 C56 10 12 1.071086E-13 K57 L55 L77 4.534765E-01 C57 10 14 1.729760E-15 K58 L55 L88 3.313096E-01 C58 10 16 7.301408E-16 K67 L66 L77 6.472215E-01 C67 12 14 1.065396E-13 K68 L66 L88 4.534765E-01 C68 12 16 1.735450E-15 K78 L77 L88 6.355457E-01 C78 14 16 1.071086E-13 .
