Intel® Pentium® 4 Processor on 90 nm Process Datasheet 2.80 GHz – 3.
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Contents 1 Introduction .................................................................................................................. 9 1.1 1.2 2 Electrical Specifications ........................................................................................ 13 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 3 Processor Pin Assignments ................................................................................ 39 Alphabetical Signals Reference ................................................
5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 6 Features ....................................................................................................................... 71 6.1 6.2 7 Power-On Configuration Options ........................................................................ 71 Clock Control and Low Power States.................................................................. 72 6.2.1 Normal State—State 1 ........................................................................... 72 6.2.
Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Datasheet Phase Lock Loop (PLL) Filter Requirements ...................................................... 16 VCC Static and Transient Tolerance for Loadline A............................................. 24 VCC Static and Transient Tolerance for Loadline B............................................. 26 VCC Overshoot Example Waveform.................................................................... 30 Processor Package Assembly...........
Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 References.......................................................................................................... 11 Core Frequency to FSB Multiplier Configuration................................................. 14 Voltage Identification Definition........................................................................... 15 FSB Pin Groups .......................................................................
Revision History Revision -001 -002 Description • Initial release Date February 2004 • Added specifications for 3.20 GHz processors with PRB = 1 April 2004 • Added ISGNT/ISLP specifications • Updated thermal diode specifications • Other changes marked with change bars -003 • Added specifications for 3.
Intel® Pentium® 4 Processor on 90 nm Process 2.80A/E GHz, 3E GHz, 3.20E GHz, and 3.40E GHz • Available at 2.80A/E GHz, 3E GHz, 3.20E GHz, and 3.
Introduction 1Introduction The Intel® Pentium® 4 processor on 90 nm process is a follow on to the Intel® Pentium® 4 processor in the 478-pin package with enhancements to the Intel NetBurst® microarchitecture. The Pentium 4 processor on 90 nm process uses Flip-Chip Pin Grid Array (FC-mPGA4) package technology, and plugs into a 478-pin surface mount, Zero Insertion Force (ZIF) socket, referred to as the mPGA478B socket.
Introduction 1.1 Terminology A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal is inverted.
Introduction 1.2 References Material and concepts available in the following documents may be beneficial when reading this document. Table 1. References Document ® Location http://developer.intel.com/design/ pentium4/specupdt/249199.htm Intel ® Pentium Intel ® 865G/865GV/865PE/865P Chipset Platform Design Guide http://developer.intel.com/design/ chipsets/designex/252518.htm Intel ® 875P Chipset Platform Design Guide http://developer.intel.com/design/ chipsets/designex/252527.
Introduction 12 Datasheet
Electrical Specifications 2 Electrical Specifications 2.1 Power and Ground Pins For clean on-chip power distribution, the processor has 85 VCC (power) and 179 VSS (ground) pins. All power pins must be connected to VCC, while all VSS pins must be connected to a system ground plane.The processor VCC pins must be supplied by the voltage determined by the VID (Voltage identification) pins. 2.
Electrical Specifications 2.2.3 FSB Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the processor core frequency is a multiple of the BCLK[1:0] frequency. No user intervention is necessary, and the processor will automatically run at the speed indicated on the package. The processor uses a differential clocking implementation. Table 2.
Electrical Specifications Table 3. VID5 Voltage Identification Definition VID4 VID3 VID2 VID1 VID0 VID VID5 VID4 VID3 VID2 VID1 VID0 VID 0 0 1 0 1 0 0.8375 0 1 1 0 1 0 1.2125 1 0 1 0 0 1 0.8500 1 1 1 0 0 1 1.2250 0 0 1 0 0 1 0.8625 0 1 1 0 0 1 1.2375 1 0 1 0 0 0 0.8750 1 1 1 0 0 0 1.2500 0 0 1 0 0 0 0.8875 0 1 1 0 0 0 1.2625 1 0 0 1 1 1 0.9000 1 1 0 1 1 1 1.2750 0 0 0 1 1 1 0.9125 0 1 0 1 1 1 1.
Electrical Specifications 2.3.1 Phase Lock Loop (PLL) Power and Filter VCCA and VCCIOPLL are power sources required by the PLL clock generators on the processor silicon. Since these PLLs are analog, they require low noise power supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O timings as well as internal core timings (i.e., maximum frequency). To prevent this degradation, these supplies must be low pass filtered from VCC.
Electrical Specifications 2.4 Reserved, Unused, and TESTHI Pins All RESERVED pins must remain unconnected. Connection of these pins to VCC, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a pin listing of the processor and the location of all RESERVED pins. For reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level.
Electrical Specifications 2.5 FSB Signal Groups The FSB signals have been combined into groups by buffer type. GTL+ input signals have differential input buffers that use GTLREF as a reference level. In this document, the term "GTL+ Input" refers to the GTL+ input group as well as the GTL+ I/O group when receiving. Similarly, "GTL+ Output" refers to the GTL+ output group as well as the GTL+ I/O group when driving.
Electrical Specifications Table 5.
Electrical Specifications 2.8 FSB Frequency Select Signals (BSEL[1:0]) The BSEL[1:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). Table 7 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset, and clock synthesizer. All agents must operate at the same frequency.
Electrical Specifications 2.9 Absolute Maximum and Minimum Ratings Table 8 specifies absolute maximum and minimum ratings. Within functional operation limits, functionality and long-term reliability can be expected. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected.
Electrical Specifications Table 9. Voltage and Current Specifications Symbol VID range Parameter VID Unit Notes1 1.400 V 2 See Table 10 and Figure 2 VID – ICC(max) * 1.45 mΩ V 3,4,5 See Table 11 and Figure 3 VID – ICC(max) * 1.45 mΩ V 3,4,5 A 6 A 7,8,10 Typ 1.250 VCC Loadline A processors VCC Max Min 3.20E GHz (PRB = 1) 3.40E GHz (PRB = 1) VCC Loadline B processors 2.80A/E GHz (PRB = 0) VCC 3E GHz (PRB = 0) 3.20E GHz (PRB = 0) 3.
Electrical Specifications 10. These parameters are based on design characterization and are not tested. Table 10. VCC Static and Transient Tolerance for Loadline A Voltage Deviation from VID Setting (V)1,2,3 Icc (A) Maximum Voltage Typical Voltage Minimum Voltage 0 0.000 -0.019 -0.038 5 -0.007 -0.027 -0.047 10 -0.015 -0.035 -0.055 15 -0.022 -0.043 -0.064 20 -0.029 -0.051 -0.072 25 -0.036 -0.058 -0.081 30 -0.044 -0.066 -0.089 35 -0.051 -0.074 -0.098 40 -0.058 -0.
Electrical Specifications Figure 2. VCC Static and Transient Tolerance for Loadline A Icc [A] 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 VID - 0.000 Vcc Maximum VID - 0.038 Vcc [V] VID - 0.076 VID - 0.114 VID - 0.152 Vcc Typical Vcc Minimum VID - 0.190 VID - 0.228 NOTES: 1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2.11. 2.
Electrical Specifications Table 11. VCC Static and Transient Tolerance for Loadline B Voltage Deviation from VID Setting (V)1,2,3 Icc (A) Maximum Voltage Typical Voltage Minimum Voltage 0 0.000 -0.025 -0.050 5 -0.007 -0.033 -0.059 10 -0.015 -0.041 -0.068 15 -0.022 -0.049 -0.077 20 -0.029 -0.058 -0.086 25 -0.036 -0.066 -0.095 30 -0.044 -0.074 -0.104 35 -0.051 -0.082 -0.113 40 -0.058 -0.090 -0.122 45 -0.065 -0.098 -0.131 50 -0.073 -0.106 -0.140 55 -0.080 -0.
Electrical Specifications Figure 3. VCC Static and Transient Tolerance for Loadline B Icc [A] 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 VID - 0.000 Vcc Maximum VID - 0.025 VID - 0.050 Vcc [V] VID - 0.075 VID - 0.100 VID - 0.125 VID - 0.150 Vcc Typical Vcc Minimum VID - 0.175 VID - 0.200 NOTES: 1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2.11. 2.
Electrical Specifications Table 12. GTL+ Signal Group DC Specifications Parameter Min Max Unit Notes1 VIL Input Low Voltage 0.0 GTLREF – (0.10 * VCC) V 2, 3 VIH Input High Voltage GTLREF + (0.10 * VCC) VCC V 3, 4 VOH Output High Voltage 0.90*VCC VCC V 3 IOL Output Low Current N/A VCC/[(0.50*RTT_MIN)+(RON_MIN)] A ILI Input Leakage Current N/A ± 200 µA 5 ILO Output Leakage Current N/A ± 200 µA 6 RON Buffer On Resistance 8 12 Ω Symbol NOTES: 1.
Electrical Specifications . Table 14. PWRGOOD and TAP Signal Group DC Specifications Symbol VHYS Parameter Input Hysteresis Min Max Unit Notes1, 2 200 350 mV 3 VT+ Input low to high threshold voltage 0.5 * (VCC + VHYS_MIN) 0.5 * (VCC + VHYS_MAX) V 4 VT- Input high to low threshold voltage 0.5 * (VCC – VHYS_MAX) 0.
Electrical Specifications . Table 17. BSEL [1:0] and VID[5:0] DC Specifications Symbol Parameter Max Unit Notes1 RON (BSEL) Buffer On Resistance 60 Ω 2 RON (VID) Buffer On Resistance 60 Ω 2 IOL Max Pin Current 8 mA ILO Output Leakage Current 200 µA 3.3 + 5% V VTOL Voltage Tolerance 3 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. These parameters are not tested and are based on design simulations. 3.
Electrical Specifications Figure 4. VCC Overshoot Example Waveform Example Overshoot Waveform Voltage (V) VID + 0.050 VOS VID TOS Time TOS: Overshoot time above VID VOS: Overshoot above VID NOTES: 1. VOS is measured overshoot voltage. 2. TOS is measured time duration above VID. 2.11.1 Die Voltage Validation Overshoot events from application testing on real processors must meet the specifications in Table 19 when measured across the VCC_SENSE and VSS_SENSE pins.
Package Mechanical Specifications 3 Package Mechanical Specifications 3.1 Package Mechanical Specifications The Pentium 4 processor on 90 nm process is in a Flip-Chip Pin Grid Array (FC-mPGA4) package that interfaces with the motherboard via a mPGA478B socket. The package consists of a processor core mounted on a substrate pin-carrier.
Package Mechanical Specifications 3.1.1 Package Mechanical Drawing The package mechanical drawings are shown in Figure 6 and Figure 7. The drawings include dimensions necessary to design a thermal solution for the processor. These dimensions include: • • • • • Package reference with tolerances (total height, length, width, etc.) IHS parallelism and tilt Pin dimensions Top-side and back-side component keep-out dimensions Reference datums All drawing dimensions are in mm [in].
Package Mechanical Specifications Figure 6.
Package Mechanical Specifications Figure 7.
Package Mechanical Specifications 3.1.2 Processor Component Keep-out Zones The processor may contain components on the substrate that define component keep-out zone requirements. A thermal and mechanical solution design must not intrude into the required keepout zones. Decoupling capacitors are typically mounted to either the topside or pin-side of the package substrate. See Figure 6 and Figure 7 for keep-out zones.
Package Mechanical Specifications 3.1.5 Package Insertion Specifications The processor can be inserted into and removed from a mPGA478B socket 15 times. The socket should meet the mPGA478B requirements detailed in the mPGA479, mPGA478A, mPGA478B, mPGA478C, and mPGA476 Socket Design Guidelines. 3.1.6 Processor Mass Specification The typical mass of the processor is 19 g [0.67 oz]. This mass [weight] includes all the components that are included in the package. 3.1.
Package Mechanical Specifications 3.1.9 Processor Pinout Coordinates Figure 9 shows the top view of the processor pin coordinates. The coordinates are referred to throughout the document to identify processor pins. . Figure 9.
Package Mechanical Specifications 38 Datasheet
Pin List and Signal Description 4 Pin List and Signal Description This chapter provides the processor pinout and signal description. 4.1 Processor Pin Assignments The pinout footprint is shown in Figure 10 and Figure 11. These figures represent the pinout arranged by pin number. Table 23 provides the pinout arranged alphabetically by signal name and Table 24 provides the pinout arranged numerically by pin number.
Pin List and Signal Description Figure 10.
Pin List and Signal Description Figure 11.
Pin List and Signal Description Table 23. Alphabetical Pin Assignment Pin Name 42 Pin # Signal Buffer Type Direction Table 23.
Pin List and Signal Description Table 23.
Pin List and Signal Description Table 23. Alphabetical Pin Assignment Pin Name 44 Pin # Signal Buffer Type Direction Table 23.
Pin List and Signal Description Table 23. Alphabetical Pin Assignment Pin Name Datasheet Pin # Signal Buffer Type Direction Table 23.
Pin List and Signal Description Table 23. Alphabetical Pin Assignment Pin Name 46 Pin # Signal Buffer Type Direction Table 23.
Pin List and Signal Description Table 23. Alphabetical Pin Assignment Pin Name Datasheet Pin # Signal Buffer Type Direction Table 23.
Pin List and Signal Description Table 24.
Pin List and Signal Description Table 24. Numerical Pin Assignment Pin # Datasheet Pin Name Signal Buffer Type Direction Table 24.
Pin List and Signal Description Table 24. Numerical Pin Assignment Pin # 50 Pin Name Signal Buffer Type Direction Table 24.
Pin List and Signal Description Table 24. Numerical Pin Assignment Pin # Datasheet Pin Name Signal Buffer Type Direction Table 24.
Pin List and Signal Description Table 24. Numerical Pin Assignment Pin # 52 Pin Name Signal Buffer Type Direction Table 24.
Pin List and Signal Description Table 24. Numerical Pin Assignment Pin # Datasheet Pin Name Signal Buffer Type Direction Table 24.
Pin List and Signal Description 4.2 Alphabetical Signals Reference Table 25. Signal Description (Page 1 of 8) Name Type Description 236-byte A[35:3]# Input/ Output A[35:3]# (Address) define a physical memory address space. In subphase 1 of the address phase, these pins transmit the address of a transaction. In subphase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of all agents on the processor FSB.
Pin List and Signal Description Table 25. Signal Description (Page 2 of 8) Name Type Description BINIT# (Bus Initialization) may be observed and driven by all processor FSB agents and, if used, must connect the appropriate pins of all such agents. If the BINIT# driver is enabled during power-on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future operation.
Pin List and Signal Description Table 25. Signal Description (Page 3 of 8) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor FSB agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period. D[63:0]# are latched from the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#.
Pin List and Signal Description Table 25. Signal Description (Page 4 of 8) Name DRDY# Type Input/ Output Description DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be de-asserted to insert idle clocks. This signal must connect the appropriate pins of all processor FSB agents. Data strobe used to latch in D[63:0]#.
Pin List and Signal Description Table 25. Signal Description (Page 5 of 8) Name IGNNE# Type Input Description IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is de-asserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in Control Register 0 (CR0) is set.
Pin List and Signal Description Table 25. Signal Description (Page 6 of 8) Name PROCHOT# PWRGOOD Type Description Input/ Output As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input, assertion of PROCHOT# by the system activates the TCC, if enabled.
Pin List and Signal Description Table 25. Signal Description (Page 7 of 8) Name SMI# Type Input Description SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, the processor saves the current state and enters System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler.
Pin List and Signal Description Table 25. Signal Description (Page 8 of 8) Name Type Description VCCIOPLL Input VCCIOPLL provides isolated power for internal processor FSB PLLs. Follow the guidelines for VCCA, and refer to the Intel® 865G/865GV/865PE/865P Chipset Platform Design Guide for complete implementation details. Output VCC_SENSE is an isolated low impedance connection to processor core power (VCC). It can be used to sense or measure voltage near the silicon with little noise.
Pin List and Signal Description 62 Datasheet
Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations 5.1 Processor Thermal Specifications The processor requires a thermal solution to maintain temperatures within operating limits as set forth in Section 5.1.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system.
Thermal Specifications and Design Considerations To determine a processor's case temperature specification based on the thermal profile, it is necessary to accurately measure processor power dissipation. Intel has developed a methodology for accurate power measurement that correlates to Intel test temperature and voltage conditions. Refer to the Intel® Pentium® 4 Processor on 90 nm Process Thermal Design Guidelines for the details of this methodology.
Thermal Specifications and Design Considerations Table 27. Thermal Profile Datasheet Power (W) Maximum Tc (°C) Power Maximum Tc (°C) 0 43.3 54 59.0 2 43.9 56 59.5 4 44.5 58 60.1 6 45.0 60 60.7 8 45.6 62 61.3 10 46.2 64 61.9 12 46.8 66 62.4 14 47.4 68 63.0 16 47.9 70 63.6 18 48.5 72 64.2 20 49.1 74 64.8 22 49.7 76 65.3 24 50.3 78 65.9 26 50.8 80 66.5 28 51.4 82 67.1 30 52.0 84 67.7 32 52.6 86 68.2 34 53.2 88 68.8 36 53.7 90 69.
Thermal Specifications and Design Considerations Figure 12. Thermal Profile 80.0 75.0 y = 0.29x + 43.3 70.0 Tcase (C) 65.0 60.0 55.0 50.0 45.0 40.0 35.0 0 10 20 30 40 50 60 70 80 90 100 Power (W) 5.1.2 Thermal Metrology The maximum and minimum case temperatures (TC) are specified in Table 27. These temperature specifications are meant to help ensure proper operation of the processor. Figure 13 illustrates where Intel recommends TC thermal measurements should be made.
Thermal Specifications and Design Considerations 5.2 Processor Thermal Features 5.2.1 Thermal Monitor The Thermal Monitor feature helps control the processor temperature by activating the TCC when the processor silicon reaches its maximum operating temperature. The TCC reduces processor power consumption as needed by modulating (starting and stopping) the internal processor core clocks. The Thermal Monitor feature must be enabled for the processor to be operating within specifications.
Thermal Specifications and Design Considerations 5.2.2 On-Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption. This mechanism is referred to as "On-Demand" mode and is distinct from the Thermal Monitor feature. On-Demand mode is intended as a means to reduce system level power consumption. Systems using the processor must not rely on software usage of this mechanism to limit the processor temperature.
Thermal Specifications and Design Considerations 5.2.4 THERMTRIP# Signal Pin Regardless of whether or not the Thermal Monitor feature is enabled, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in Table 25). At this point, the FSB signal THERMTRIP# will go active and stay active as described in Table 25.
Thermal Specifications and Design Considerations Table 28. Thermal Diode Parameters Symbol Parameter Min Typ Max Unit Notes 187 uA 1 IFW Forward Bias Current 11 n Diode Ideality Factor 1.0083 1.011 1.023 Series Resistance 3.242 3.33 3.594 RT 2, 3, 4, 5 Ω 2, 3, 6 NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. 2. Characterized at 75 °C. 3. Not 100% tested. Specified by design characterization. 4.
Features 6 Features This chapter contains power-on configuration options and clock control/low power state descriptions. 6.1 Power-On Configuration Options Several configuration options can be configured by hardware. The processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 30. The sampled information configures the processor for subsequent operation.
Features 6.2 Clock Control and Low Power States The processor allows the use of AutoHALT, Stop-Grant, and Sleep states to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. See Figure 14 for a visual representation of the processor low power states. 6.2.1 Normal State—State 1 This is the normal operating state for the processor. 6.2.
Features 6.2.3 Stop-Grant State—State 3 When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. Since the GTL+ signal pins receive power from the FSB, these pins should not be driven (allowing the level to return to VCC) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the FSB should be driven to the inactive state.
Features 6.2.5 Sleep State—State 5 The Sleep state is a very low power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be entered from Stop-Grant state. Once in the Stop-Grant state, the processor will enter the Sleep state upon the assertion of the SLP# signal. The SLP# pin should only be asserted when the processor is in the Stop Grant state.
Boxed Processor Specifications 7 Boxed Processor Specifications The processor will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed processor will be supplied with a cooling solution. This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed processor.
Boxed Processor Specifications 7.1 Mechanical Specifications 7.1.1 Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 15 shows a mechanical representation of the boxed processor. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling.
Boxed Processor Specifications Figure 17. Space Requirements for the Boxed Processor (Top View) 7.1.2 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 450 grams. See Chapter 5 and the Intel® Pentium® 4 Processor on 90 nm Process Thermal Design Guidelines for details on the processor weight and heatsink requirements.
Boxed Processor Specifications 7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly The boxed processor thermal solution requires a processor retention mechanism and a heatsink attach clip assembly to secure the processor and fan heatsink in the baseboard socket. The boxed processor will not ship with retention mechanisms but will ship with the heatsink attach clip assembly.
Boxed Processor Specifications Table 31. Fan Heatsink Power and Signal Specifications Description +12 V: 12 volt fan power supply Min Typ Max 10.2 12 13.8 V 740 mA IC: Fan current draw SENSE: SENSE frequency 2 Unit pulses per fan revolution Notes 1 NOTES: 1. Baseboard should pull this pin up to 5 V with a resistor. Figure 19. Baseboard Power Header Placement Relative to Processor Socket 7.
Boxed Processor Specifications boxed processor fan heatsink to operate properly, it is critical that the airflow provided to the fan heatsink is unimpeded. Airflow of the fan heatsink is into the center and out of the sides of the fan heatsink. Airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked. Blocking the airflow to the fan heatsink reduces the cooling efficiency and decreases fan life.
Boxed Processor Specifications 7.3.2 Variable Speed Fan The boxed processor fan operates at different speeds over a short range of internal chassis temperatures. This allows the processor fan to operate at a lower speed and noise level, while internal chassis temperatures are low. If the internal chassis temperature increases beyond a lower set point, the fan speed will rise linearly with the internal temperature until the higher set point is reached. At that point, the fan speed is at its maximum.
