Intel® Pentium® 4 Processor in the 478-Pin Package at 1.40 GHz, 1.50 GHz, 1.60 GHz, 1.70 GHz, 1.80 GHz, 1.90 GHz, and 2GHz Datasheet Product Features § § § § § § § § Available at 1.40, 1.50, 1.60, 1.70, 1.80, 1.
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Contents 1.0 Introduction .................................................................................................................. 7 1.1 1.2 2.0 Electrical Specifications ........................................................................................11 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 3.0 Package Load Specifications ..............................................................................50 Processor Insertion Specifications .........................
6.0 Thermal Specifications and Design Considerations ................................. 77 6.1 6.2 7.0 Features ....................................................................................................................... 81 7.1 7.2 7.3 8.0 8.3 8.4 Introduction ......................................................................................................... 87 Mechanical Specifications................................................................................... 88 8.2.
Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Datasheet Typical VCCIOPLL, VCCA and VSSA Power Distribution ..................................14 Phase Lock Loop (PLL) Filter Requirements .....................................................15 Vcc Static and Transient Tolerance1, 2, 3 ..........................................................22 AC Test Circuit ...............................................................................
Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 6 References ........................................................................................................... 9 Voltage Identification Definition .......................................................................... 13 System Bus Pin Groups ..................................................................................... 17 BSEL[1:0] Frequency Table for BCLK[1:0] ............
Introduction 1.0 Introduction The Intel® Pentium® 4 processor in the 478-pin package is a follow on to the Pentium® 4 processor in the 423-pin package with Intel® NetBurstTM microarchitecture. The Pentium 4 processor in the 478-pin package utilizes Flip-Chip Pin Grid Array (FC-PGA2) package technology, and plugs into a 478-pin surface mount, Zero Insertion Force (ZIF) socket, referred to as the mPGA478B socket.
Introduction Intel will be enabling support components for the Pentium 4 processor in the 478-pin package including heatsink, heat sink retention mechanism, and socket. Manufacturability is a high priority; hence, mechanical assembly can be completed from the top of the motherboard and should not require any special tooling. The enabled components for the 478-pin package will be similar but different from the enabled components for the 423-pin package due to package stackup differences.
Introduction • Retention mechanism —The structure mounted on the system board which provides support and retention of the processor heatsink. 1.2 References Material and concepts available in the following documents may be beneficial when reading this document: Table 1. References Document Order Number Intel® Pentium® 4 Processor in the 478-pin Package and Intel® 850 Chipset Platform Design Guide http://developer.intel.com/design/ pentium4/guides/249888.
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Electrical Specifications 2.0 Electrical Specifications 2.1 System Bus and GTLREF Most Pentium 4 processor in the 478-pin package system bus signals use Assisted Gunning Transceiver Logic (AGTL+) signalling technology. As with the Intel P6 family of microprocessors, this signalling technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates.
Electrical Specifications Failure to do so can result in timing violations or reduced lifetime of the component. For further information and design guidelines, refer to Table 1 for the appropriate Platform Design Guide, and the Intel® Pentium® 4 Processor VR-Down Design Guidelines. 2.3.1 VCC Decoupling Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR) and keep a low interconnect resistance from the regulator to the socket.
Electrical Specifications processor in the 423-pin package. If the processor socket is empty (VID[4:0] = 11111), or the voltage regulation circuit cannot supply the voltage that is requested, it must disable itself. See the Intel® Pentium® 4 Processor VR-Down Design Guidelines for more details. Power source characteristics must be guaranteed to be stable whenever the supply to the voltage regulator is stable. Table 2.
Electrical Specifications 2.4.1 Phase Lock Loop (PLL) Power and Filter VCCA and VCCIOPLL are power sources required by the PLL clock generators on the Pentium 4 processor in the 478-pin package silicon. Since these PLLs are analog in nature, they require quiet power supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O timings as well as internal core timings (i.e., maximum frequency). To prevent this degradation, these supplies must be low pass filtered from VCC.
Electrical Specifications . Figure 2. Phase Lock Loop (PLL) Filter Requirements 0.2 dB 0 dB -0.5 dB forbidden zone -28 dB forbidden zone -34 dB DC 1 Hz fpeak 1 MHz passband 66 MHz fcore high frequency band NOTES: 1. Diagram not to scale. 2. No specification for frequencies beyond fcore (core frequency). 3. fpeak, if existent, should be less than 0.05 MHz. 2.5 Reserved, Unused, and TESTHI Pins All RESERVED pins must remain unconnected.
Electrical Specifications TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die termination. Input and used outputs must be terminated on the system board. Unused outputs may be terminated on the system board or left unconnected. Note that leaving unused output unterminated may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing.
Electrical Specifications Table 3. System Bus Pin Groups Signal Group Signals1 Type AGTL+ Common Clock Input Synchronous to BCLK[1:0] BPRI#, DEFER#, RESET#2, RS[2:0]#, RSP#, TRDY# AGTL+ Common Clock I/O Synchronous to BCLK[1:0] AP[1:0]#, ADS#, BINIT#, BNR#, BPM[5:0]#2, BR0#2, DBSY#, DP[3:0]#, DRDY#, HIT#, HITM#, LOCK#, MCERR# Signals REQ[4:0]#, AGTL+ Source Synchronous I/O AGTL+ Strobes Synchronous to assoc.
Electrical Specifications 2.7 Asynchronous GTL+ Signals The Pentium 4 processor in the 478-pin package does not utilize CMOS voltage levels on any signals that connect to the processor. As a result, legacy input signals such as A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#, SLP#, and STPCLK# utilize GTL+ input buffers. Legacy output FERR# and other non-AGTL+ signals (THERMTRIP# and PROCHOT#) utilize GTL+ output buffers.
Electrical Specifications 2.10 Maximum Ratings Table 5 lists the processor’s maximum environmental stress ratings. Functional operation at the absolute maximum and minimum is neither implied nor guaranteed. The processor should not receive a clock while subjected to these conditions. Functional operating parameters are listed in the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability.
Electrical Specifications Table 6. Voltage and Current Specifications Symbol Parameter Min Typ Max Notes1, 9 Unit VCC for processor at VCC 1.40 GHz 1.585 1.50 GHz10 1.580 1.60 GHz 1.570 1.70 GHz10 1.565 1.80 GHz 1.560 1.90 GHz 1.545 2 GHz 1.540 Refer to Table 7 and Figure 3 V 2, 3, 4, 5 ICC for processor at ICC 1.40 GHz 41.3 1.50 GHz10 43.5 1.60 GHz 45.9 1.70 GHz10 48.1 1.80 GHz 50.4 1.90 GHz 55.2 2 GHz 57.4 A ICC Stop-Grant 1.40 GHz 12.3 1.50 GHz10 12.
Electrical Specifications Table 7. Vcc Static and Transient Tolerance Voltage Deviation from VID Setting (V)1, 2, 3 Icc (A) Maximum Typical Minimum 0 0.000 -0.025 -0.050 5 -0.010 -0.037 -0.064 10 -0.019 -0.048 -0.078 15 -0.029 -0.060 -0.092 20 -0.038 -0.072 -0.106 25 -0.048 -0.083 -0.120 30 -0.057 -0.095 -0.133 35 -0.067 -0.107 -0.147 40 -0.076 -0.119 -0.161 45 -0.085 -0.130 -0.175 50 -0.095 -0.142 -0.189 55 -0.105 -0.154 -0.203 60 -0.114 -0.165 -0.
Electrical Specifications Figure 3. Vcc Static and Transient Tolerance1, 2, 3 1.800 1.750 1.700 Vcc [V] Vcc Maximum 1.650 Vcc Typical 1.600 Vcc Minimum 1.550 1.500 1.450 0 10 20 30 40 50 60 70 80 Icc Load [A] NOTES: 1. The loadline specification includes both static and transient limits. 2. This loadline specification applies to processors with a VID setting of 1.75 V. 3. The loadlines specify voltage limits at the die measured at the VCC_sense and VSS_sense pins.
Electrical Specifications Table 8. System Bus Differential BCLK Specifications Symbol Parameter Min Typ Max Unit Figure Notes1 VL Input Low Voltage -0.150 0.000 N/A V 6 VH Input High Voltage 0.660 0.710 0.850 V 6 VCROSS(abs) Absolute Crossing Point 0.250 N/A 0.550 V 6, 7 2, 3, 8 VCROSS(rel) Relative Crossing Point V 6, 7 2, 3, 8, 9 ∆VCROSS Range of Crossing Points N/A N/A 0.140 V 6, 7 2, 10 VOV Overshoot N/A N/A VH + 0.3 V 6 4 0.250 + 0.5(VHavg - 0.
Electrical Specifications Table 10. Asynchronous GTL+ Signal Group DC Specifications Symbol Parameter Min Max Unit Notes1 VIL Input Low Voltage 0.0 GTLREF-0.100 3 VIH Input High Voltage GTLREF+0.100 VCC 4, 5, 7 VOH Output High Voltage VCC V 2, 5, 7 IOL Output Low Current 64 mA 8, 9 ILI Input Leakage Current N/A ± 100 µA ILO Output Leakage Current N/A ± 100 µA RON Buffer On Resistance 5 11 Ω 6 NOTES: 1.
Electrical Specifications 2.12 AGTL+ System Bus Specifications Routing topology recommendations may be found in the appropriate Platform Design Guide as referenced in Table 1. Termination resistors are not required for most AGTL+ signals, as these are integrated into the processor silicon. Valid high and low levels are determined by the input buffers which compare a signal’s voltage with a reference voltage called GTLREF (known as VREF in previous documentation). Table 12 lists the GTLREF specifications.
Electrical Specifications Table 13. System Bus Differential Clock Specifications T# Parameter Min Nom System Bus Frequency T1: BCLK[1:0] Period 10.0 T2: BCLK[1:0] Period Stability Max Unit Notes1 Figure 100 MHz 10.2 ns 6 2 200 ps 6 3, 4 T3: BCLK[1:0] High Time 3.94 5 6.12 ns 6 T4: BCLK[1:0] Low Time 3.94 5 6.12 ns 6 T5: BCLK[1:0] Rise Time 175 700 ps 6 5 T6: BCLK[1:0] Fall Time 175 700 ps 6 5 NOTES: 1.
Electrical Specifications Table 15. System Bus Source Synch AC Specifications AGTL+ Signal Group T# Parameter Min Typ Max Unit Figure Notes1,2,3,4 1.20 ns 10, 11 5 T20: Source Synchronous Data Output Valid Delay (first data/address only) 0.20 T21: TVBD: Source Synchronous Data Output Valid Before Strobe 0.85 ns 11 5, 8 T22: TVAD: Source Synchronous Data Output Valid After Strobe 0.85 ns 11 5, 8 T23: TVBA: Source Synchronous Address Output Valid Before Strobe 1.
Electrical Specifications Table 16. Miscellaneous Signals AC Specifications T# Parameter Min T35: Asynch GTL+ Input Pulse Width 2 T36: PWRGOOD to RESET# de-assertion time 1 T37: PWRGOOD Inactive Pulse Width T38: PROCHOT# pulse width Max Unit Figure Notes1,2,3,6 BCLKs 10 ms 12 10 BCLKs 12 4 500 us 14 5 s 13 T39: THERMTRIP# Assertion until Vcc removal 0.5 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2.
Electrical Specifications Table 18. TAP Signals AC Specifications Parameter Notes1,2,3,9 Max Unit Figure ns 5 T56: TCK Rise Time 9.5 ns 5 4 T57: TCK Fall Time 9.5 ns 5 4 T58: TMS, TDI Rise Time 8.5 ns 5 4 ns 5 T55: TCK Period Min 60.0 T59: TMS, TDI Fall Time T61: TDI, TMS Setup Time 8.5 0 T62: TDI, TMS Hold Time T63: TDO Clock to Output Delay T64: TRST# Assert Time 0.5 4 ns 5, 7 3 ns 5, 7 3.5 ns 6 2 TCK 14 8 NOTES: 1.
Electrical Specifications Figure 4. AC Test Circuit VCC VCC Rload 2.4nH 600 mils, 42 ohms, 169 ps/in 1.2pF AC Timings test measurements made here. Rload = 50 ohms Figure 5. TCK Clock Waveform Tr *V2 *V3 CLK *V1 T f Tp Tr = T56, T58 (Rise Time) Tf = T57, T59 (Fall Time) Tp = T55 (Period) V1, V2: For rise and fall times, TCK is measured between 20% to 80% points on the waveform. V3: 30 TCK is referenced to 0.5 * Vcc.
Electrical Specifications . Figure 6. Differential Clock Waveform Tph Overshoot VH BCLK1 Rising Edge Ringback Crossing Voltage Threshold Region Crossing Voltage Ringback Margin Falling Edge Ringback, BCLK0 VL Undershoot Tpl Tp Tp = T1 (BCLK[1:0] period) T2 = BCLK[1:0] Period stability (not shown) Tph =T3 (BCLK[1:0] pulse high time) Tpl = T4 (BCLK[1:0] pulse low time) T5 = BCLK[1:0] rise time through the threshold region T6 = BCLK[1:0] fall time through the threshold region Figure 7.
Electrical Specifications Figure 8. System Bus Common Clock Valid Delay Timings T0 T1 T2 BCLK1 BCLK0 TP Common Clock Signal (@ driver) valid valid TQ Common Clock Signal (@ receiver) TR valid TP = T10: TCO (Data Valid Output Delay) TQ = T11: TSU (Common Clock Setup) TR = T12: TH (Common Clock Hold Time) Figure 9.
Electrical Specifications Figure 10. Source Synchronous 2X (Address) Timings T1 2.5 ns 5.0 ns T2 7.5 ns BCLK1 BCLK0 TP ADSTB# (@ driver) TR TH A# (@ driver) valid TJ TH TJ valid TS ADSTB# (@ receiver) TK A# (@ receiver) valid valid TN TM TH = T23: Source Sync. Address Output Valid Before Address Strobe TJ = T24: Source Sync. Address Output Valid After Address Strobe TK = T27: Source Sync. Input Setup to BCLK TM = T26: Source Sync. Input Hold Time TN = T25: Source Sync.
Electrical Specifications Figure 11. Source Synchronous 4X Timings T0 T1 2.5 ns 5.0 ns T2 7.5 ns BCLK1 BCLK0 DSTBp# (@ driver) TH DSTBn# (@ driver) TA TB TA TD D# (@ driver) DSTBp# (@ receiver) TJ DSTBn# (@ receiver) TC D# (@ receiver) TE TG TE TG TA = T21: Source Sync. Data Output Valid Delay Before Data Strobe TB = T22: Source Sync. Data Output Valid Delay After Data Strobe TC = T27: Source Sync. Setup Time to BCLK TD = T30: Source Sync.
Electrical Specifications Figure 13. THERMTRIP# Power Down Sequence T39 THERMTRIP# Vcc T39 < 0.5 seconds Note: THERMTRIP# is undefined when RESET# is active Figure 14. Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform V Tq T = T38 (PROCHOT# Pulse Width), V=GTLREF q T64 (TRST# Pulse Width), V=0.5*Vcc Figure 15. TAP Valid Delay Timing Waveform TCK V Tx Signal Ts Th V Valid Tx = T63 (Valid Time) Ts = T61 (Setup Time) Th = T62 (Hold Time) V = 0.
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System Bus Signal Quality Specifications 3.0 System Bus Signal Quality Specifications Source synchronous data transfer requires the clean reception of data signals and their associated strobes. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage swing will adversely affect system timings. Ringback and signal nonmonotinicity cannot be tolerated since these phenomena may inadvertently advance receiver state machines.
System Bus Signal Quality Specifications Table 19. BCLK Signal Quality Specifications Parameter Min Max Unit Figure BCLK[1:0] Overshoot N/A 0.30 V 16 BCLK[1:0] Undershoot N/A 0.30 V 16 BCLK[1:0] Ringback Margin 0.20 N/A V 16 BCLK[1:0] Threshold Region N/A 0.20 V 16 Notes1 2 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all Pentium® 4 processor in the 478-pin package frequencies. 2.
System Bus Signal Quality Specifications Table 20. Ringback Specifications for AGTL+ and Asynchronous GTL+ Signal Groups Transition Maximum Ringback (with Input Diodes Present) Unit Figure All Signals 0→1 GTLREF + 0.100 V 17 1,2,3,4,5,6,7 All Signals 1→0 GTLREF - 0.100 V 18 1,2,3,4,5,6,7 Signal Group Notes NOTES: 1. All signal integrity specifications are measured at the processor silicon. 2.
System Bus Signal Quality Specifications Figure 18. High-to-Low System Bus Receiver Ringback Tolerance V CC +100 mV GTLREF -100 mV Noise Margin V SS Figure 19. Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers Vcc Threshold Region to switch receiver to a logic 1. Vt+ (max) Vt+ (min) 0.
System Bus Signal Quality Specifications Figure 20. High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers Vcc Allowable Ringback Vt+ (min) 0.5 * Vcc Vt- (max) Vt- (min) Threshold Region to switch receiver to a logic 0. Vss 3.3 System Bus Signal Quality Specifications and Measurement Guidelines 3.3.1 Overshoot/Undershoot Guidelines Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high voltage (or below VSS) as shown in Figure 21.
System Bus Signal Quality Specifications 3.3.2 Overshoot/Undershoot Magnitude Magnitude describes the maximum potential difference between a signal and its voltage reference level. For the Pentium 4 processor in the 478-pin package both are referenced to VSS. It is important to note that overshoot and undershoot conditions are separate and their impact must be determined independently.
System Bus Signal Quality Specifications Note 3: Activity factor for source synchronous (4x) signals is referenced to DSTBP[3:0]# and DSTBN[3:0]#. 3.3.5 Reading Overshoot/Undershoot Specification Tables The overshoot/undershoot specification for the Pentium 4 processor in the 478-pin package is not a simple single value. Instead, many factors are needed to determine the over/undershoot specification.
System Bus Signal Quality Specifications Note: The following notes apply to Table 22 through Table 25. 1. Absolute Maximum Overshoot magnitude of 2.3 V must never be exceeded. 2. Absolute Maximum Overshoot is measured relative to VSS, Pulse Duration of overshoot is measured relative to VCC. 3. Absolute Maximum Undershoot and Pulse Duration of undershoot is measured relative to VCC. 4. Ringback below VCC cannot be subtracted from overshoots/undershoots. 5.
System Bus Signal Quality Specifications Table 23. Source Synchronous (200 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance Absolute Maximum Overshoot (V) Absolute Maximum Undershoot (V) Pulse Duration (ns) AF = 1 Pulse Duration (ns) AF = 0.1 Pulse Duration (ns) AF = 0.01 2.30 -0.585 0.12 1.2 10.0 2.25 -0.535 0.22 2.2 10.0 2.20 -0.485 0.44 4.4 10.0 2.15 -0.435 0.82 8.2 10.0 2.10 -0.385 1.5 10.0 10.0 2.05 -0.335 2.7 10.0 10.0 2.00 -0.285 5.0 10.0 10.0 1.95 -0.
System Bus Signal Quality Specifications Table 25. Asynchronous GTL+, PWRGOOD and TAP Signal Groups Overshoot/Undershoot Tolerance Absolute Maximum Overshoot (V) Absolute Maximum Undershoot (V) Pulse Duration (ns) AF = 1 Pulse Duration (ns) AF = 0.1 Pulse Duration (ns) AF = 0.01 2.30 -0.585 0.72 7.2 60.0 2.25 -0.535 1.32 13.2 60.0 2.20 -0.485 2.64 26.4 60.0 2.15 -0.435 4.92 49.2 60.0 2.10 -0.385 9.0 60.0 60.0 2.05 -0.335 16.2 60.0 60.0 2.00 -0.285 30.0 60.0 60.0 1.
Package Mechanical Specifications 4.0 Package Mechanical Specifications The Pentium 4 processor in the 478-pin package is packaged in a Flip-Chip Pin Grid Array (FC-PGA2) package. Components of the package include an integrated heat spreader (IHS), processor core, and the substrate which is the pin carrier. Mechanical specifications for the processor are given in this section. See Section 1.1 for a terminology listing.
Package Mechanical Specifications Figure 23. Intel® Pentium® 4 Processor in the 478-Pin Package Table 26. Description Table for Processor Dimensions mm Code Letter Notes 1 Min Max A1 2.266 2.378 2.490 A2 0.980 1.080 1.180 B1 30.800 31.000 31.200 B2 30.800 31.000 31.200 C1 33.000 Includes Placement Tolerance C2 33.000 Includes Placement Tolerance D 34.900 35.000 35.100 D1 31.500 31.750 32.000 G1 13.970 Keep-In Zone Dimension G2 13.970 Keep-In Zone Dimension G3 1.
Package Mechanical Specifications Figure 24 details the keep-In specification for pin-side components. The Pentium 4 processor in the 478-pin package may contain pin side capacitors mounted to the processor package. Figure 26 details the flatness and tilt specifications for the IHS. Tilt is measured with the reference datum set to the bottom of the processor interposer. Figure 24. Processor Cross-Section and Keep-In FCPGA 2 IHS Substrate 1.25mm 13.
Package Mechanical Specifications Figure 26. IHS Flatness Specification IHS SUBSTRATE NOTES: 1. Flatness is specific as overall, not per unit of length. 2. All dimensions are in mm. 4.1 Package Load Specifications Table 27 provides dynamic and static load specifications for the Pentium 4 processor in the 478-pin package IHS. These mechanical load limits should not be exceeded during heatsink assembly, mechanical stress testing, or standard drop and shipping conditions.
Package Mechanical Specifications 4.2 Processor Insertion Specifications The Pentium 4 processor in the 478-pin package can be inserted and removed 15 times from a mPGA478B socket meeting the Intel® Pentium® 4 Processor 478-Pin Socket (mPGA478B) Design Guidelines document. 4.3 Processor Mass Specifications Table 28 specifies the processor’s mass. This includes all components which make up the entire processor product. Table 28.
Package Mechanical Specifications 4.6 Processor Pin-Out Coordinates Figure 28.
Pin Listing and Signal Definitions 5.0 Pin Listing and Signal Definitions 5.1 Intel® Pentium® 4 Processor in the 478-Pin Package Pin Assignments Section 5.1 contains the pinlist for the Pentium 4 processor in the 478-pin package in Table 30 and Table 31. Table 30 is a listing of all processor pins ordered alphabetically by pin name. Table 31 is also a listing of all processor pins but ordered by pin number.
Pin Listing and Signal Definitions Table 30. Pin Listing by Pin Name Table 30.
Pin Listing and Signal Definitions Table 30. Pin Listing by Pin Name Pin Name Pin Number Signal Buffer Type Table 30.
Pin Listing and Signal Definitions Table 30. Pin Listing by Pin Name Pin Name Pin Number Signal Buffer Type Table 30.
Pin Listing and Signal Definitions Table 30. Pin Listing by Pin Name Pin Name Pin Number Signal Buffer Type Table 30.
Pin Listing and Signal Definitions Table 30. Pin Listing by Pin Name Pin Name Pin Number Signal Buffer Type Table 30.
Pin Listing and Signal Definitions Table 30. Pin Listing by Pin Name Pin Name Pin Number Signal Buffer Type Table 30.
Pin Listing and Signal Definitions Table 30.
Pin Listing and Signal Definitions Table 31. Pin Listing by Pin Number Table 31.
Pin Listing and Signal Definitions Table 31. Pin Listing by Pin Number Pin Number Pin Name Signal Buffer Type Direction Table 31.
Pin Listing and Signal Definitions Table 31. Pin Listing by Pin Number Pin Number Pin Name Signal Buffer Type Direction Table 31.
Pin Listing and Signal Definitions Table 31. Pin Listing by Pin Number Pin Number Pin Name Signal Buffer Type Direction Table 31.
Pin Listing and Signal Definitions Table 31. Pin Listing by Pin Number Pin Number Pin Name Signal Buffer Type Direction Table 31.
Pin Listing and Signal Definitions Table 31. Pin Listing by Pin Number Pin Number Pin Name Signal Buffer Type N21 VSS Power/Other N22 D#[33] Source Synch N23 D#[36] Source Synch Direction Table 31.
Pin Listing and Signal Definitions Table 31.
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Pin Listing and Signal Definitions 5.2 Alphabetical Signals Reference Table 32. Signal Description (Sheet 1 of 8) Name Type Description 36 A[35:3]# Input/ Output A[35:3]# (Address) define a 2 -byte physical memory address space. In subphase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of all agents on the Pentium 4 processor in the 478-pin package system bus.
Pin Listing and Signal Definitions Table 32. Signal Description (Sheet 2 of 8) Name Type Description BINIT# (Bus Initialization) may be observed and driven by all processor system bus agents and if used, must connect the appropriate pins of all such agents. If the BINIT# driver is enabled during power-on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future operation.
Pin Listing and Signal Definitions Table 32. Signal Description (Sheet 3 of 8) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor system bus agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period.
Pin Listing and Signal Definitions Table 32. Signal Description (Sheet 4 of 8) Name DRDY# Type Input/ Output Description DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of all processor system bus agents. Data strobe used to latch in D[63:0]#.
Pin Listing and Signal Definitions Table 32. Signal Description (Sheet 5 of 8) Name INIT# Type Input Description INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion.
Pin Listing and Signal Definitions Table 32. Signal Description (Sheet 6 of 8) Name PWRGOOD Type Input Description PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. ‘Clean’ implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification.
Pin Listing and Signal Definitions Table 32. Signal Description (Sheet 7 of 8) Name SMI# Type Input Description SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, the processor saves the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler.
Pin Listing and Signal Definitions Table 32. Signal Description (Sheet 8 of 8) Name Type Description VCCSENSE Output VCCSENSE is an isolated low impedance connection to processor core power (VCC). It can be used to sense or measure power near the silicon with little noise. VCCVID Input VID[4:0] VSSA VSSSENSE 76 Output Input Output There is no imput voltage requirement for VCCVID for designs intended to support only the Pentium 4 processor in the 478-pin package.
Thermal Specifications and Design Considerations 6.0 Thermal Specifications and Design Considerations The Pentium 4 processor in the 478-pin package uses an integrated heat spreader (IHS) for heatsink attachment which is intended to provide for multiple types of thermal solutions. This section will provide data necessary for development of a thermal solution. See Figure 29 for an exploded view of an example Pentium 4 processor in the 478-pin package thermal solution. This is for illustration purposes.
Thermal Specifications and Design Considerations Note: The processor is either shipped by itself or with a heatsink for boxed processors. See Chapter 8.0 for details on boxed processors. Figure 29.
Thermal Specifications and Design Considerations 6.1 Thermal Specifications Table 33 specifies the thermal design power dissipation envelope for Pentium 4 processor in the 478-pin package. Analysis indicates that real applications are unlikely to cause the processor to consume the maximum possible power consumption. Intel recommends that system thermal designs target the “Thermal Design Power” indicated in Table 33 instead of “Max Processor Power.” The Thermal Monitor feature (refer to Section 7.
Thermal Specifications and Design Considerations 6.2.2 Measurements For Thermal Specifications 6.2.2.1 Processor Case Temperature Measurement The maximum and minimum case temperature (TCASE) for the Pentium 4 processor in the 478-pin package is specified in Table 33. This temperature specification is meant to ensure correct and reliable operation of the processor. Figure 30 illustrates where Intel recommends TCASE thermal measurements should be made. Figure 30.
Features 7.0 Features 7.1 Power-On Configuration Options Several configuration options can be configured by hardware. The Pentium 4 processor in the 478-pin package samples the hardware configuration at reset, on the active-toinactive transition of RESET#. For specifications on these options, please refer to Table 34. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset.
Features The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the AutoHALT Power Down state. See the Intel Architecture Software Developer's Manual, Volume III: System Programmer's Guide for more information. The system can generate a STPCLK# while the processor is in the AutoHALT Power Down state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state.
Features Since the AGTL+ signal pins receive power from the system bus, these pins should not be driven (allowing the level to return to VCC) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the system bus should be driven to the inactive state. BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be latched and can be serviced by software upon exit from the Stop Grant state.
Features If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset itself, ignoring the transition through Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP# and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the processor correctly executes the Reset sequence.
Features Thermal Monitor controls the processor temperature by modulating the internal processor core clocks. The processor clocks are modulated when the TCC is activated. Thermal Monitor uses two modes to activate the TCC: Automatic mode and On-Demand mode. Automatic mode is required for the processor to operate within specifications and must first be enabled via BIOS.
Features 7.3.1 Thermal Diode The Pentium 4 processor in the 478-pin package incorporates an on-die thermal diode. A thermal sensor located on the system board may monitor the die temperature of the Pentium 4 processor in the 478-pin package for thermal management/long term die temperature change purposes. Table 35 and Table 36 provide the diode parameter and interface specifications.
Boxed Processor Specifications 8.0 Boxed Processor Specifications 8.1 Introduction The Pentium 4 processor in the 478-pin package will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from motherboards and standard components. The boxed Pentium 4 processor in the 478-pin package will be supplied with a cooling solution.
Boxed Processor Specifications 8.2 Mechanical Specifications 8.2.1 Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed Pentium 4 processor in the 478-pin package. The boxed processor will be shipped with an unattached fan heatsink. Figure 32 shows a mechanical representation of the boxed Pentium 4 processor in the 478-pin package. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling.
Boxed Processor Specifications Figure 34. Top View Space Requirements for the Boxed Processor 8.2.2 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 450 grams. See Chapter 6.0 and the Intel® Pentium® 4 Processor in the 478-pin Package Thermal Design Guidelines for details on the processor weight and heatsink requirements. 8.2.
Boxed Processor Specifications Note: The processor retention mechanism based on the Intel reference design should be used, to ensure compatibility with the heatsink attach clip assembly and the boxed processor thermal solution. The heatsink attach clip assembly is latched to the retention tab features at each corner of the retention mechanism. 8.3 Electrical Requirements 8.3.1 Fan Heatsink Power Supply The boxed processor's fan heatsink requires a +12V power supply.
Boxed Processor Specifications Table 37. Fan Heatsink Power and Signal Specifications Description +12V: 12 volt fan power supply Min 10.2 Typ 12 IC: Fan current draw SENSE: SENSE frequency 2 Max Unit 13.8 V 740 mA pulses per fan revolution Notes 1 NOTE: 1. Motherboard should pull this pin up to VCC with a resistor. Figure 36. MotherBoard Power Header Placement Relative to Processor Socket 8.
Boxed Processor Specifications 8.4.1 Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink. However, meeting the processor's temperature specification is also function of the thermal design of the entire system, and ultimately the responsibility of the system integrator. The processor temperature specification is found in Chapter 6.0 of this document.
Boxed Processor Specifications Figure 38. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view) 8.4.2 Variable Speed Fan The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures. This allows the processor fan to operate at a lower speed and noise level, while internal chassis temperatures are low.
Boxed Processor Specifications Table 38. Boxed Processor Fan Heatsink Set Points Boxed Processor Fan Heatsink Set Point (ºC) Boxed Processor Fan Speed Notes 33 When the internal chassis temperature is below or equal to this set point, the fan operates at its lowest speed. Recommended maximum internal chassis temperature for nominal operating environment. 40 When the internal chassis temperature is at this point, the fan operates between its lowest and highest speeds.
Debug Tools Specifications 9.0 Debug Tools Specifications Please refer to the ITP700 Debug Port Design Guide, and the appropriate Platform Design Guide for information regarding debug tools specifications. 9.1 Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging Pentium 4 processor in the 478-pin package systems.
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Intel® Pentium® 4 Processor in the 478-pin Package A A10#...........................................................................81 A15#...........................................................................81 A20M# .......................................................................16 definition of ........................................................69 A7#.............................................................................81 A9#.......................................................
Intel® Pentium® 4 Processor in the 478-pin Package I IERR# definition of ........................................................72 IGNNE#.....................................................................16 definition of ........................................................72 IHS.See also Integrated heat spreader INIT# ...................................................................81, 83 definition of ........................................................73 input buffers........................
Intel® Pentium® 4 Processor in the 478-pin Package T TCK definition of ........................................................75 TDI definition of ........................................................75 TDO definition of ........................................................75 Termination resistors .................................................25 TESTHI......................................................................15 definition of ........................................................
Intel® Pentium® 4 Processor in the 478-pin Package 100 Datasheet
