Intel® Pentium® 4 Processor Specification Update August 2008 Revision 071 Document Number: 249199-071
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Contents Preface............................................................................................................................. 9 Summary Tables of Changes.............................................................................................. 11 General Information ......................................................................................................... 21 Identification Information .........................................................................................
Revision History Revision Date -001 • Initial Release November 2000 -002 • Added errata numbers N41-N44. December 2000 -003 • Updated Intel Pentium 4 Processor Identification Information. Updated erratum N40. Added errata N45 through N46. January 2001 -004 • Added errata N47. February 2001 -005 • Updated the processor identification information table.
Revision Description Date -018 • Added Documentation Change N4. January 2002 -019 • Added errata N60 and N61. February 2002 -020 • Added Documentation Change N5 -021 • Added errata N62 and N63. Removed Documentation Changes, Specification Clarifications, and Specification Changes that have been incorporated into documentation. Added Specification Clarifications N1 – N5. April 2002 -022 • Updated erratum N37. Added errata N64. Added Specification Change N1 to N3.
Revision Description -039 • Added Errata N76 and N77. -040 • Added Erratum N78 and Updated Erratum N69. Date July 2003 August 2003 • Added N2 to specification changes. -041 • Added Errata N79 to N82. -042 • Added Erratum N83. -043 • Release for launch of Intel® Pentium® 4 Processor Extreme Edition Supporting Hyper-Threading Technology. September 2003 October 2003 November 2003 • Added Erratum N84 Added S-Spec number under identification information table.
Revision Description Date micron process in 775-LGA package -051 o Added Figure 5 o Added Datasheet information and its link o Added S-spec number SL7GD • Added S-Spec number under identification information table Aug 2004 • Updated Summary Tables of Changes (Errata N16, N51, N56, N69, N79, N84, N85 and N92) • Modified erratum N69, and added erratum N92 -052 • Updated Figure 7 diagram -053 • Added Errata N93-95 -054 • Updated processor identification table, and added Errata N9697 -055 •
Revision Description Date -069 • Updated Summary Table of Changes. May 2007 -070 • Updated Summary Table of Changes.
Preface Preface This document is an update to the specifications contained in the documents listed the following Affected Documents/Related Documents table. It is a compilation device and document errata and specification clarifications and changes, and intended for hardware system manufacturers and for software developers applications, operating system, and tools.
Preface Document Title and Link Architecture Intel® 64 and IA-32 Intel Architectures Software Developer's Manual Volume 2A: Instruction Set Reference, A-M Intel® 64 and IA-32 Intel Architectures Software Developer's Manual Volume 2B: Instruction Set Reference, N-Z Intel® 64 and IA-32 Intel Architectures Software Developer's Manual Volume 3A: System Programming Guide Intel® 64 and IA-32 Intel Architectures Software Developer's Manual Volume 3B: System Programming Guide Nomenclature Errata are design defec
Summary Tables of Changes Summary Tables of Changes The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed MCH steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
Summary Tables of Changes 12 E= Intel® Pentium® III processor F= Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor I= Dual-Core Intel® Xeon® processor 5000 series J= 64-bit Intel® Xeon® processor MP with 1MB L2 cache K= Mobile Intel® Pentium® III processor L= Intel® Celeron® D processor M= Mobile Intel® Celeron® processor N= Intel® Pentium® 4 processor O= Intel® Xeon® processor MP P= Intel ® Xeon® processor Q= Mobile Intel® Pentium® 4 processor supporting Hyper
Summary Tables of Changes AJ = Quad-Core Intel® Xeon® processor 5300 series AK = Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 Quad processor Q6000 sequence AL = Dual-Core Intel® Xeon® processor 7100 series AM = Intel® Celeron® processor 400 sequence AN = Intel® Pentium® dual-core processor AO = Quad-Core Intel® Xeon® processor 3200 series AP = Dual-Core Intel® Xeon® processor 3000 series AQ = Intel® Pentium® dual-core desktop processor E2000 sequence AR = Int
Summary Tables of Changes No.
Summary Tables of Changes No.
Summary Tables of Changes No. B2 C1 D0 E0 B0 C1 D1 M0 Plan ERRATA as expected Fixed Processor may Timeout Waiting for a Device to Respond after ~0.
Summary Tables of Changes No.
Summary Tables of Changes No.
Summary Tables of Changes No.
Summary Tables of Changes No.
General Information General Information Figure 1 Intel® Pentium® 4 Processor in the 423-Pin Package and Boxed Pentium 4 Processor in the 423-Pin Package Markings Frequency/Cache/Bus/Voltage Intel® pentium®bbb 2-D Matrix Mark S-Spec/Country of Assy 1.5GHz/256/400/1.
General Information Figure 4 Intel® Pentium® 4 Processor with 512-KB L2 Cache on 0.13 Micron Process, Intel® Pentium® 4 Processor Extreme Edition Supporting Hyper-Threading Technology, and Boxed Pentium 4 Processor with 512-KB L2 Cache on 0.13 Micron Process Processor Markings INTEL m c `01 PENTIUM® 4 Frequency/Cache/Bus/Voltage 2.40 GHZ/512/800/1.
General Information Figure 7 Intel® Pentium® 4 Extreme Edition on 0.13 micron in the 775-Land LGA Package Marking S-Spec/ Country of Assy FPO INTEL m c `04 PENTIUM® 4 3.
Identification Information Identification Information The Pentium 4 processor may be identified by the following component markings: Family1 Model2 Brand ID3 1111 0000 00001000 1111 0001 00001000 or 00001001 1111 0010 00001001 1111 0011 — NOTES: 1.
Identification Information S-Spec Core Stepping L2 Cache Size (bytes) CPUID Speed Core/Bus Package and Revision Notes SL4X4 C1 256K 0F0Ah 1.60GHz/400MHz 31.0 mm OOI rev 1.0 1, 3 SL57V C1 256K 0F0Ah 1.70GHz/400MHz 31.0 mm OOI rev 1.0 1, 3 SL4X5 C1 256K 0F0Ah 1.80GHz/400MHz 31.0 mm OOI rev 1.0 1, 3 SL5SX D0 256K 0F12h 1.50GHz/400MHz 31.0 mm FC rev 1.0 3 SL5VL D0 256K 0F12h 1.60GHz/400MHz 31.0 mm FC rev 1.0 3 SL5SY D0 256K 0F12h 1.70GHz/400MHz 31.0 mm FC rev 1.
Identification Information S-Spec Core Stepping L2 Cache Size (bytes) CPUID Speed Core/Bus Package and Revision Notes SL5UJ D0 256K 0F12h 1.60GHz/400MHz 31.0 mm FC rev 1.0 1, 4 SL5UG D0 256K 0F12h 1.70GHz/400MHz 31.0 mm FC rev 1.0 1, 4 SL62Z D0 256K 0F12h 1.70GHz/400MHz 31.0 mm FC rev 1.0 1, 4, 7 SL5UK D0 256K 0F12h 1.80GHz/400MHz 31.0 mm FC rev 1.0 1, 4 SL5WG D0 256K 0F12h 1.90GHz/400MHz 31.0 mm FC rev 1.0 1, 4 SL668 B0 512K 0F24h 1.60GHz/400MHz 31.
Identification Information S-Spec Core Stepping L2 Cache Size (bytes) CPUID Speed Core/Bus Package and Revision Notes SL6S7 C1 512K 0F27h 2.00GHz/400MHz 31.0 mm FC rev 1.0 5, 16 SL6S8 C1 512K 0F27h 2.20GHz/400MHz 31.0 mm FC rev 1.0 5, 16 SL6RY C1 512K 0F27h 2.26GHz/533MHz 31.0 mm FC rev 1.0 5, 16 SL6SR C1 512K 0F27h 2.40GHz/400MHz 31.0 mm FC rev 1.0 1, 5, 16 SL6S9 C1 512K 0F27h 2.40GHz/400MHz 31.0 mm FC rev 1.0 5, 16 SL6RZ C1 512K 0F27h 2.40GHz/533MHz 31.
Identification Information S-Spec Core Stepping L2 Cache Size (bytes) CPUID Speed Core/Bus Package and Revision Notes SL6QN D1 512K 0F29h 2.2GHz/400MHz 31.0 mm FC rev 1.0 1, 5, 16 SL6QP D1 512K 0F29h 2.4GHz/400MHz 31.0 mm FC rev 1.0 1, 5, 16 SL6QQ D1 512K 0F29h 2.5GHz/400MHz 31.0 mm FC rev 1.0 1, 5, 16 SL6QR D1 512K 0F29h 2.6GHz/400MHz 31.0 mm FC rev 1.0 1, 5, 16 SL6Q7 D1 512K 0F29h 2.26GHz/533MHz 31.0 mm FC rev 1.0 1, 5, 16 SL6Q8 D1 512K 0F29h 2.
Identification Information S-Spec Core Stepping L2 Cache Size (bytes) CPUID Speed Core/Bus Package and Revision Notes SL6WS D1 512K 0F29h 2.60GHz/800MHz 31.0 mm FC rev 1.0 1, 5, 11, 16 SL6WT D1 512K 0F29h 2.80GHz/800MHz 31.0 mm FC rev 1.0 1, 5, 11, 16 SL6Z3 M0 512K 0F25h 2.40GHz/800MHz 31.0 mm FC rev 1.0 1, 5, 11, 16,18,20 SL6Z5 M0 512K 0F25h 2.80GHz/800MHz 31.0 mm FC rev 1.0 1, 5, 11, 16,18,20 SL7AA M0 512K 2M (L3) 0F25h 3.20GHz/800MHz 31.0 mm FC rev 1.
Identification Information 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. These parts include Hyper-Threading Technology. These parts are at VID=1.475 V. These parts are at VID=1.500 V. These parts are at VID=1.525 V. These parts are at VID=1.550 V. These parts have multiple VIDs. These parts will only operate at the specified core to bus frequency ratio and lower. These parts have some specifications that differ from those in the Intel® Pentium® 4 Processor with 512-KB L2 Cache on 0.
Errata Errata 1. I/O Restart in SMM May Fail after Simultaneous Machine Check Exception (MCE). Problem: If an I/O instruction (IN, INS, REP INS, OUT, OUTS, or REP OUTS) is being executed, and if the data for this instruction becomes corrupted, the processor will signal a Machine Check Exception (MCE). If the instruction is directed at a device that is powered down, the processor may also receive an assertion of SMI#.
Errata 3. Uncacheable (UC) Code in Same Line As Write Back (WB) Data May Lead to Data Corruption Problem: When both code (being accessed as UC or WC) and data (being accessed as WB) are aliased into the same cache line, the UC fetch will cause the processor to self-snoop and generate an implicit writeback. The data supplied by this implicit writeback may be corrupted due to the way the processor handles self-modifying code.
Errata Implication: When this erratum occurs, system and cache memory may be corrupted. Workaround: While there is no workaround to prevent the second line from being corrupted, avoiding tight data sharing and tight spin loops will reduce the possibility of this erratum occurring. Tight spin loops can be avoided by inserting the PAUSE instruction into the loop. Status: For the steppings affected, see the Summary Tables of Changes. 7.
Errata Workaround: Remove the software’s dependency on #AC having precedence over #PF. Alternately, correct the page fault in the page fault handler and then restart the faulting instruction. Status: For the steppings affected, see the Summary Tables of Changes. 10. IERR# May Not go Active When an Internal Error Occurs Problem: If the processor hangs because a store to the system bus does not complete, the processor may not assert the IERR# signal.
Errata 13. Processor May Hang Due to Speculative Page Walks to Non-Existent System Memory Problem: A load operation that misses the Data Translation Lookaside Buffer (DTLB) will result in a page-walk. If the page-walk loads the Page Directory Entry (PDE) from cacheable memory and that PDE load returns data that points to a valid Page Table Entry (PTE) in uncacheable memory the processor will access the address referenced by the PTE.
Errata Status: For the steppings affected, see the Summary Tables of Changes. 16. IA32_MC0_STATUS Register Overflow Bit Not Set Correctly Problem: The Overflow Error bit (bit 62) in the IA32_MC0_STATUS register indicates, when set, that a machine check error occurred while the results of a previous error were still in the error reporting bank (i.e. the valid bit was set when the new error occurred).
Errata internal boundary conditions exist that may prevent the data breakpoint from being captured. Implication: When this erratum occurs, a data breakpoint will not be captured. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. 20.
Errata 23. MCA Error Incorrectly Logged As Prefetches Problem: An MCA error is being incorrectly logged as PREFETCH type errors in the Request sub-field of the Compound error code in the IA32_MC0_STATUS register. A store, which hits a double bit data error in the L2 cache, is incorrectly logged as a prefetch data error. Implication: When this erratum occurs, the IA32_MC0_STATUS register will contain incorrect information. Workaround: None identified.
Errata The snoop makes the RFO appear to have missed cache. Although the RFO appears to have missed the cache, the ECC error code is not cleared and the L2 cache control logic to fails to communicate that the RFO has completed. The processor does not see that the RFO has completed and will hang. Implication: When this erratum occurs, the processor will hang. Intel has not been able to reproduce this erratum with commercial software. Workaround: None identified.
Errata Implication: When this erratum occurs, data corruption may occur. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. 30. Stale Data in Processor Translation Cache May Result in Hang Problem: Several instructions and task switches normally invalidate the processor translation cache.
Errata Problem: The processor may incorrectly go to the Machine Check handler in the following scenario: • Error reporting is enabled in the IA32_MC1_CTL register, • The processor issues a Read for Ownership (RFO) that hits an L2 cache line in the Shared state, and • This RFO access also receives a correctable error. • An external snoop hits the same cacheline immediately after the RFO. Implication: When this erratum occurs, the processor will incorrectly enter the machine check handler.
Errata Problem: Bit 1 of the IA32_THERM_STATUS register (Thermal Status Log) is a sticky bit designed to be set to '1' if the thermal control circuit (TCC) has been active since either the previous processor reset or software cleared this bit. If TCC is active and the Thermal Status Log bit is cleared by a processor reset or by software, it will remain clear (set to ‘0’) as long as the TCC remains active. Once TCC deactivates, the next activation of the TCC will set the Thermal Status Log bit.
Errata Problem: When the processor detects errors it should attempt to report and/or recover from the error. In the situations described below, the processor does not report and/or recover from the error(s) as intended. • When a transaction is deferred during the snoop phase and subsequently receives a Hard Failure response, the transaction should be removed from the bus queue so that the processor may proceed.
Errata • If an I/O instruction (IN, INS, REP INS, OUT, OUTS, or REP OUTS) is being executed, and if the data for this instruction becomes corrupted, the processor will signal a Machine Check Exception (MCE). If the instruction is directed at a device that is powered down, the processor may also receive an assertion of SMI#. Since MCEs have higher priority, the processor will call the MCE handler, and the SMI# assertion will remain pending.
Errata issued to the bus before the processor vectors to the machine check handler. Once the chipset receives its last Stop Grant special cycle it is allowed to ignore any bus activity from the processors. As a result, processor accesses to the machine check handler may not be acknowledged, resulting in a processor hang. Implication: The processor is unable to correctly report and/or recover from certain errors. Workaround: None identified.
Errata 41. Possible Machine Check Due to Line-Split Loads with Page-Tables in Uncacheable (UC) Space Problem: The processor issues a speculative load which splits a 64-byte cache line. At the same time the page miss handling logic completes a page-walk for a different load. The resulting translation fills the DTLB and evicts the TLB entry to be used by the line-split load. Since the page tables are located in UC memory, this generates a load on the system bus for the Page Directory Entry (PDE).
Errata instruction pointer (LIP) is pointing to a floating-point instruction whose instruction bytes are in UC space and which takes an exception 16 (floating point error exception). The processor stalls trying to fetch the bytes of the faulting floating-point instruction and those following it. This processor hang is caused by interactions between thermal control circuit and floating-point event handler. Implication: The processor will go into a sleep state from which it fails to return.
Errata 45. Speculative Page Fault May Cause Livelock Problem: If the processor detects a page fault which is corrected before the operating system page fault handler can be called e.g., DMA activity modifies the page tables and the corrected page tables are left in a non-accessed or not dirty state, the processor may livelock. Intel has not been able to reproduce this erratum with commercial software.
Errata 48. Bus Invalidate Line Requests That Return Unexpected Data May Result in L1 Cache Corruption Problem: When a Bus Invalidate Line (BIL) request receives unexpected data from a deferred reply, and a store operation write combines to the same address, there is a small window where the L0 is corrupt, and loads can retire with this corrupted data.
Errata Workaround: Do not place page directories and/or page tables in WC memory. Status: For the steppings affected, see the Summary Tables of Changes. 51. Buffer on Resistance May Exceed Specification Problem: The datasheet specifies the resistance range for RON (Buffer On Resistance) for the AGTL+ and Asynchronous GTL+ buffers as 5 to 11 Ohms. Due to this erratum, RON may be as high as 13.11 Ohms.
Errata 54. Processor May Hang When Resuming from Deep Sleep State Problem: When resuming from the Deep Sleep state the address strobe signals (ADSTB [1:0]#) may become out of phase with respect to the system bus clock (BCLK). Implication: When this erratum occurs, the processor will hang. Workaround: The system BIOS should prevent the processor from going to the Deep Sleep state. Status: For the steppings affected, see the Summary Tables of Changes. 55.
Errata 57. IA32_MC0_ADDR and IA32_MC0_MISC Registers Will Contain Invalid or Stale Data following a Data, Address, or Response Parity Error Problem: If the processor experiences a data, address, or response parity error, the ADDRV and MISCV bits of the IA32_MC0_STATUS register are set, but the IA32_MC0_ADDR and IA32_MC0_MISC registers are not loaded with data regarding the error. Implication: When this erratum occurs, the IA32_MC0_ADDR and IA32_MC0_MISC registers will contain invalid or stale data.
Errata Workaround: If use of the on-demand mode of the processor's TCC is desired in conjunction with STPCLK# modulation, then assure that STPCLK# is not asserted at a 12.5% duty cycle. Status: For the steppings affected, see the Summary Tables of Changes. 61.
Errata Workaround: It is possible for BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. 63. Re-Mapping the APIC Base Address to a Value Less Than or Equal to 0xDC001000 May Cause IO and Special Cycle Failure Problem: Remapping the APIC base address from its default can cause conflicts with either I/O or special cycle bus transactions.
Errata Implication: Processor may fetch incorrect data, resulting in BIOS failure. Workaround: De-asserting and re-asserting A20M# prior to the data access will workaround this erratum. Status: For the steppings affected, see the Summary Tables of Changes. 67.
Errata Implication: When this erratum occurs in an HT Technology enabled system, it may cause a system hang. Workaround: BIOS should initialize the second thread of the processor supporting HyperThreading Technology prior to STPCLK# assertion. Additionally, it is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. 70.
Errata 73. Disabling a Local APIC Disables Both Logical Processor APICs on a Hyper-Threading Technology1 Enabled Processor Problem: Disabling a local APIC on one logical processor of a Hyper-Threading Technology enabled processor by clearing bit 11 of the IA32_APIC_BASE MSR will effectively disable the local APIC on the other logical processor. Implication: Disabling a local APIC on one logical processor prevents the other logical processor from sending or receiving interrupts.
Errata 76. Changes to CR3 Register Do Not Fence Pending Instruction Page Walks Problem: When software writes to the CR3 register, it is expected that all previous/outstanding code, data accesses and page walks are completed using the previous value in CR3 register. Due to this erratum, it is possible that a pending instruction page walk is still in progress, resulting in an access (to the PDE portion of the page table) that may be directed to an incorrect memory address.
Errata 79. Simultaneous Page Faults at Similar Page Offsets on Both Logical Processors of a Hyper-Threading Technology Enabled Processor May Cause Application Failure Problem: An incorrect value of CR2 may be presented to one of the logical processors of an HT Technology enabled processor if a page access fault is encountered on one logical processor in the same clock cycle that the other logical processor also encounters a page fault.
Errata necessary to avoid a multi-agent livelock scenario in which the processor cannot gain ownership of a line and modify it before that data is snooped out by another agent. In the case of this erratum, split load lock instructions incorrectly trigger the useonce protocol. A load lock operation accesses data that splits across a page boundary with both pages of WB memory type. The use-once protocol activates and the memory type for the split halves get forced to UC.
Errata 84. Simultaneous Cache Line Eviction from L2 and L3 Caches May Result in the Write Back of Stale Data Problem: If a cache line is evicted simultaneously from both the L2 and L3 caches, and the internal bus queues are full, an older L3 eviction may be allowed to remain in an internal queue entry. If, in a narrow timing window an external snoop is generated, the data from the older eviction may be used to respond to the external snoop.
Errata 87. Modified Cache Line Eviction from L2 Cache May Result in Writeback of Stale Data Problem: It is possible for a modified cache line to be evicted from the L2 cache just prior to another update to the same line by software. In rare circumstances, the processor may accrue two bus queue entries that have the same address but have different data. If an external snoop is generated in a narrow timing window, the data from the older eviction may be used to respond to the external snoop.
Errata 90. Memory Aliasing of Pages As Uncacheable Memory Type and Write Back (WB) May Hang the System Problem: When a page is being accessed as either Uncacheable (UC) or Write Combining (WC) and WB, under certain bus and memory timing conditions, the system may loop in a continual sequence of UC fetch, implicit writeback, and Request For Ownership (RFO) retries. Implication: This erratum has not been observed in any commercially available operating system or application.
Errata 93. Machine Check Exceptions May not Update Last-Exception Record MSRs (LERs) Problem: The Last-Exception Record MSRs (LERs) may not get updated when Machine Check Exceptions occur. Implication: When this erratum occurs, the LER may not contain information relating to the machine check exception. They will contain information relating to the exception prior to the machine check exception. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. 94.
Errata 96. With TF (Trap Flag) Asserted, FP Instruction That Triggers an Unmasked FP Exception May Take Single Step Trap before Retirement of Instruction Problem: If an FP instruction generates an unmasked exception with the EFLAGS.TF=1, it is possible for external events to occur, including a transition to a lower power state. When resuming from the lower power state, it may be possible to take the single step trap before the execution of the original FP instruction completes.
Errata 99. Memory Ordering Failure May Occur with Snoop Filtering Third Party Agents after Issuing and Completing a BWIL (Bus Write Invalidate Line) or BLW (Bus Locked Write) Transaction Problem: Under limited circumstances, the processors may, after issuing and completing a BWIL or BLW transaction, retain data from the addressed cache line in shared state even though the specification requires complete invalidation.
Errata Implication: An interrupt may immediately be generated with the new vector when a LVT entry is written, even if the new LVT entry has the mask bit set. If there is no Interrupt Service Routine (ISR) set up for that vector the system will GP fault. If the ISR does not do an End of Interrupt (EOI) the bit for the vector will be left set in the in-service register and mask all interrupts at the same or lower priority.
Errata Status: For the steppings affected, see the Summary Tables of Changes. 104.
Specification Changes Specification Changes The Specification Changes listed in this section apply to the following documents: • Intel® Pentium® 4 Processor in the 423-pin Package, Intel® Pentium® 4 Processor in the 478-pin Package Datasheet • Intel® Pentium® 4 Processor in the 478-pin Package Datasheet • Intel® Pentium® 4 Processor with 512-KB L2 Cache on 0.
Specification Clarifications Specification Clarifications The Specification Clarifications listed in this section apply to the following documents: • Intel® Pentium® 4 Processor in the 423-pin Package, Intel® Pentium® 4 Processor in the 478-pin Package Datasheet • Intel® Pentium® 4 Processor in the 478-pin Package Datasheet • Intel® Pentium® 4 Processor with 512-KB L2 Cache on 0.
Specification Clarifications processor is halted by the HLT instruction or the external STPCLK# pin. Note that the assertion of the external DPSLP# pin may cause the time-stamp counter to stop.
Specification Clarifications 15.10.9 COUNTING CLOCKS The count of cycles, also known as clockticks, forms a basis for measuring how long a program takes to execute. Clockticks are also used as part of efficiency ratios like cycles per instruction (CPI). Processor clocks may stop ticking under circumstances like the following: • The processor is halted when there is nothing for the CPU to do. For example, the processor may halt to save power while the computer is servicing an I/O request.
Specification Clarifications § Specification Update 73
Documentation Changes Documentation Changes The Documentation Changes listed in this section apply to the following documents: • Intel® Pentium® 4 Processor in the 423-pin Package, Intel® Pentium® 4 Processor in the 478-pin Package Datasheet • Intel® Pentium® 4 Processor in the 478-pin Package Datasheet • Intel® Pentium® 4 Processor with 512-KB L2 Cache on 0.
