® Intel Pentium 4 Processor VR-Down Design Guidelines November 2002 Order Number 249891-004
® ® Intel Pentium 4 Processor VR-Down Design Guidelines THIS DOCUMENT AND RELATED MATERIALS AND INFORMATION ARE PROVIDED "AS IS" WITH NO WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION, OR SAMPLE.
® ® Intel Pentium 4 Processor VR-Down Design Guidelines Contents 1 2 3 Output Requirements......................................................................................................................5 1.1 Voltage and Current REQUIRED .......................................................................................5 1.2 Voltage Tolerance REQUIRED ...........................................................................................5 1.3 Load Line Definitions REQUIRED ..........
® ® Intel Pentium 4 Processor VR-Down Design Guidelines Applications and Terminology This document defines DC-to-DC converters to meet the power requirements of computer systems using Intel microprocessors. Requirements will vary according to the needs of different computer systems and processors that a specific voltage regulator (VR) is expected to support. The “VR” designation in this document refers to an embedded voltage regulator on a system board. Please refer to the VRM 9.
® ® Intel Pentium 4 Processor VR-Down Design Guidelines 1 Output Requirements 1.1 Voltage and Current REQUIRED ® ® The voltage regulator for the Intel Pentium 4 processor in the 478-pin package and Pentium 4 processor with 512-KB L2 cache on 0.13 micron process is a DC-DC converter that supplies the required voltage and current to a single processor. A five-bit VID code provided by the processor to the voltage regulator (VR) determines a reference output voltage, as described in Section 3.1.
® ® Intel Pentium 4 Processor VR-Down Design Guidelines 1.3 Load Line Definitions REQUIRED The following load lines contain DC and transient-droop data, as well as maximum and minimum voltage levels. The voltages are measured at the processor socket Vcc and Vss pins. The following figure and table show load-line voltage offsets and current levels based on the VID (maximum) voltage settings specified in.
® ® Intel Pentium 4 Processor VR-Down Design Guidelines Table 2, Load Line at Processor Socket Icc (A) 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 Voltage Deviation from VID Setting (V) Minimum Typical Maximum -0.050 -0.025 0.000 -0.057 -0.033 -0.008 -0.065 -0.040 -0.015 -0.072 -0.047 -0.023 -0.080 -0.055 -0.030 -0.087 -0.063 -0.038 -0.095 -0.070 -0.045 -0.103 -0.077 -0.053 -0.110 -0.085 -0.060 -0.118 -0.092 -0.067 -0.125 -0.100 -0.075 -0.133 -0.108 -0.083 -0.140 -0.115 -0.090 -0.148 -0.123 -0.097 -0.
® ® Intel Pentium 4 Processor VR-Down Design Guidelines 1.6 Turn-on Response Time PROPOSED The processor socket voltage should reach its specified range within 50 ms of the input power reaching its minimum voltage. Please refer to the next paragraph and related figures for complete power up timing requirements. 1.7 Processor Power Sequencing REQUIRED The Pentium 4 processor in the 478-pin package and Pentium 4 processor with 512-KB L2 cache on 0.13 micron process require a 1.
® ® Intel Pentium 4 Processor VR-Down Design Guidelines Intel® ICH2 Component PWRGOOD VRMPWRGD VID[4:0] VID_Good* Processor Voltage Regulator Processor Vcc *VID_Good connected to voltage regulator controller output enable System Power Supply VID_Good Generation Logic 1ms delay VCCVID Voltage Regulator PS_PWR_OK Figure 2: Power Sequencing Block Diagram VCCVID Ta Tb VID_GOOD VID[4:0] BCLK Vcc PWRGOOD Tc Td RESET# Ta= 1ms minimum (VCCVID > 1V to VID_GOOD high) Tb= 50ms maximum (VID_GOOD t
® ® Intel Pentium 4 Processor VR-Down Design Guidelines Vcc PWRGOOD VCCVID VID_GOOD VID[4:0] Note: VID_GOOD is not a processor signal. This signal is routed to the output enable pin of the voltage regluator control silicon. 1. This timing diagram is not intended to show specific times. Instead a general ordering of events with respect to time should be observed. 2. When VCCVID is less than 1V, VID_GOOD must be low. 3. Vcc must be disabled before VID[4:0] becomes invalid.
® ® Intel Pentium 4 Processor VR-Down Design Guidelines 20 50% 40% 1 100% 100% 250 Units • % of Icc-max • number of clock cycles 5% 1 2 100% Imax 5-10 50% 40% 5% 400 1 2.2 2.7 µs 2.1 2.6 µs 5% Imax Figure 5: Processor Current during Thermal Monitor Operation Notes: ⋅ Duration of on-off periods depends on processor speed: faster processors have shorter durations. ⋅ Other operating system-controlled events could have on-times as short as 700 internal clock cycles.
® ® Intel Pentium 4 Processor VR-Down Design Guidelines 1.10 Thermal Monitoring PROPOSED This section describes how to protect the voltage regulator design from heat damage while supporting thermal design current (TDC) specifications. It is included for reference and is applicable to Intel® Pentium® 4 processors supporting Hyper-Threading Technology1 operating at 3.06 GHz or higher. Intel does not recommend integrating this feature into Vcc PWM controller designs.
® ® Intel Pentium 4 Processor VR-Down Design Guidelines Assertion of PROCHOT# is governed by the comparator (LM393) using the sensor voltage (at the negative comparator terminal) and a trigger reference voltage (at the positive comparator terminal). As the thermistor temperature increases due to system loading, the resistance will decrease.
® ® Intel Pentium 4 Processor VR-Down Design Guidelines 2 Input Voltage and Current 2.1 Input Voltages REQUIRED The main power source for the VR is 12V +5%, -8%. This voltage is supplied by a conventional computer power supply through a cable to the system board. The system board will supply local bulk bypassing on the 12V rail. Adequate connector current handling capacity must be part of system power budgeting. 2.
® ® Intel Pentium 4 Processor VR-Down Design Guidelines Table 4, Voltage Identification (VID) Processor Pins (0 = low, 1 = high) VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Vcc (VDC) Off 1.1 1.125 1.15 1.175 1.2 1.225 1.250 1.275 1.3 1.325 1.35 1.375 1.4 1.425 1.
® ® Intel Pentium 4 Processor VR-Down Design Guidelines 6 Fault Protection 6.1 Over Voltage Protection EXPECTED The VR should provide over-voltage protection (OVP) by including a circuit, separate from the voltage sense path, capable of shutting off the output drive when the output voltage rises beyond Vtrip. If practical, the protection circuit should also enable a low-resistance path to ground such that if the output transistor shorts to input power the output voltage will not rise above Vtrip.
