R Mobile Intel® Pentium® 4 Processor-M and Intel® 845MP/845MZ Chipset Platform Design Guide April 2002 Order Number: 250688-002
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Contents 1. Introduction ................................................................................................................................ 14 1.1. 1.2. 1.3. 1.4. 2. General Design Considerations ................................................................................................. 24 2.1. 3. Nominal Board Stackup................................................................................
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 4.3. 4.4. 4.5. 4.6. 4.7. 4.8. 4.9. 5. Introduction ....................................................................................................................54 DDR System Memory Topology and Layout Design Guidelines....................................55 5.2.1. Data Signals – SDQ[63:0], SDQS[8:0], SCB[7:0] ........................................55 5.2.1.1. Data to Strobe Length Matching Requirements ............
® 6.3.3. 6.3.4. 6.3.5. 6.3.6. 6.3.7. 6.3.8. 6.3.9. 7. 6.3.2.3. Trace Length Mismatch Requirements .......................................... 90 AGP Clock Skew......................................................................................... 91 AGP Signal Noise Decoupling Guidelines................................................... 91 AGP Routing Ground Reference................................................................. 92 Pull-ups ............................................................
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 9.8. 9.9. 9.10. 6 R 9.7.1. FWH Decoupling........................................................................................115 9.7.2. In Circuit FWH Programming.....................................................................115 FWH Signaling Voltage Compatibility ..........................................................................116 9.8.1. FWH Vpp Design Guidelines ......................................
® 10. ® Platform Clock Routing Guidelines .......................................................................................... 142 10.1. 10.2. 10.3. 11. ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Clock Generation......................................................................................................... 142 Clock Control............................................................................................................... 145 10.2.1.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 11.6. 11.7. 11.8. 12. 8 11.5.13. 3.3-V FWH Decoupling ..............................................................................169 11.5.14. 3.3-V General LAN Decoupling..................................................................170 3.3-V Clock Driver Decoupling.....................................................................................170 DDR Power Delivery Design Guidelines ...........................
® R ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Figures Figure 1. Typical System Block Diagram ................................................................................. 20 Figure 2. Cross-Sectional View of 2:1 Ratio ............................................................................ 27 Figure 3. GTLREF Routing ...................................................................................................... 28 Figure 4. Processor Topology .........
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Figure 51. Example Speaker Circuit.......................................................................................107 Figure 52. Minimum IOAPIC Disable Topology......................................................................111 Figure 53. Example PIRQ Routing .........................................................................................111 Figure 54. SMBUS 2.0/SMLink Interface.........................
® R ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Tables Table 1. Conventions and Terminology ................................................................................... 16 Table 2. Mobile Pentium 4 Processor-M in the 478-Pin Package Feature Set Overview........ 19 Table 3. Platform Bandwidth Summary.................................................................................... 23 Table 4. System Bus Routing Summary for the Processor.........................
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Table 53. CLK33 Routing Guidelines .....................................................................................154 Table 54. CLK14 Routing Guidelines .....................................................................................155 Table 55. PCICLK Routing Guidelines ...................................................................................156 Table 56. PCICLK Routing Guidelines .....................
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Revision History Rev.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 1. R Introduction This design guide provides Intel’s design recommendations for systems based on the Mobile Intel® Pentium® 4 Processor-M and the Intel® 845MP/845MZ chipset. Design issues such as thermal considerations should be addressed using specific design guides or application notes for the processor or 845MP/845MZ chipset.
® 1.1. ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Related Documentation Reference the following documents or models for more information. All Intel issued documentation revision numbers are subject to change, and the latest revision should be used. The specific revision numbers referenced should be used for all documents not released by Intel. Contact the field representative for information on how to obtain Intel issued documentation.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Document Document Number/Source Intel® 82562ET/EM PCB Design Platform LAN Connect (AP-412) 1.2. R Contact your Field Representative Conventions and Terminology This section defines conventions and terminology that are used throughout this document. Table 1.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Convention/ Terminology Flight Time Definition Flight time is a term in the timing equation that includes the signal propagation delay, any effects the system has on the TCO of the driver, and any adjustments to the signal at the receiver needed to guarantee the setup time of the receiver.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Convention/ Terminology 1.3. R Definition SSO Simultaneous Switching Output (SSO) effects refers to the difference in electrical timing parameters and degradation in signal quality caused by multiple signal outputs simultaneously switching voltage levels (e.g., high-to-low) in the opposite direction from a single signal (e.g., lowto-high) or in the same direction (e.g., high-to-low).
® R ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Table 2. Mobile Pentium 4 Processor-M in the 478-Pin Package Feature Set Overview 1.4. Feature Mobile Intel Pentium 4 Processor-M in the 478 Pin Package L1 Cache 12 KB on-die L2 Cache 512 KB on-die L3 Cache None Data Transfer Rate 3.2 GB/sec Manageability Features Thermal Monitor Package Pin Configuration 478 pin, 0.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Figure 1. Typical System Block Diagram Mobile Intel® Pentium® 4 Processor-M System Bus 400MT/S (3.2 GB/sec Data Rate) PC1600/PC2100 845MP/845MZ MCH-M 593 FC-BGA DDR200/266 AGP 2.0 DDR200/266 4X AGP Graphic Controller 8-Bit HUB Interface 6 USB 1.1 Port FWH 2 ATA 66/100 IDE Channels ICH3-M 421 mBGA LAN/HPNA PCI Bus AC'97 Modem CODEC (Optional) CardBUS MOON2 LAN LPC Bus SMC 1.4.1.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R • AGTL+ host bus with integrated termination supporting 32-bit host addressing • 1.5-V AGP interface with 4x SBA/data transfer and 2x/4x fast write capability • 8-bit, 66-MHz,, 4x hub interface to the Intel ICH3-M 1.4.1.1.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform • AGP BUSY protocol. • AGP Clamping and sense amp control • Supports 32-deep AGP address queue. 1.4.1.3. Packaging/Power • 593-pin, FC-BGA package • 1.5 V (±5%) core and mixed 3.3 V, 1.5 V, 1.8 V, and AGTL+ I/O 1.4.1.4. I/O Controller Hub (ICH3-M) ICH3-M provides the I/O subsystem with access to the rest of the system: • Upstream Accelerated Hub Architecture interface at 266 MB/s for access to the MCH-M • PCI 2.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Table 3.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 2. R General Design Considerations This section documents motherboard layout and routing guidelines for Intel 845MP/845MZ platforms. This section does not discuss the functional aspects of any bus, or the layout guidelines for an add-in device. If the guidelines listed in this document are not followed, it is very important that thorough signal integrity and timing simulations are completed for each design.
® R ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 3. Processor System Bus Design Guidelines 3.1. Introduction Intel’s Mobile Pentium 4 Processor-M is the first mobile Intel processor with the Intel NetBurst microarchitecture. The Mobile Pentium 4 Processor-M utilizes Micro Flip-Chip Pin Grid Array (MicroFCPGA) package technology, and plugs into a 478-pin, surface-mount, Zero Insertion Force (ZIF) socket, which is referred to as the mPGA478M socket.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 3.2. Processor System Bus (PSB) Routing Guidelines Table 4 summarizes the layout recommendations for mobile Pentium 4 Processor-M in the 478-pin package configurations and expands on specific design issues and their recommendations. Table 4.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Parameter Processor Routing Guidelines within) either the source-synchronous data or address groups. As long as the strobe and associated line length routing guidelines are met for each group, there is no need to length-match between the groups. For example, one data group may be routed to the minimum allowable length while another data group could be routed to the maximum allowable length.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 3.2.2. R GTLREF Layout and Routing Recommendations There are four AGTL+ GTLREF pins on the processor that are used to set the reference voltage level for the AGTL+ signals (GTLREF). Because all of these pins are connected inside the processor package, the GTLREF voltage only needs to be supplied to one of the four pins. The other three pins can be left unconnected. Figure 3. GTLREF Routing VCC_CPU 49.9 ohms 1% L1 = 1.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R are Intel’s best guidelines based on extensive simulation and experimentation that make assumptions, which may be different than an OEM's system design. The most accurate way to understand the signal integrity and timing of the system bus in your platform is by performing a comprehensive simulation analysis.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Source synchronous groups and associated strobes should be routed on the same layer for the entire length of the bus. This results in a significant reduction of the flight time skew since the dielectric thickness, line width, and velocity of the signals will be uniform across a single layer of the stackup. There is no guarantee of a relationship of dielectric thickness, line width, and velocity between layers. Figure 4.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Table 6. Processor System Bus Address Signal Routing Guidelines Routing Length (pin-to-pin) L1 Signal Names Topology CPU Intel 845MP/845MZ A[35:3]# HA[35:3]# REQ[4:0]# ADSTB[1:0]# NOTE: Nominal Impedance (ohms) Width & Spacing (mils) Max (inches) Min (inches) Stripline 10.0 1.5 55 ± 15% 4&8 HREQ[4:0]# Stripline 10.0 1.5 55 ± 15% 4&8 HADSTB[1:0]# Stripline 10.0 1.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 3.4.3. R Common Clock (CC) AGTL+ Signals Table 7. Processor System Bus Control Signal Routing Guidelines Routing Trace Length (Pin-to-Pin) Signal Names Topology CPU Intel 845MP/845MZ RESET# CPURST# BR0# Width & spacing (mils) Max (inches) Min (inches) Stripline 10.0 1.5 55 ± 15% 4&8 BR0# Stripline 10.0 1.5 55 ± 15% 4&8 BNR# BNR# Stripline 10.0 1.
® R ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Figure 6. CC Topology With ODT Processor Vtt Pin Vtt Chipset Vtt Chipset Pin Pad Pad L1 Figure 7.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 3.4.4. R PWRGOOD and Asynchronous AGTL+ Signals Table 8. Asynchronous AGTL+ Nets 34 Signal Names Description Topology # CPU IO Type Output Output Buffer Type Output Power Well Input Input Power Well FERR# Floating point error 1 O CPU OD AGTL+ N/A ICH3-M Main I/O (3.
® R ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform All signals must meet the AC and DC specifications as documented in the Mobile Intel® Pentium® Processor-M Datasheet. In addition, several design guidelines should be implemented when designing your platform with these signals.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 3.4.4.1.1. R Topology #1: Asynchronous AGTL+ Signals Driven by the Processor; FERR#, IERR#, PROCHOT# and THRMTRIP# These signals should adhere to the following routing and layout recommendations. Figure 9 illustrates the recommended topology.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Figure 10. Routing Illustration for LINT1/INTR, LINT0/NMI, DPSLP#, SLP#, STPCLK#, IGNNE#, SMI# and A20M#, CPUPERF#, and PWRGOOD- Topology 2, 2A Vtt_CPU Rtt_CPU CPU ICH3-M L2 L2 L3 L1 Table 10. Layout Recommendations for Miscellaneous Signals – Topology 2, 2A L1 L2 L3 Rtt 1.5" - 14.0" 1.1" max 3.0" max Rtt_#2 = 200 ohms ± 5% Rtt_#2A = 300 ohms ± 5% 3.4.4.1.3.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 3.4.4.2. R Voltage Translator Circuit This recommended Voltage translator circuit should be applied to topologies #1 and #2B shown in Section 3.4.4.1.1 and 3.4.4.1.3. Figure 12. Voltage Translator Circuit of Topology#1 and #2B Vcc of Receiver 470 ohm +/- 5% To Receiver 3904 From Driver 470 ohm +/- 5% 3.5. 3904 ITP Debug Port Note: 3.5.1.1.
® R ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform normally occupied by the Mobile Pentium 4 Processor-M heat sink. If this is the case, the logic analyzer vendor will provide a cooling solution as part of the LAI. 3.5.1.1.2.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 4. Processor Power Requirements 4.1. General Description The IMVP-III Design Guide defines the electrical requirements for the DC-to-DC Voltage Regulator for the Mobile Pentium 4 Processor-M that features Intel SpeedStep® technology in a Micro-FCPGA package. Please contact your Field Representative for more information.
® R 4.2. ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Power Delivery Architectural Block Diagram Figure 13. Voltage Regulator Block Diagram . VDC V_5 V_3 STP_CPU# DPRSLPVR VREF IMVP-III Processor Core Voltage Regulator VDPRSLP VR_ON VCC VID[0..4] VCC VID CPU_PWRGOOD VTT VCC VCCA VSSA Mobile Intel® Pentium® 4 Processor-M LC Filter PWRGOOD VVID V_3 . ICH3-M ChipSet VR_ON VID (1.2V) Voltage Regulator PWRGOOD_VID . 4.3.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R general desired filter topology is shown in Figure 14. Not shown in the core is parasitic routing and excluded from the external circuitry are parasitics associated with each component. Figure 14. Typical VCCIOPLL, VCCA, and VSSA Power Distribution VCCA VCC_VID 4.7 µH CA Motherboard 33 µF c2 1 µF PLLs pkg CIO 33 µF 4.7 µH VSSA Processor Core VCCIOPLL The function of the filter is two-fold.
® R ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Figure 15. Filter Recommendation 0.2 dB 0 dB -0.5 dB forbidden zone -28 dB forbidden zone -34 dB DC 1 Hz fpeak 1 MHz 66 MHz fcore high frequency band passband NOTES: 1. Diagram not to scale. 2. No specification for frequencies beyond fcore (core frequency). 3. fpeak, if existent, should be less than 0.05 MHz.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Figure 16. Example Component Placement for PLL Filter 4.4. Voltage and Current A mobile processor core regulator supplies the required voltage and current to a single processor. Refer to the IMVP-III Mobile Processor Core Voltage Regulator Specification Design Guide (contact your Field Representative) for the load line specification and implementation features. 4.4.1.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Figure 17. Power On Sequencing Diagram VID_ON VVID VID[4..0] PWRGOOD_VID VCC PWRGOOD RESET# Figure 18. Power Off Sequencing Diagram VID_ON VVID PWRGOOD_VID VCC PWRGOOD RESET# 4.5. Voltage Regulator Design Recommendations For more information please refer to the IMVP-III Mobile Processor Core Voltage Regulator Specification Design Guide for the actual specifications (contact your Field Representative).
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform response of the processor, it is necessary to properly place bulk and high frequency capacitors close to the processor power and ground pins. 4.6.1. Transient Response The inductance of the motherboard power planes slows the voltage regulator’s ability to respond quickly to a current transient. Decoupling a power plane can be broken into several independent parts.
® R 4.6.3. ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform High Frequency Decoupling System motherboards should include high frequency decoupling capacitors as close to the socket power and ground pins as possible. A total of thirty-eight 10.0-µF, X5R/X7R, 1206 package, ceramic capacitors are recommended to provided high frequency decoupling for the processor. Ten of these 1206 capacitors should be placed in the socket cavity area.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R heat being generated by the device and its ability to shed heat either through radiation into the surrounding air or by conduction into the circuit board. Increased power will effectively raise the temperature of the processor power delivery circuit’s. Switching transistor die temperatures can exceed the recommended operating value if the heat cannot be removed from the package effectively.
® R 4.8. ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Voltage Regulator Topology For more information please refer to the IMVP-III Mobile Processor Core Voltage Regulator Specification Design Guide for the actual specifications (contact your Field Representative). 4.9.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Table 12. Intel Mobile Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Package Lengths Processor lengths Signal Processor ball MCH-M Lengths Length (inches) Signal MCH-M ball Length (inches) Address Group 0 ADSTB#[0] L5 0.219 HADSTB0# R5 0.530 A#[03] K2 0.392 HA03# T4 0.518 A#[04] K4 0.281 HA04# T5 0.434 A#[05] L6 0.170 HA05# T3 0.728 A#[06] K1 0.435 HA06# U3 0.577 A#[07] L3 0.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Processor lengths MCH-M Lengths Signal Processor ball Length (inches) Signal MCH-M ball Length (inches) A#[27] V2 0.423 HA27# H4 0.634 A#[28] R6 0.177 HA28# N5 0.472 A#[29] W1 0.491 HA29# G2 0.792 A#[30] T5 0.232 HA30# M6 0.449 A#[31] U4 0.293 HA31# L7 0.365 Data Group 0 DSTBN#[0] E22 0.465 HDSTBN0# AD4 0.759 DSTBP#[0] F21 0.362 HDSTBP0# AD3 0.801 D#[00] B21 0.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Processor lengths R MCH-M Lengths Signal Processor ball Length (inches) Signal MCH-M ball Length (inches) D#[22] F26 0.521 HD22# AG3 0.898 D#[23] D26 0.605 HD23# AE5 0.709 D#[24] L21 0.187 HD24# AH7 0.863 D#[25] G26 0.535 HD25# AH3 0.904 D#[26] H24 0.412 HD26# AF4 0.794 D#[27] M21 0.171 HD27# AG8 0.789 D#[28] L22 0.254 HD28# AG7 0.785 D#[29] J24 0.410 HD29# AG6 0.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Processor lengths MCH-M Lengths Signal Processor ball Length (inches) Signal MCH-M ball Length (inches) D#[48] U26 0.424 HD48# AG13 0.668 D#[49] U24 0.329 HD49# AH13 0.712 D#[50] U23 0.269 HD50# AC14 0.412 D#[51] V25 0.386 HD51# AF14 0.548 D#[52] U21 0.174 HD52# AG14 0.621 D#[53] V22 0.246 HD53# AE14 0.520 D#[54] V24 0.343 HD54# AG15 0.612 D#[55] W26 0.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 5. Double Data Rate Synchronous DRAM (DDR-SDRAM) System Memory Design Guidelines 5.1. Introduction R The Intel 845MP/845MZ chipset Double Data Rate (DDR) SDRAM system memory interface consists of 120 CMOS signals. These CMOS signals have been divided into several signal groups: Data, Command, Control, Feedback, and Clock signals. Table 13 summarizes the different signal groupings.
® R 5.2. ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform DDR System Memory Topology and Layout Design Guidelines The Intel 845MP/845MZ chipset Double Data Rate (DDR) SDRAM system memory interface implements the low swing, high-speed, terminated SSTL_2 topology.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Figure 20. Data Signal Routing Topology MCHPkg MCH Pad Rs L1 Vtt Rt w L2 L4 L3 w SO-DIMM1 PAD SO-DIMM0 PAD Table 14.
® 5.2.1.1. ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Data to Strobe Length Matching Requirements The data signals SDQ[63:0] and the check bit signals [7:0] are grouped by byte lane and associated with a data strobe, SDQS[7:0]. The data signals and check bit signals must be length matched to their associated strobe within ± 25mils.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Figure 21.
® R 5.2.1.2. ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Strobe to Clock Length Matching Requirements The data strobe signals must be 1.0 inch to 2.0 inches shorter than their associated differential clock pairs. Length matching equation for SO-DIMM0: X1=SCK/SCK#[2:0] Y1=SDQS[8:0] = MCH-M package + L1 + L2 of Figure 21 where, ( X1 – 2.0” ) ≤ Y1 ≤ ( X1 – 1.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Figure 22.
® 5.2.1.3. ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Data Routing Example Figure 23 is an example of a board routing for the data signal group. Data routing is shown in red. The majority of the Data signal route is on an internal layer, both external layers can used for parallel termination R-pack placement. Figure 23. Data Signal Group Routing Example MCH Data signals 5.2.2.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Table 16. Control Signal SO-DIMM Mapping Signal Relative To SO-DIMM Pin SCS#[0] SO-DIMM0 121 SCS#[1] SO-DIMM0 122 SCS#[2] SO-DIMM1 121 SCS#[3] SO-DIMM1 122 SCKE[0] SO-DIMM0 96 SCKE[1] SO-DIMM0 95 SCKE[2] SO-DIMM1 96 SCKE[3] SO-DIMM1 95 Refer to Figure 24 and Figure 27 for clarification of the description below.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Table 17. Control Signal Group Routing Guidelines1 Parameter Routing Guidelines Signal Group Control – SCS#[3:0], SCKE[3:0] Topology Point to Point Parallel Termination Figure Figure 24, Figure 27 2 Reference Plane Ground Referenced Characteristic Trace Impedance (Zo) 55 Ω ± 15% Trace Width Inner Layer= 4 mils Outer Layer= 5 mils Trace to space ratio 1:2 (e.g.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 5.2.2.1. Control Group Signal Length Matching Requirements The control signals must be 1.0 inch to 3.0 inches shorter than their associated differential clocks pair. Note that these requirements may change in a later revision of the design guide based on a post silicon simulation analysis. Length matching equation for SO-DIMM0: X1=SCK/SCK#[2:0] Y1=SCS#[1:0] and SCKE[1:0] = L1 of Figure 26 where, ( X1 – 3.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Figure 26. Control Signal to SCK/SCK# Trace Length Matching Requirements SO-DIMM0 = Motherboard Trace Lengths MCH-M SCS#[1:0], SCKE[1:0] (X - 3.0") < = (CNTRL Length) = < ( X - 1.0" ) SCK[2:0 ] SCK#[2:0] SCK/SCK#[2:0] Length = X Note: Lengths are measured from MCH-M pins to SO-DIMM0 connector pins. SO-DIMM0 SO-DIMM1 = Motherboard Trace Lengths MCH-M SCS#[3:2], SCKE[3:2] (X - 3.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Figure 27. Control Routing Example FROM MCH-M Control signals Parallel Termination on Both Layers Control routing is shown in red. The majority of the control signal route is on an internal layer, both external layers are used for parallel termination R-pack placement. 5.2.3. Command Signals – SMA[12:0], SBS[1:0], SRAS#, SCAS#, SWE# There are two supported topologies for the command signal group.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R 5.2.3.1. Command Topology 1 Solution 5.2.3.1.1. Routing description for Command Topology 1 Refer to Figure 28 and Figure 31 for clarification of the description below. The command signal routing should transition from an external layer to an internal signal layer under the MCH-M.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R 1 Table 18. Command Signal Group Routing Guidelines Parameter Routing Guidelines Signal Group Command – SMA[12:0], SBS[1:0], SRAS#, SCAS#, SWE# Topology Daisy Chain Reference Plane Ground Referenced2 Characteristic Trace Impedance (Zo) 55Ω ±15% Trace Width Inner layers= 4 mils Figure Figure 28, Figure 31 Outer layer= 5 mils Trace to space ratio 1:2 (e.g.
® R ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Figure 29. Referencing Plane Stack-up 5.2.3.1.2. Command Group Signal Length Matching Requirements The command signals must be 1.0 inch to 3.0 inches shorter than their associated differential clock pairs SCK/SCK#[5:0]. Note that these requirements may change in a later revision of the design guide based on a post silicon simulation analysis.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Figure 30. Command Signal to SCK/SCK# Trace Length Matching Requirements SO-DIMM0 = Motherboard MCH-M SMA[12:0], SBS[1:0], RAS#, CAS#, WE# (X - 3.0") < = (CMD Length) = < ( X - 1.0" ) SCK[2:0] SCK/SCK#[2:0] Length = X SCK#[2:0] Note: CMD Lengths are measured from MCH-M pins to SO-DIMM0 connector pins SO-DIMM0 SO-DIMM1 = Motherboard MCH-M SMA[12:0], SBS[1:0], RAS#, CAS#, WE# (X - 3.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Figure 31. Command Routing Example for Topology 1 From MCH-M Serial Dampening Resistor Rd2d Parallel Termination NOTE: Red signals are command routing. The majority of the command signal route is on an internal layer.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 5.2.3.2. Command Topology 2 Solution 5.2.3.2.1. Routing Description for Command Topology 2 R Refer to Figure 32 and Figure 33 for clarification of the description below. The command signal routing should transition from an external layer to an internal signal layer under the MCH-M. Keep to the same internal layer until transitioning back to an external layer at the series resistor Rd2d.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Table 19. Command Signal Group Routing Guidelines Parameter Routing Guidelines Signal Group Command – SMA[12:0], SBS[1:0], SRAS#, SCAS#, SWE# Topology T Topology Reference Plane Ground Referenced2 Characteristic Trace Impedance (Zo) 55 Ω ± 15% Trace Width Inner layers= 4 mils Figure Figure 32, Figure 35 Outer layer= 5 mils Trace to space ratio 1:2 (e.g.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 5.2.3.2.2. Command Group Signal Length Matching Requirements The command signals, must be 1.0 inch to 3.0 inches shorter than their associated differential clock pairs SCK/SCK#[5:0]. Note that these requirements may change in a later revision of the design guide based on a post silicon simulation analysis. Length matching equation for SO-DIMM0: X1=SCK/SCK#[2:0] Y1=L1 +L2 of Figure 34 where, ( X1 – 3.0” ) ≤ Y1 ≤ ( X1 – 1.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Figure 34. Command Signal to SCK/SCK# Trace Length Matching Requirements SO-DIMM0 = Motherboard MCH-M Package SMA[12:0], SBS[1:0], RAS#, CAS#, WE# (X - 3.0") < = (CMD Length) = < ( X - 1.0" ) SCK[2:0] SCK/SCK#[2:0] Length = X SCK#[2:0] Note: CMD Lengths are measured from MCH-M pins to SO-DIMM0 connector pins SO-DIMM0 SO-DIMM1 = Motherboard MCH-M Package SMA[12:0], SBS[1:0], RAS#, CAS#, WE# (X - 3.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 5.2.3.2.3. R Command Routing Example for Topology 2 Solution Figure 35 is an example of a board routing for the command signal group. Figure 35. Command Routing Example for Topology 2 From MCH-M Series Dampening Resistor Rd2d Parallel Termination on Both layers NOTE: 76 Red signals are command routing.
® 5.2.4. ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Clock Signals – SCK[5:0], SCK#[5:0] The clock signal group includes the differential clock pairs SCK[5:0] and SCK#[5:0]. The MCH-M generates and drives these differential clock signals required by the DDR interface; therefore, no external clock driver is required for the DDR interface. The MCH-M only supports unbuffered DDR SODIMMs, three differential clock pairs are routed to each SO-DIMM connector.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R 1 Table 21.
® R 5.2.4.1. ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Clock Group Signal Length Matching Requirements The MCH-M provides three differential clock pair signals for each SO-DIMM. A differential clock pair is made up of a SCK signal and its complement signal SCK#.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Figure 38. SCK to SCK# Trace Length Matching Requirements SO-DIMM0 = MCH Package Lengths from Die Pad to Ball = Motherboard Trace Lengths MCH-M Package SCK0 SCK#0 SCK0 Length = X SCK#0 Length = X SCK1 Length = X SCK#1 Length = X SCK2 Length = X SCK#2 Length = X SCK1 SCK#1 MCH-M DIE SCK2 SCK#2 Note: Lengths are measured from MCH-M pad to SO-DIMM0 connector pins.
® R ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Figure 39.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R External trace lengths should be minimized. All internal and external signals should be ground referenced to keep the path of the return current continuous. The diagrams and table below depicts the recommended topology and layout routing guidelines for the DDR-SDRAM feedback signal. Figure 40. DDR Feedback (RCVEN#) Routing Topology MCH-M MCH-M RCVENIN# Ball RCVENOUT# Ball A A B Internal Layer Table 22.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Table 23. MCH-M DDR Signal Package Lengths DDR Data Signals Data Signal MCH-M Ball Package Length (inches) Data Signal MCH-M Ball Package Length (inches) SDQ0 G28 0.716 SDQ36 B13 0.639 SDQ1 F27 0.699 SDQ37 C13 0.552 SDQ2 C28 0.874 SDQ38 C11 0.588 SDQ3 E28 0.754 SDQ39 D10 0.626 SDQ4 H25 0.532 SDQ40 E10 0.533 SDQ5 G27 0.666 SDQ41 C9 0.605 SDQ6 F25 0.592 SDQ42 D8 0.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R DDR Data Signals Data Signal MCH-M Ball Package Length (inches) Data Signal MCH-M Ball Package Length (inches) SDQ33 C12 0.543 SCB5 C17 0.583 SDQ34 B11 0.596 SCB6 C15 0.54 SDQ35 C10 0.59 SCB7 D14 0.503 DDR Data Strobe Signals 84 DDR Clock Signals Data Signal MCH-M Ball Package Length (inches) Data Signal MCH-M Ball Package Length (inches) SDQS0 F26 0.651 SCK0 E14 0.453 SDQS1 C26 0.
® R 6. ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform AGP Port Design Guidelines For detailed AGP interface functionality (e.g., protocols, rules, signaling mechanisms), refer to the latest AGP Interface Specification, Revision 2.0, which can be obtained from http://www.agpforum.org. This design guide (Intel® 845MP/845MZ Chipset Platform Design Guide) focuses only on specific Intel 845MP/845MZ chipset platform recommendations. 6.1.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 6.2. R AGP 2.0 The AGP Interface Specification, rev. 2.0, enhances the functionality of the original AGP Interface Specification (rev. 1.0) by allowing 4X data transfers (i.e., 4 data samples per clock) and 1.5-volt operation. The 4X operation of the AGP interface provides for "quad-pumping" of the AGP AD (address/data) and SBA (side-band addressing) buses. That is, data is sampled four times during each 66MHz AGP clock.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R These signals are used in 4X AGP mode ONLY. Table 25. AGP 2.0 Data/Strobe Associations Data Associated Strobe in 1X Associated Strobe in 2X Associated Strobes in 4X AD[15:0] and C/BE[1:0]# Strobes are not used in 1X mode. All data is sampled on rising clock edges. AD_STB0 AD_STB0, AD_STB0# AD[31:16] and C/BE[3:2]# Strobes are not used in 1X mode. All data is sampled on rising clock edges.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Table 26. Layout Routing Guidelines for AGP 1X Signals 6.3.1.2. 1X signals Max.
® R ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Figure 41. AGP Layout Guidelines (Line:Space) Always 1:2 Strobe to Strobe# Routing Always 1:3 Strobe to Data Routing MCH-M 1:3 routing 6.0” max length +/-0.1” mismatch AGP Controller If the AGP interface is less than 6.0 inches, a 1:2 trace spacing is required for 2X/4X lines. These 2X/4X signals must be matched their associated strobe within ± 0.1 inches.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Table 27. Layout Routing Guidelines for AGP 2X/4X Signals 6.3.2.3. Trace Space (mils) Maximum Length (inch) (4 mil traces) Length Mismatch (inch) 2X/4X Timing Domain Set#1 6 8 2X/4X Timing Domain Set#2 6 2X/4X Timing Domain Set#3 6 Signal Relative To Notes ± 0.1 AGP_ADSTB0 and AGP_ADSTB0# AGP_ADSTB0, AGP_ADSTB0# must be the same length (±10 mils) 8 ± 0.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Table 29. AGP 2.0 Routing Guideline Summary Maximum Length Trace Spacing (4 mil traces) Length Mismatch Relative To Notes 1X Timing Domain 10 in 4 mils No Requirement N/A None 2X/4X Timing Domain Set#1 6 in 8 mils ± 0.1 in AD_STB0 and AD_STB0# AD_STB0, AD_STB0# must be the same length 2X/4X Timing Domain Set#2 6 in 8 mils ± 0.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R layer PCB design, the signals transition from one side of the board to the other. One extra 0.01-µF capacitor is required per 10 vias. The capacitor should be placed as close as possible to the center of the via field. 6.3.5.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R • AD_STB[1:0]# (pull down to ground) • SB_STB# (pull down to ground) The trace stub to the pull-up/pull-down resistor on 2X/4X timing domain signals should be kept to less than 0.1 inch, to avoid signal reflections from the stub. The pull-up/pull-down resistor value requirements are shown in Table 30. Table 30. AGP 2.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform The Vref divider network should be placed as close to the AGP interface as is practical to get the benefit of the common mode power supply effects. However, the trace spacing around the Vref signals must be a minimum of 25 mils to reduce crosstalk and maintain signal integrity. All resistors used in above reference generation schemes should have ± 1% tolerance. 6.3.9.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R 7. MCH-M PLL Requirements 7.1. MCH-M PLL Power Delivery VCCA1 and VSSA1, and VCCA0 and VSSA0 are power sources required by the MCH-M’s PLL clock generators. Figure 42. Intel 845MP/845MZ PLL0 Filter V_1P5_CORE VCCA0 (ball T13) L C PLL MCH MCH-M VSSA0 (ball U13) Length A Table 31. PLL0 Filter Routing Guidelines Parameter Routing Guidelines Trace Width 5 mils Trace Spacing 10 mils Trace Length – A 1.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Figure 43. Intel 845MP/845MZ PLL1 Filter V_1P5_CORE VCCA1 (ball T17) L C MCH PLL VSSA1 (ball U17) Length A Table 32. PLL1 Routing Guidelines Parameter Routing Guidelines Trace Width 5 mils Trace Spacing 10 mils Trace Length – A 1.5” Capacitor – C 33 µF Inductor – L 4.7 µH Table 33. Recommended Inductor Components for MCH-M PLL Filter Value Tolerance SRF Rated I DCR 4.7µH 10% 35 MHz 30 mA 0.
® R 8. ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Hub Interface The MCH-M and ICH3-M ballout assignments have been optimized to simplify the Hub Interface routing between these devices. Intel recommends that the Hub Interface signals be routed directly from the MCH-M to ICH3-M with all signals referenced to VSS. Layer transition should be kept to a minimum.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R The maximum hub interface data signal trace length is six inches. Each data signal must be matched within ± 200 mils of the HL_STB differential pair. There is no explicit matching requirement between the individual data signals. Table 36. Hub Interface Signals Signal 8.3.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Figure 45. Single HUBREF Voltage Divider 1.8V R1 4" MCH-M 4" ICH3-M HUBREF HIREF C1 R2 C1 C2 Figure 46. Locally Generated HUBREF Divider 1.8V R1 MCH-M 1.8V R1 <4" <4" ICH3-M HUBREF HIREF C2 NOTE: 8.5. R2 R2 C2 There is no C1. Hub Interface Decoupling Guidelines To improve I/O power delivery, use two 0.1-µF capacitors per each component (i.e. the ICH3-M and MCH-M).
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 9. I/O Subsystem 9.1. IDE Interface R This section contains guidelines for connecting and routing the ICH3-M IDE interface. The ICH3-M has two independent IDE channels. This section provides guidelines for IDE connector cabling and motherboard design, including component and resistor placement, and signal termination for both IDE channels.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Signal Max length (inch) Width (mils) Space (mils) Relative Mismatch max length (mils) Relative To Space with other signals (mils) IDE_SDCS3# IDE_SDDACK# IDE_SDDREQ IDE_SDIOW# Signal Group#ide2 8 4 7 ±5 IDE_PIORDY with IDE_PIORDY IDE_PDIOR# IDE_PDIOR# IDE_SIORDY And IDE_SIORDY with IDE_SDIOR# IDE_SDIOR# 8 Other signals INT_IRQ1 IDE_PDACTIVE # INT_IRQ15 IDE_SDACTIVE # Design Guide 101
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 9.1.1. R Primary IDE Connector Requirements Figure 47. Connection Requirements for Primary IDE Connector PCIRST_BUF#* PCIRST# 22 - 47 ohm Reset# PDD[15:0] 3.3V Primary IDE Connector PDA[2:0] PDCS1# PDCS3# PDIOR# PDIOW# PDDREQ 3.3V 8.2K-10K ohm 4.7K ohm PIORDY IRQ14 PDDACK# GPIOx PDIAG#/ CBLID# CSEL 10K ohm N.C. ICH3-M Pin32,34 *Due to ringing, PCIRST# must be buffered.
® R 9.1.2. ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Secondary IDE Connector Requirements Figure 48. Connection Requirements for Secondary IDE Connector PCIRST_BUF#* PCIRST# 22 - 47 ohm Reset# SDD[15:0] 3.3V Secondary IDE Connector SDA[2:0] SDCS1# SDCS3# SDIOR# SDIOW# SDDREQ 3.3V 8.2K-10K ohm 4.7K ohm SIORDY IRQ15 SDDACK# GPIOy PDIAG#/ CBLID# CSEL 10K ohm N.C. ICH3-M Pin32,34 *Due to ringing, PCIRST# must be buffered.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform • A 10-kΩ pull-down resistor to ground is on the PDIAG#/CBLID# signal is now required on the Secondary Connector. This change is to prevent the GPI pin from floating if a device is not present on the Secondary IDE interface. 9.2. PCI The ICH3-M provides a PCI Bus interface that is compliant with the PCI Local Bus Specification Revision 2.2.
® R ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Figure 50. ICH3-M AC’97 – Codec Connection Digital AC '97 2.1 Controller AC / MC / AMC RESET# AC '97 2.1 controller section of the ICH3-M SDOUT SYNC BIT_CLK Primary Codec SDIN 0 SDIN 1 AC / MC Secondary Codec 9.3.1. Four-Layer Layout Example Using the assumed 4-layer stack-up, the AC’97 interface can be routed using 5-mil traces with 5-mil space between the traces.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 9.3.2. R AC’97 Audio Codec Detect Circuit and Configuration Options The following provides general circuits to implement a number of different Codec configurations. Please refer to Intel’s White Paper Recommendations for ICHx/AC’97 Audio (Motherboard and Communication and Network Riser) for Intel’s recommended Codec configurations (available at the URL given in Section 9.3).
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Figure 51. Example Speaker Circuit VCC3_3 R Value is Im plem entation Specific Stuff Jum per to Disable Tim eout Feature (No Reboot) ICH3 SPKR Integrated Pulldown 9.3.5. 13K Ω - 38K Ω Effective Im pedance Due to Speaker and Codec Circuit R eff AC’97 Routing To ensure the maximum performance of the codec, proper component placement and routing techniques are required.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R • Bypassing and decoupling capacitors should be close to the IC pins, or positioned for the shortest connections to pins, with wide traces to reduce impedance. • All resistors in the signal path or on the voltage reference should be metal film. Carbon resistors can be used for DC voltages and the power supply path, where the voltage coefficient, temperature coefficient, and noise are not factors.
® R ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform • USB signals should be ground referenced. • Route USB signals using a minimum of vias and corners. This reduces reflections and impedance changes. • When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This reduces reflections on the signal by minimizing impedance discontinuities.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Table 40. USB Signals Signal USB Signals Group Width (mils) 4 Space (mils) Mismatch length (mils) 6 ± 75 USB_PN0 to USB_PN5 Relative To Signal differential pair Space with other signals (mils) 20 Notes Clock and PCI should be 50 mils away from USB signals (min) USB_PP0 to USB_PP5 9.4.4. Plane Splits, Voids and Cut-Outs (Anti-Etch) The following guidelines apply to the use of plane splits voids and cutouts. 9.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R To disable IOAPIC in BIOS: • ICH3-M: D31:F0; Offset: D1; bit 0 (0=disable); • Mobile Pentium 4 Processor-M: MSR 1Bh bit 11 (0 = disable) Figure 52. Minimum IOAPIC Disable Topology 33Ω Ω 10KΩ Ω PCIF0 APICD0 APICD1 CK-408 APICLK ICH3-M 9.5.2. PIRQ Routing Example PCI interrupt request signals E-H are new to the ICH3-M.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Figure 53 is an example. It is up to the board designer to route these signals in a way that will prove the most efficient for their particular system. A PCI slot can be routed to share interrupts with any of the ICH3-M’s internal device/functions (but at a higher latency cost). 9.6. SMBus 2.0/SMLink Interface The SMBus interface on the ICH3-M is the same as that on the ICH2-M.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Figure 54. SMBUS 2.0/SMLink Interface SPD data Host controller and slave interface Network interface card on PCI Temperature on thermal sensor SMBus SMBCLK Microcontroller SMBDATA ICH3-M SMLink SMLink0 SMLink1 Wire OR Intel(r) Motherboard LAN controller smbus_smlink_IF NOTE: 9.6.1. 9.6.1.1. Intel does not support external access of the ICH3-M’s Integrated LAN Controller via the SMLink interface.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Figure 55. Unified Vcc_Suspend Architecture Vsus Vsus Vsus SMBus DEVICES ICH3-M SMBus 9.6.1.4. The Unified Vcc_Core Architecture In this design, all SMBUS devices are powered by the Vcc_Core supply. This architecture allows none of the devices to operate in STR, but minimizes the load on Vcc_Suspend. Figure 56. Unified Vcc_Core Architecture Vcore Vsus Vsus SMBus DEVICES ICH3-M SMBus NOTES: 1.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Figure 57. Mixed Vcc_Suspend/Vcc_Core Architecture Devices running in Standby Vsus Vsus Non-Standby devices Vcore Vcore Vsus Vsus ICH3 Vcore Vsus BUS SWITCH SMBus 2.0 SMBus2.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 9.8. R FWH Signaling Voltage Compatibility Depending on the V_CPU_IO of the processor and the manufacturer of the FWH, there may be signaling voltage compatibility issues with the ICH3-M. The range of acceptable V_CPU_IO for the ICH3-M is 1.2 V to 2.5 V. If the processor core voltage is not within this range, translation logic will be required on the processor side before even considering the FWH.
® R ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform RTCX1 signal is amplified to drive internal logic as well as generate a free running full swing clock output for system use. This output ball of the ICHn is called SUSCLK. This is illustrated in Figure 59. Figure 59. RTCX1 and SUSCLK Relationship in ICH3-M Low-Swing 32.768kHz Sine Wave Source RTCX1 Internal Oscillator Full-Swing 32.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Figure 60. External Circuitry for the ICH3-M RTC +V3ALWAYS +V_RTC 1uF 1KΩ RTC_RST# 15KΩ 1uF 1KΩ 0.047uF BATT_SKT 1KΩ RTC_VBIAS 10MΩ RTC_X1 10pF 10MΩ 32.768KHz RTC_X2 10pF NOTES: 1. The exact capacitor value needs to be based on what the crystal maker recommends. (Typical values for C2 and C3 are 18 pF.) 2. VCCRTC: Power for RTC Well. 3. RTCX2: Feedback for the external crystal. 4.
® 9.9.2. ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R External Capacitors To maintain the RTC accuracy, the external capacitor C3 needs to be 0.047 µF, and the capacitor values C1 and C2 should be chosen to provide the manufacturer’s specified load capacitance (Cload) for the crystal when combined with the parasitic capacitance of the trace, socket (if used), and package. The following equation can be used to choose the external capacitance values: Equation 2.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 9.9.3. RTC Layout Considerations • Keep the RTC lead lengths as short as possible; around ¼ inch is sufficient. • Minimize the capacitance between Xin and Xout in the routing. • Put a ground plane under the XTAL components. • Don’t route switching signals under the external components (unless on the other side of the board). • The oscillator Vcc should be clean; use a filter, such as an RC lowpass, or a ferrite inductor.
® R ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Figure 62. A Diode Circuit to Connect RTC External Battery VCC3_3SBY 1K VccRTC 1.0uF A standby power supply should be used in a mobile system to provide continuous power to the RTC when available, which will significantly increase the RTC battery life and thereby the RTC accuracy. 9.9.5.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Note that VBIAS is also very sensitive to environmental conditions. 9.9.7. SUSCLK SUSCLK is a square waveform signal output from the RTC oscillation circuit. Depending on the quality of the oscillation signal on RTCX1 (largest voltage swing), SUSCLK duty cycle can be between 30-70%. If the SUSCLK duty cycle is beyond 30-70% range, it indicates a poor oscillation signal on RTCX1 and RTCX2.
® 9.10. ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Internal LAN Layout Guidelines The ICH3-M provides several options for integrated LAN capability. The platform supports several components depending on the target market. These guidelines use the 82562ET to refer to both the 82562ET and 82562EM. The 82562EM is specified in those cases where there is a difference. Table 41.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Table 42. LAN Design Guide Section Reference 9.10.1. Layout Section Figure 13-22 Reference ICH3-M – LAN Interconnect A General Routing Guidelines B,C,D 82562EH B 82562ET /82562EM C Dual Layout Footprint D Design Guide Section ICH3-M – LAN Interconnect Guidelines ICH3-M – LAN Interconnect Guidelines This section contains guidelines to the design of motherboards and riser cards to comply with LAN Connect.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Figure 64. Single Solution Interconnect L LAN_CLK LAN_RSTSYNC ICH3-M ICH3 LAN_RXD[2:0] LAN_TXD[2:0] Platform LAN Connect (PLC) Table 43. LAN Design Guide Point-to-Point Length Requirements Length Requirements From the Previous Figure 9.10.1.2. Configuration: A 82562EH L = 4.5” to 10” (Signal Lines LAN_RXD[2:1] and LAN_TXD[2:1] not connected) 82562ET L = 3.5” to 10” CNR L = 3” to 9” (0.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Figure 65. LAN_CLK Routing Example LAN_CLK LAN RXD0 9.10.1.3. Crosstalk Consideration Noise due to crosstalk must be carefully controlled to a minimum. Crosstalk is the key cause of timing skews and is the largest part of the tRMATCH skew parameter. tRMATCH is the sum of the trace length mismatch between LAN_CLK and the LAN data signals.
® R Note: ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Some suggestions are specific to a 4.5-mil stackup. • Maximum mismatch between the length of the clock trace and the length of any data trace is 0.5 inches (clock trace must be longest). See Table 44 below for summary of recommendations • Maintain constant symmetry and spacing between the traces within a differential pair. • Keep the signal trace lengths of a differential pair equal to each other.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Table 44. LAN Signals Signal Signals Group#lan1 LAN_RXD0 to LAN_RXD2 LAN_TXD0 to LAN_TXD2 Max length (inch) Widt h (mils) Space btwn diff pair (mils) Space btwn trans. recv. diff pair or other signals(mils ) Mismatc h relative max. (mils) Relative To Notes 10 (min 3.5) 4 *4 8 -500 LAN_JCLK Diff. Pair must be the same length (±10 mils) 4 4 7 100 +/-10 Signals Group#lan2 diff pair Diff.
® R ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform are not equidistant from the power or ground plane. Differential trace impedances should be controlled to be ~100 ohms. It is necessary to compensate for trace-to-trace edge coupling, which can lower the differential impedance by up to 10 ohms, when the traces within a pair are closer than 30 mils (edge to edge). Traces between decoupling and I/O filter capacitors should be as short and wide as practical.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Figure 67. Ground Plane Separation Separate Chassis Ground Plane Good grounding requires minimizing inductance levels in the interconnections and keeping ground returns short, signal loop areas small, and power inputs bypassed to signal return, will significantly reduce EMI radiation. Some rules to follow that will help reduce circuit inductance in both backplanes and motherboards.
® R 9.10.2.3.2. ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Ground Plane A layout split (100 mils) of the ground plane under the magnetic module between the primary and secondary side of the module is recommended. It is also recommended to minimize the digital noise injected into the 82562 common ground plane. Suggestions include optimizing decoupling on neighboring noisy digital components, isolating the 82562 digital ground using a ground cutout, etc. 9.10.2.3.3.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform • Use of an 82555 or 82558 physical layer schematic in a PLC design. The transmit terminations and decoupling are different. There are also differences in the receive circuit. Please follow the appropriate reference schematic or Ap-Note. • Not using (or incorrectly using) the termination circuits for the unused pins at the RJ-45/11 and for the wire-side center-taps of the magnetic modules.
® R 9.10.3.2. ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Power and Ground Connections Some rules to follow for power and ground connections: • For best performance place decoupling capacitors on the backside of the PCB directly under the 82562EH with equal distance from both pins of the capacitor to power/ground. • The analog power supply pins for 82562EH (VCCA, VSSA) should be isolated from the digital VCC and VSS through the use of ferrite beads.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Figure 68. 82562EH Termination The filter and magnetic component T1, integrates the required filter network, high-voltage impulse protection, and transformer to support the HomePNA* LAN interface. One RJ-11 jack (labeled “LINE” in the above figure) allows the node to be connected to the phoneline, and the second jack (labeled “PHONE” in the above figure) allows other downline devices to be connected at the same time.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Figure 69. Critical Dimensions for Component Placement A B C ICH3-M Magnetics Module Gilad Line RJ11 LPF Phone RJ11 EEPROM Table 45. 82562EH Home/PNA* Critical Dimensions for Component Placement 9.10.3.6.1. Distance Priority Guideline B 1 < 1 inch A 2 < 1 inch C 3 < 1 inch Distance from Magnetic Module to Line RJ11 This distance ‘B’ should be given highest priority and should be less then 1 inch.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 9.10.3.6.3. R Distance from LPF to Phone RJ11 This distance ‘C’ should be less then 1 inch. In regards to trace symmetry, route differential pairs with consistent separation and with exactly the same lengths and physical dimensions.
® R 9.10.4.4. ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 82562ET/82562EM Termination Resistors The 100-Ω (1%) resistor used to terminate the differential transmit pairs (TDP/TDN) and the 100-Ω (1%) receive differential pairs (RDP/RDN) should be placed as close to the Platform LAN Connect component (82562ET or 82562EM) as possible. This is due to the fact these resistors are terminating the entire impedance that is seen at the termination source (i.e.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Table 46. 82562ET / 82562EM Critical Dimensions for Component Placement 9.10.4.5.1. Distance Priority Guideline A 1 < 1 inch B 2 < 1 inch Distance from Magnetic Module to RJ45 The distance A in the above figure should be given the highest priority in board layout. The distance between the magnetic module and the RJ45 connector should be kept to less than one inch of separation.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R The most sensitive signal returns closest to the chassis ground should be connected together. This will result in a smaller loop area and reduce the likelihood of crosstalk. The effect of different configurations on the amount of crosstalk can be studied using electronics modeling software. 9.10.4.6.1.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R The dual footprint for this particular solution uses a SSOP footprint for 82562ET and a TQFP footprint for 82562EH. The combined footprint for this configuration is shown in the below two figures. Figure 73. Dual Footprint LAN Connect Interface L LAN_CLK ICH3-M ICH3 LAN_RSTSYNC 82562EH LAN_RXD[2:0] TQFP LAN_TXD[2:0] 8 2 5 6 2 E T S S O P Stub Figure 74.
® R ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform • No stubs should be present when 82562ET is installed. • Packages used for the Dual Footprint are TQFP for 82562EH and SSOP for 82562ET. • A 22-Ω resistor can be placed at the driving side of the signal line to improve signal quality on the LAN connect interface. • Resistor should be placed as close as possible to the component. • Use components that can satisfy both the 82562ET and 82562EH configurations (i.e.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 10. Platform Clock Routing Guidelines 10.1. Clock Generation Only one clock generator component is required in an Intel 845MP/845MZ chipset-based system. Clock synthesizers that meet the Intel CK-408 Clock Synthesizer/Driver Specification are suitable for an Intel 845MP/845MZ chipset based system. For more information on CK-408 compliance, refer to the CK-408 Clock Synthesizer/Driver Specification Document.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Table 48.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Figure 75. Processor BCLK Topology CPU# CPU CPU# CPU 100 MHz 100 MHz CPU BCLK0 BCLK1 Debug Port 100 MHz 100 MHz BCK# BCK MCH-M 66Buff CK-408 66Buff PCIF USB PCI PCI REFO PCI PCI 66IN AGP Connector 66 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz PCI HCLKINP CLK ICH3-M CLK66 PCICLK CLK48 CLK14 33 MHz 33 MHz 33 MHz 14.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R 10.2. Clock Control 10.2.1. CK-408 Delay Circuit Recommendation Ensure the processor gets power before receiving the clock. Follow Figure 76. Figure 76. ICH3-M Follows the CK-408 Power-up CK 408 VTT_PWRGD# VCC_CORE Delay Circuit 8-9ms 10.2.2. ICH3-M V_GATE SLP_S1# When asserted SLP_S1# indicates that the system is in the S1-M power state.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Figure 77. PWRDWN# to CK-408 V3.3S SLP_S1# PWRDWN# (CK-408) SLP_S3# NOTES: 1. CK-408 Minimum power up latency should be ≥ 100 µS to guarantee functionality of “AND logic”.
® R ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform • Iref pin (pin # 42) is connected to ground through a 475-Ohm (±1 % tol.) resistor – making the Iref as 2.32 mA. Figure 78.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Table 49. End of Line Termination Topology BCLK [1:0]# Routing Guidelines 10.3.1.2. Layout Guideline Value Illustration Notes BCLK Skew between agents 400 ps totalBudget:150 ps for Clock driver250 ps for interconnect Differential pair spacing S max. Figure 80 5, 6 Spacing to other traces 4 S- 5 S mils Figure 80 -- Line width 4.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R • Mult0 pin (pin #43) connected to HIGH – making the multiplication factor as 6. • Iref pin (pin # 42) is connected to ground through a 475-Ohm (± 1 % tol.) resistor – making the Iref as 2.32 mA. Figure 79. Source Shunt Termination Topology L1 RS L1' Clock Driver L2 L4 L2' L4' RS L3' L3 RT CPU or MCH-M RT Table 50.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Layout Guideline Value Illustration R Notes driver to Chipset length matching (L1+L2+L4) -190 mils BCLK0 – BCLK1 length matching ± 10 mils -- Rs Series termination value 33 Ω ± 5% 11 Rt Shunt termination value 55 Ω ± 1% (for 55 Ω MB impedance) 12 NOTES: 1. This number does not include clock driver common m. 2.
® R ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Figure 80. Clock Skew as Measured from Agent to Agent Figure 81. Trace Spacing 10.3.2. CLK66 Clock Group The driver is the clock synthesizer 66-MHz clock output buffer and the receiver is the 66- MHz clock input buffer at the MCH-M and the Intel ICH3-M. Note that the goal is to have as little skew between the clocks within this group.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Figure 82. Topology for CLK66 R1 A B Clock Driver MCH and ICH2 Table 51. CLK66 Routing Guidelines Parameter Routing Guidelines Clock Group CLK66 Topology Point to point Reference Plane Ground Referenced (Contiguous over entire Length) Characteristic Trace Impedance (Zo) 55 Ohms ± 15% Trace Width 4 mils Trace Spacing 20 mils Spacing to other traces 20 mils Trace Length – A 0.00” to 0.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Figure 83. Topology for AGPCLK to AGP Connector R1 A B C Trace on AGP Card Clock Driver AGP Connector AGP Device Figure 84. Topology for AGPCLK to AGP Device Down R1 A B Clock Driver AGP Device Table 52.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 10.3.4. R CLK33 Clock Group The driver is the clock synthesizer 33-MHz clock output buffer and the receiver is the 33-MHz clock input buffer at the Intel ICH3-M, FWH, Glue Chip, and SIO. Note that the goal is to have minimal (~ 0) skew between the clocks within this group, and also minimal (~ 0) skew between the clocks of this group and that of group CLK66. Figure 85.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Figure 86. Topology for CLK14 R1 A B Clock Driver ICH3 and SIO Table 54. CLK14 Routing Guidelines Parameter Routing Guidelines Clock Group CLK14 Topology Point to point Reference Plane Ground Referenced (Contiguous over entire Length) Characteristic Trace Impedance (Zo) 60 Ohms ± 15% Trace Width 5 mils Trace Spacing 10 mils Spacing to other traces 10 mils Trace Length – A 0.00” to 0.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 10.3.6. R PCICLK Clock Group The driver is the clock synthesizer 33-MHz clock output buffer and the receiver is the 33-MHz clock input buffer at the PCI devices on the PCI cards. Note that the goal is to have a maximum of ±1 ns skew between the clocks within this group, and also a maximum of ±1 ns skew between the clocks of this group and that of group CLK33. Figure 87.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Figure 88. Topology for PCICLK to PCI Slot R1 A B C Trace on PCI Card Clock Driver PCI Connector PCI Device Table 56.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 10.3.7. R USBCLK Clock Group The driver is the clock synthesizer USB clock output buffer and the receiver is the USB clock input buffer at the Intel ICH3-M. Note that this clock is asynchronous to any other clock on the board. Figure 89. Topology for USB_CLOCK R1 A B Clock Driver ICH2 Table 57.
® R ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 11. Platform Power Guidelines 11.1. Definitions Suspend-To-RAM (STR): In the STR state, the system state is stored in main memory and all unnecessary systemlogic is turned off. Only main memory and logic required to wake the system remain powered. Full-power operation: During full-power operation, all components on the motherboard remain powered.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R 11.2. Platform Power Requirements 11.2.1. Platform Power Delivery Architectural Block Diagram Figure 90. Platform Power Delivery Block Diagram Mobile Processor VCC_CORE = IMVP-III VCC_VID = 1.2V DDR200 X 2 Or DDR266 X 2 System Bus 400 MT/S AGP AGP4X(1.5V) 1.06GB/s +V1.5S +V3.3S +V5S +V12S MCH-M PC1600/ 2100 VTT = VCC_CORE +V1.5S +V1.8S +V2.5 +V1.25 +V2.5 +V1.25 8-Bit Hub Interface 266MB/s USB +V3.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R 11.3. Voltage Supply 11.3.1. Power Management States Table 58. Power Management States SIGNAL STATE 11.3.2.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Signal Names Voltage (V) Current (A)* Tolerance + 9% AC 11.3.3. 11.3.3.1. R Enable Description PLL and VID circuitry. Power Supply Control Signals SLP_S3# SLP_S3# is a signal coming from the ICH3-M. Deassertion of SLP_S3# enables the outputs for the following rails: +V1.25, +V1_5S, +V1_8S, +V3_3S, +V5S, and +V12S. SLP_S3# will be asserted when the system enters S3/S4/S5 or powers off.
® R ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform the voltage at the base of the PNP transistor. By connecting the emitter of the NPN transistor to the 1.8 V plane, current will not flow from the 3.3-V supply into 1.8-V plane when the 1.8-V plane reaches 1.8 V. Figure 91. Example 1.8-V/3.3-V Power Sequencing Circuit +1.8V +3.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Figure 92. Example 3.3-V/V5REF Sequencing Circuitry V C C S u p p ly (3 .3 V ) 5 V S u p p ly 1 K 1 u F V R E F T o S y s te m T o S y s te m In compliance with USB 2.0 specification requirements for continuous short conditions, V5REF_Sus pins must be connected to 5 V. 5VREF_Sus affects 5-V tolerance for all USB signals, both over-current and data pins. USB 2.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Figure 94. V5REF_Sus Option 1: +V5_Always Not Available in Platform +V5 or +V5S Customer specific or Intel recommended USB power circuit +3.3V_Always D1* V5Ref_Sus1 V5Ref_Sus2 D2* USB Power (5V) 0.1uF ICH3-M Customer specific or Intel recommended USB interface circuits USB D+ USB D- GND D1 and D2 are BAT54 or Equivalent Schottky Diode 11.4.3.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 11.5. R Decoupling Recommendations Intel recommends proper design and layout of the system board bulk and high frequency decoupling capacitor solution to meet the transient tolerances for each component. To meet the component transient load steps, it is necessary to properly place bulk and high frequency capacitors close to the component power and ground pins. 11.5.1.
® R ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Two 0.1 µF, 0603, X7R capacitors and one 4.7 µF, X5R capacitors should be placed between the VCCPAUX supply pins and the VSS ground pins. Place the all capacitors as close to the ICH3-M package as possible, but ensure the 0603 capacitors are the closest to the package. Connections should be done to minimize loop area and loop inductance of these capacitors. 11.5.3.2. 3.3-V Power Supply Rails Twelve 0.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R the MCH-M DDR system memory interface and must be placed perpendicular to the MCH-M with the power (2.5 V) side of the capacitors facing the MCH-M. The trace from the power end of the capacitor should be as wide as possible and it must connect to a 2.5-V power ball on the outer row of balls on the MCH-M. Each capacitor should have their 2.5-V via placed directly over and connected to a separate 2.
® R ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 11.5.10. 1.25-V DDR VTT Low Frequency Bulk Decoupling Requirements The VTT Termination Island requires low frequency bulk decoupling. Place one 220-µF electrolytic capacitor at each end of the termination island. The power end of the capacitors must connect to the Vtt termination island directly, and the ground end of the capacitors must connect to ground. Also, the output of the 1.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R 11.5.14. 3.3-V General LAN Decoupling • All Vcc pins should be connected to the same power supply. • All Vss pins should be connected to the same ground plane. • Four to six decoupling capacitors, including two 4.7-µF capacitors are recommended • Place decoupling as close as possible to power pins. 11.6. 3.
® R ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Figure 95. DDR Power Delivery Block Diagram +V5 Switching Regulator Vin +VDDR2.5 Vout Sense Adj. 10K + 10K + +VDDREF - +V5 Switching Regulator Vin Vout +VDDR1.25 Sense Adj. 11.7.1. DDR Memory Bypass Capacitor Guidelines Discontinuities in the DDR signal return paths will occur when the signals transition between the motherboard and the SO-DIMMs. To account for this ground to 2.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform DDR signals and for optimal MCH-M power delivery. The copper fingers must be kept as wide as possible in order to keep the loop inductance path from the 2.5-V voltage regulator to the MCH-M at a minimum. In the areas where the copper flooding necks down around the MCH-M make sure to keep these neck down lengths as short as possible. The 2.5-V copper flooding under the SO-DIMM connectors must encompass all the SO-DIMM 2.
® R 11.7.3. ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Intel 845MP/845MZ Chipset DDR Reference Board Power Delivery Figure 96 shows the power delivery architecture for the Intel 845MP/845MZ Chipset DDR memory subsystem. This power delivery example provides support for the suspend-to-RAM (STR) and the full Power-on State. Figure 96. Intel 845MP/845MZ Chipset DDR Power Delivery Example +VDC DDR VR Vout = 2.5V DDR VR Vout = 1.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R (the top 3 listed) and the MCH-M requirements (next row of 3) and finally the termination voltage and current requirements. For convenience, tolerances are given in both % and Volts though validation should be done using the spec exactly as it is written. The voltage specs are clearly defined under “Specification Definition”. If this states a tolerance in terms of volts (as Vref says ± 0.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Table 61. DDR SDRAM Memory Voltage & Current Specification Name "Vdd" "Vddq" "Vref" PURPOSE CORE SUPPLY VOLTAGE, STATIC I/O SUPPLY VOLTAGE , STATIC I/O REFERENCE SUPPLY VOLTAGE, STATIC SPECIFICATION DEFINITION Vdd Vddq Vref = (Vdd/2) ±0.050 V VOLTAGE Nominal (V) 2.500 2.500 1.250 TOLERANCE (±%) 8.0% 8.0% 4.0% TOLERANCE (±-V) 0.200 0.200 0.050 MAX ABSOLUTE SPEC VALUE (V) 2.700 2.700 1.400 ((2.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Table 62. MCH-M DDR Voltage and Current Specifications Name "VCCSM" "SDREF" "Vtt"= "SMRCOMP" PURPOSE MCH-M DDR SUPPLY VOLTAGE (I/O), STATIC MCH-M REFERENCE SUPPLY VOLTAGE, STATIC SMRCOMP TERMINATION SUPPLY VOLTAGE, STATIC DEFINITION VCCSM SDREF=(VCCSM/2) ±2% Vtt = ("Vref")+/-0.040V VOLTAGE Nominal (V) 2.500 1.250 1.250 TOLERANCE (±%) 5.0% 2.0% 3.2% TOLERANCE (±V) 0.125 0.025 0.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Table 63. Termination Voltage and Current Specifications Name "Vtt" Description PURPOSE TERMINATION SUPPLY VOLTAGE, STATIC DEFINITION Vtt = ("Vref")± 0.040 V VOLTAGE Nominal (V) 1.250 TOLERANCE (±%) 3.2% TOLERANCE (±V) 0.040 MAX ABSOLUTE SPEC VALUE (V) 1.440 (((2.5 V+8%)/2)+0.050 V)+0.040 MIN ABSOLUTE SPEC VALUE (V) 1.060 (((2.5 V-8%)/2)-0.050 V)-0.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Table 64. MCH-M DDR I/O NAME VCCSM1 SDREF PURPOSE MCH-M DDR SUPPLY VOLTAGE (I/O), STATIC MCH-M REFERENCE SUPPLY VOLTAGE, STATIC VCCSM SDREF =( VCCSM± 5%) / 2 VOLTAGE Nominal (V) 2.500 "± 5%" 1.250 "± 2%" TOLERANCE (+/-V) 0.125 0.025 Vmax(V) 2.625 1.275 Vmin(V) 2.375 1.225 Ivccsm (max) Isdref (max) 1.400 0.010 Imax NOTE: MCH-M VREF REQUIREMENTS: the MCH-M core is called "VCCSM" =+2.5 V ±5%.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R The implementation of a buffer is also required by the DDR. The same VREF may be used for both MCH-M and the DDR as well. 11.7.4.2. DDR VREF Requirements Making the same calculations for the DDR loading, results to find the max Vref load of 1 mA, a divider is STILL NOT feasible here as the load of 1 mA causes unacceptable drop across even small Rs, which waste power. Table 66.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 11.7.5. R DDR SMRCOMP Resistive Compensation The MCH-M uses a compensation signal to adjust the system memory buffer characteristics over temperature, process, and voltage variations. The DDR system memory (SMRCOMP) must be connected to the DDR termination voltage (1.25 V) through a 30 Ω ±1% resistor and one 0603 0.1-µF decoupling capacitor to ground.
® R ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform The ground flood should be viaed through to the ground plane with no less than 12-16 vias under the part. It should be well connected. For all power connections, heavy duty and/or dual vias should be used. It is imperative that the standard signal vias and small traces not be used for connecting decoupling caps and ground floods to the power and ground planes. VddA should be generated by using a CLC filter.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Figure 98.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R 12. System Design Checklist 12.1. Host Interface Table 68. Resistor Recommendations Mobile Intel Pentium 4-M – Resistor Recommendations Signal System Pull-up/ Pull-down H_A[35:3]# Connect A[31:3]# to MCH-M. Leave A[35:32]# as No Connect H_RESET# Pull-up to VCC_CORE 51 Ω ±1% H_IERR# Pull-up to VCC_CORE 10 kΩ H_FERR# Pull-up to VCC_CORE COMP[1:0] Pull-down to GND 51.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Mobile Intel Pentium 4-M – Resistor Recommendations Signal System Pull-up/ Pull-down Ω Notes This implementation is strongly discouraged for system boards that do not implement an onboard debug port. As an alternative, group 2 (TESTHI[5:2]), and the ITPCLKOUT[1:0] pins may be tied directly to the processor VCC. This has no impact on system functionality.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Mobile Intel Pentium 4-M – Resistor Recommendations Signal System Pull-up/ Pull-down Notes Ω 9 VCC_CORE NOTE: 12.2. Default tolerance for resistors is ± 5% unless otherwise specified. In Target Probe (ITP) Table 69.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 12.3. R Thermal Sensor Table 70. Thermal Sensor Signals Mobile Intel Pentium 4 Processor-M – Thermal Sensor Signal System Pull-up/Pulldown Ω ADD[1:0] Pull-up to V3.3S 1 kΩ STBY# Pull-up to V3.3S 10 kΩ SMBDATA Pull-up to V3.3S 10 kΩ SMBCLK Pull-up to V3.3S 10 kΩ THRM_ALERT# Pull-up to V3.3S 10 kΩ DXP, DXN 12.4.
® 12.6. ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R CK-408 Clock Checklist Table 73. Resistor Recommendation Checklist Items Recommendations Reason/Impact 66_BUFF0 Connect to MCH-M. Series resistor of 33 Ω ± 1% Refer to the reference schematics. 66_BUFF1 Connect to ICH3-M. Series resistor of 33 Ω ± 1% Refer to the reference schematics. 66_BUFF2 Connect to AGP. Series resistor of 33 Ω ± 1% Refer to the reference schematics. 66_INPUT No Connect.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Checklist Items 188 Recommendations R Reason/Impact SEL_2 Pull down to ground through a1 K ± 5% resistor. Refer to the reference schematics. SCLK Connect to SO-DIMMs. Refer to the reference schematics. SDATA Connect to SO-DIMMs. Refer to the reference schematics. USB_48MHZ Connect to ICH3-M. 33 Ω ±5% series resistor Refer to the reference schematics. VDD Connect to VCC3_CLK and decouple with 0.
® 12.7. ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R DDR SO-DIMM0 Connector Table 74. DDR S0-DIMM0 Recommendations Checklist Items S#[0] Recommendations Connect to SCS#[0] pin on MCH-M Connect to a 56 ohm ± 5% parallel termination resistor tied to Vtt (1.25 V DDR Termination Voltage) S#[1] Connect to SCS#[1] pin on MCH-M Connect to a 56 ohm ± 5% parallel termination resistor tied to Vtt (1.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Checklist Items Recommendations R Reason/Impact DM[8:0] / DQS[17:9] Connect to Ground Refer to the reference schematics. CK[2:0] Connect to the MCH-M SCK[2:0] pins Refer to the reference schematics. CK#[2:0] Connect to the MCH-M SCK#[2:0] pins Refer to the reference schematics. SA[2:0] Connect to ground. Refer to the reference schematics.
® 12.8. ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R DDR SO-DIMM1 Connector Table 75. DDR S0-DIMM0 Recommendations Checklist Items S#[0] Recommendations Connect to SCS#[2] pin on MCH-M Connect to a 56 ohm ± 5% parallel termination resistor tied to Vtt (1.25 V DDR Termination Voltage) S#[1] Connect to SCS#[3] pin on MCH-M Connect to a 56 ohm ± 5% parallel termination resistor tied to Vtt (1.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Checklist Items SA[2:0] Recommendations Connect SA2 and SA1 to ground Connect SA0 to V3.3S R Reason/Impact Refer to the reference schematics. Connect to SMB_DATA and SMB_CLK with 10KΩ resistor pull-ups to +V3.3Always Refer to the reference schematics. VDD Connect to DDR 2.5 V Refer to the reference schematics. VDDQ Connect to DDR 2.5 V Refer to the reference schematics.
® 12.9. ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R MCH-M Signals Table 77.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Table 78. Miscellaneous Signals MCH-M – Miscellaneous Signals Signal AGP_RCOMP Ω System Pull-up/Pull-down Notes 36.5 Ω ± 1% Connect to GND 9 For AGP devices Referencing a 55-Ω board impedance 36.5 Ω ± 1% HUB_RCOMP Pull-up to VCC1_8 SMRCOMP Connect to DDR Termination Voltage (Vtt) through a 30.1 Ω ± 1% pull-up resistor. Referencing a 55-Ω board impedance Connect to a 0.1-µF capacitor tied to ground.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Table 80. Reference Voltage Dividers MCH-M – Reference Voltage Dividers* Signal System Pull-up/Pulldown Ω Voltage divider with w/ cap and 0 Ω in parallel to bottom resistor 301 Ω ± 1% (both) F Notes 9 SM_VREF HUB_VREF 0.01 µF Design Guide Place divider pair in middle of bus. Divided voltage is [1/2]*1.8 V.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 12.10. R AGP Table 81. Resistor Recommendation AGP – Resistor Recommendations Signal System Pull-up/Pulldown Ω Series Damping AGP_SBSTB# Notes Have internal pull-downs. AGP_ADSTB[1:0]# ST[0] Pull-down to GND 2 kΩ ST[0] signal pulled low indicates that system memory is DDR SDRAM ST[2:1] Pull-up to V1.5S 8.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Table 82. Decoupling Recommendation AGP– High Speed Decoupling Recommendations* Signal Configuration F Qty Notes AGP_VREF Decouple to GND 0.1 µF 2 Place one capacitor near MCH-M and one near AGP connector +V1-5S_AGP Decouple to GND 150 µF 2 0.1 µF 7 Distribute as close as possible to AGP connector VDDQ and VDDQ1.5 Quadrants 22 µF 1 100 µF 1 0.1 µF 3 22 µF 2 0.1 µF 2 22 µF 1 0.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 12.11. R ICH3-M Checklist Table 84. PCI Resistor Recommendation ICH3-M – PCI Resistor Recommendations Signal Ω System Series Damping Notes Pull-up/Pull-down PCI_FRAME#, PCI_IRDY#, PCI_TRDY#, PCI_STOP# Pull-up to V3.3S 8.2 kΩ Alternative system can be 2.7 kΩ pull-up to V5S PCI_PERR#, PCI_SERR#, PCI_DEVSEL#, PCI_LOCK# Pull-up to V3.3S 8.2 kΩ Alternative system can be 2.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Table 85. System Management Interface (SM-BUS) ICH3-M – System Management Interface Signal Ω System Pull-up/Pull-down Notes SM_LINK[1:0] Pull-up to V3_3ALWAYS 4.7 kΩ SM_INTRUDER# Pull-up to V3_3ALWAYS 100 kΩ Pull signal to VCCRTC (VBAT) if not needed SMB_ALERT#/ GPIO11 Pull-up to V3_3ALWAYS 10 kΩ Pull-up only if using this signal as SMB_ALERT# SMB_CLK, SMB_DATA Pull-up to V3_3ALWAYS 10 kΩ 9 Table 86.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R ICH3-M – Power Management Interface Signal System Ω Series Damping Notes Pull-up/Pulldown DPRSLPVR , PM_SLP_S3#, PM_SLP__S5# External pull-up/down not required.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Table 88. LPC Interface ICH3-M – LPC Interface Signal Ω System Notes 9 Pull-up/Pull-down LPC_AD[3:0], LPC_DRQ#[1:0] Has integrated weak internal pull-up Table 89. USB Interface ICH3-M – USB Interface Signal Ω System Series Damping Notes 9 Pull-up/Pull-down USB_RBIAS 18.2 Ω ± 1% Pull-down to GND 22.6 Ω for ICH3-M B0 ES Samples only HUB_VREF 12.12. HUB Interface Table 90.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Table 92. RTC Circuitry ICH3-M – RTC Circuitry Recommendations Signal Ω System Notes 9 Pull-up/Pull-down CLK_VBIAS CLK_RTCX1, CLK_RTCX2 Connect 10 MΩ across to CLK_RTCX1 and 0.047 µF decoupling cap in series with 1 kΩ Connect a 32.768 kHz crystal oscillator across these pins with a 10 MΩ resistor and use 12 pF decoupling caps at each signal.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R Table 94. Decoupling Recommendation ICH3-M – High Speed Decoupling Recommendations Signal +VCC_CORE +V1.8S Configuration F Pull-down to GND 0.1 µF 2 1.0 µF, 16 V 1 0.1 µF 7 22 µF 1 100 µF 1 0.1 µF 3 10 µF 1 0.1 µF 2 22 µF 1 Pull-down to GND 0.1 µF 12 Pull-down to GND 22 µF 2 Pull-down to GND 0.1 µF 8 22 µF 1 0.1 µF 2 4.7 µF 1 22 µF 1 Pull-down to GND +V1.8Always +V1.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 12.13. R USB Checklist Table 97.Resistor Recommendations USB – Resistor Recommendations Signal System Pull-up/Pull-down Ω Series Damping USB_PN[5:0], USB_PP[5:0] USB_OC[5:0] NOTE: Notes 9 Place near ICH3-M 10 kΩ Pull-up to V3.3Always Pull-up voltage rail will depend on usage Default tolerance for resistors is ± 5% unless otherwise specified. Table 98.
® 12.15. ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R LAN/HomePNA Checklist Table 100.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 12.17. R Interrupt Interface Table 102. Interrupt Interface Recommendation Checklist Items 206 Recommendations Reason/Impact PIRQ[D:A]# These signals require a pull-up resistor. Recommend a 2.7 KΩ pull-up resistor to VCCVCC5 or 8.2 KΩ to VCCCC3_.3. In Non-APIC Mode the PIRQx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in the Interrupt Steering section.
® 12.18. ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R GPIO Table 103. GPIO Recommendation Checklist Items GPIO Balls Recommendations GPIO[7, 5:0]: • These balls are in the Main Power Well. Pullups must use the VCC3_3 plane. • Unused core well inputs must be pulled up to VCC3_3. • GPIO[1:0] can be used as REQ[B:A]#. • GPIO[1] can be used as PCI REQ[5]#. • GPIO[5:2] can be used as PIRQ[H:E]#.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 12.19. R CPU Signals Table 104. CPU Signals Signal Group Recommendation Reason FERR#,IERR#,PROCHOT#, *THRMTRIP# **Translation circuit is required between CPU and ICH3 Voltage translation Pullup at Rtt_CPU=56_5% Pullup at Vcc_Rcvr=300_5% LINT1/INTR, LINT0/NMI, DPSLP#, SLP#, STPCLK#, IGNNE#, SMI#, A20M#, CPUPERF# Pullup 200 Ohm_5% to Vtt_CPU VCC_CORE<1.3 V PWRGOOD Pullup 300 Ohm_5% to Vtt_CPU VCC_CORE<1.
® 12.21. ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform R HomePNA - Resistor Recommendation Table 106. HomePNA - Resistor Recommendation HomePNA – Resistor Recommendations* Signal System Pull-up/Pull-down Ω TX_EN, MDC, MDIO, ISOLATE, HMII/JORD Pull-down to GND 1 kΩ XO Pull-down 121 Ω ± 1% RX_TX_P, RX_TX_N Pull-up 51.
® ® ® Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform 13. Customer Reference Board Schematics See the following page for the customer reference board schematics.
A B C D E INTEL (R) 845MP/MZ PLATFORM SCHEMATICS 4 4 PG 5 Fan Header CPU Thermal Sensor PG 5 PG 35 CK-408 Clocking PG 14 PG 3,4,5 PG 10 PSB 100MHz x4, 64b (3.2GB/s) AGP 1.5V, 66MHz, 1\2\4x, 32b INTEL(R) 845MP/MZ MCH-M PG 9 DDR SDRAM 2.5V, 200/266MHz, 64b (1.6/2.
A B C D E SCHEMATIC ANNOTATIONS AND BOARD INFORMATION 4 3 2 Voltage Rails I C / SMB Addresses +VDC +VCC_CORE +VCC_VID +V1.25 +V1.5S +V1.8ALWAYS +V1.8 +V1.8S +V2.5 +V3.3ALWAYS +V3.3 +V3.3S +V5 +V5S +V12S -V12S Device Clock Generator SO-DIMM0 SO-DIMM1 Thermal Diode Smart Battery Smart Battery Charger Smart Selector Primary DC system power supply (10 to 17V) Core voltage for CPU 1.2V For CPU PLL and VID circuitry DDR Termination voltage 1.5V switched power rail (off in S3-S5) 1.
A B C D E U18B H_ADSTB#0 7 H_REQ#4 H_REQ#3 H_REQ#2 H_REQ#1 H_REQ#0 H_REQ#[4:0] 3 7 H_ADSTB#1 BR3# BR2# BR1# BR0# U6 W4 Y3 H6 D15# D14# D13# D12# D11# D10# D9# D8# D7# D6# D5# D4# D3# D2# D1# D0# DINV0# STBN0# STBP0# 56 56 56 7 7 7 H_D#31 H25 H_D#30 K23 H_D#29 J24 H_D#28 L22 H_D#27 M21 H_D#26 H24 H_D#25 G26 H_D#24 L21 H_D#23 D26 H_D#22 F26 H_D#21 E25 H_D#20 F24 H_D#19 F23 H_D#18 G23 H_D#17 E24 H_D#16 H22 G25 H_DINV#1 K22 H_DSTBN#1 J23 H_DSTBP#1 D31# D30# D29# D28# D27# D26# D25# D24# D23#
H1 VSS1 H4 VSS2 H23 VSS3 H26 VSS4 A11 VSS5 A13 VSS6 A15 VSS7 A17 VSS8 A19 VSS9 A21 VSS10 A24 VSS11 A26 VSS12 A3 VSS13 A9 VSS14 AA1 VSS15 AA11 VSS16 AA13 VSS17 AA15 VSS18 AA17 VSS19 AA19 VSS20 AA23 VSS21 AA26 VSS22 AA4 VSS23 AA7 VSS24 AA9 VSS25 AB10 VSS26 AB12 VSS27 AB14 VSS28 AB16 VSS29 AB18 VSS30 AB20 VSS31 AB21 VSS32 AB24 VSS33 AB3 VSS34 AB6 VSS35 AB8 VSS36 AC11 VSS37 AC13 VSS38 AC15 VSS39 AC17 VSS40 AC19 VSS41 AC2 VSS42 AC22 VSS43 AC25 VSS44 AC5 VSS45 AC7 VSS46 AC9 VSS47 AD1 VSS48 AD10 VSS49 AD12 VSS50 A
A B C D E CPU Thermal Sensor +V3.3S U12 2 3 4 10 6 R246 3 H_THERMDA 0 C425 2200PF 3 VCC DXP DXN ADD0 ADD1 STBY# 15 SMBDATA SMBCLK ALERT# 12 14 11 GND1 GND2 NC1 NC2 NC3 NC4 NC5 1 5 9 13 16 H_THERMDC R192 0 7 8 Layout Note: Route H_THERMDA and H_THERMDC on same layer.
1 9 AGP_AD[31:0] 9 AGP_CBE#[3:0] Correct BD IPN is: A56859-008 Correct BD (MZ) IPN is: A83134-001 845MP/MZ 1 of 3 A 9 9 9 9 9 9 9 9 AGP_FRAME# AGP_DEVSEL# AGP_IRDY# AGP_TRDY# AGP_STOP# AGP_PAR AGP_REQ# AGP_GNT# For GRCOMP resistor value: 2/3 of board impedance. 40.2 ohm for 60 board impedance. 36.5 ohm for 55 board impedance. 9 14 9 9 9 9 9 9 9 9 9 9 9 9 9 B 2 C Design Guide M_RCOMP Title D +V1.
A +V1.5S B C D E 9,36,40 H_D#[63:0] 3 +V1.5S_MCH 2 U20B 1 NO_STUFF_0.01_1% 4 2 1 N14 N16 P13 P15 P17 R14 R16 T15 U14 U16 VCCCORE0 VCCCORE1 VCCCORE2 VCCCORE3 VCCCORE4 VCCCORE5 VCCCORE6 VCCCORE7 VCCCORE8 VCCCORE9 L29 N26 L25 M22 N23 NO_STUFF_0.01_1% VCCHL1 VCCHL2 VCCHL3 VCCHL4 VCCHL5 2 1 1 +V1.5S_MCH 2 C122 - 33UF 2 T17 T13 VCCGA1 VCCHA1 U17 U13 VSSGA2 VSSHA2 1 + L5 4.7UH + C121 - 33UF 2 1 2 L6 4.
A B C D E 14,15 CLK_ICH66 Layout:Place 0 Ohm close to "T" 2 1 VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 1 3 5 7 9 11 13 15 17 19
A B C D E +V1.5S_AGP 4 3 +V1.5S_AGP 6 AGP_ADSTB1# 6 AGP_ADSTB1 R126 R123 6 AGP_ADSTB0# 8.2K 8.
A B C D E 9 21 33 45 57 69 81 93 113 131 143 155 157 167 179 191 10 22 34 36 46 58 70 82 92 94 114 132 144 156 168 180 192 J43B CON200_DDR-SODIMM VSS1 3 VDD1 VSS2 15 VDD2 VSS3 27 VDD3 VSS4 39 VDD4 VSS5 51 VDD5 VSS6 63 VDD6 VSS7 75 VDD7 VSS8 87 VDD8 VSS9 103 VDD9 VSS10 125 VDD10 VSS11 137 VDD11 VSS12 149 VDD12 VSS13 159 VDD13 VSS14 161 VDD14 VSS15 173 VDD15 VSS16 185 VDD16 VSS17 4 VDD17 VSS18 16 VDD18 VSS19 28 VDD19 VSS20 38 VDD20 VSS21 40 VDD21 VSS22 52 VDD22 VSS23 64 VDD23 VSS24 76 VDD24 VSS25 88 VD
A B C D 10,12 M_DQS_R[8:0] 4 M_DATA_R_[63:0] 10,12 M_DQS_R8 R377 22 M_DQS8 M_DQS_R7 R381 22 M_DQS7 M_DQS_R6 R384 22 M_DQS6 M_DQS_R5 R380 22 M_DQS5 M_DQS_R4 R383 22 M_DQS4 M_DQS_R3 R378 22 M_DQS3 M_DQS_R2 R382 22 M_DQS2 M_DQS_R1 R379 22 M_DQS1 M_DQS_R0 R376 22 M_DQS0 M_DATA0 4RP46D 22 5 M_DATA_R_0 M_DATA32 4RP50D 22 5 M_DATA_R_32 M_DATA1 3RP46C 22 6 M_DATA_R_1 M_DATA33 3RP50C 22 6 M_DATA_R_33 M_DATA2 2RP46B 22 7 M_DATA_R_2 M_DATA34 2RP50B 22 7 M_DATA_R_34 M_DATA3
3 5 4 6 56 56 1 1 2 3 4 3 4 6 4 1 2 5 RP91C 56 3 8 8 7 6 5 5 6 7 8 7 8 5 6 6 1 5 8 7 8 1 2 3 4 4 3 2 1 1 2 3 4 4 3 2 1 1 2 3 4 4 3 2 1 1 2 3 4 4 3 2 1 1 56 R385 4 56 R386 1 2 7 6 6 7 5 5 5 6 7 8 8 7 6 5 5 6 7 8 8 7 6 5 5 6 7 8 8 7 6 5 5 6 7 8 8 7 6 5 2 8 3 2 4 4 4 3 2 1 1 2 3 4 4 3 2 1 1 2 3 4 4 3 2 1 1 2 3 4 4 3 2 1 1 2 3 56 56 4 RP91A RP91B 3 7 3 56 56 56 56 56 56 RP78D 56 M_DQS_R5 2 RP83A RP83B RP83C RP83D RP69D RP69C 56 RP91D M_DQS_R6 M_A_SR_8 M_A_SR_9 M_A_SR_10 M_A_
A B C D E 4 4 +V2.5_DDR 10,39 +V2.5 7,8,39,40 One 0.1uF cap per power pin. Place each cap close to pin. R171 2 1 NO_STUFF_0.01_1% C540 0.1UF C538 0.1UF C547 0.1UF C548 0.1UF C537 0.1UF C545 0.1UF C539 0.1UF C546 0.1UF C536 0.1UF C511 0.1UF C509 0.1UF C283 150uF C341 150uF C325 150uF C306 150uF C506 0.1UF C504 0.1UF C512 0.1UF C510 0.1UF C505 0.1UF C503 0.1UF Layout note: Place capacitors between and near DDR connector if possible.
A B C Only need the AND gate if S1M is supported NO_STUFF_0 5 1 16,21,29,34,39,40 PM_SLP_S3# 2 4,5,6,9,10,17,19,23,28,29,30,31,32,33,36,37,40 CK408PWRDN# 4 +V3.3S_CLKSRC 74AHC1G08 U60 1 3 Used for D3 Hot C431 C115 22UF 1UF Place crystal within 500 mils of CK_TITAN R39 +V3.3S_CLKSRC FB21 1 2 300ohm@100MHz C435 0.1UF No stuff; caps are internal to CK-408. 0.
A B C D E 5,16,17,18,19,20,22,34 +V3.3S_ICH U46A 4 3 28 +V3.
A B C D E U46B +V3.3S_ICH 5,15,17,18,19,20,22,34 R228 R394 4 NO_STUFF_1K AC_SPKR NO_STUFF_10K AC_SDATAOUT R395 NO_STUFF_1K PCI_GNTA# 15,18 R396 NO_STUFF_1K LAN_EEP_DOUT 15 Board Default Optional Override No Reboot NO STUFF R197 Safe Mode Boot NO STUFF R198 A16 swap override NO STUFF R199 Reserved NO STUFF STUFF for No Reboot STUFF for safe mode STUFF for A16 swap override STUFF +V3.
A B C D 4,5,6,9,10,14,19,23,28,29,30,31,32,33,36,37,40 R258 1 U46C 10UF R189 0.1UF 0.1UF C575 0.1UF +V1.8_ICHLAN 2 1 NO_STUFF_0.01_1% 4 C624 4,9,19,20,24,31,32,33,35,36,37,40 +V5S C328 5,15,16,18,19,20,22,34 22UF 0.1UF 0.1UF +V3.3S_ICH 1 C595 C596 R179 1K 16,22 +V_RTC Q20 BAT54 VCC5REFSUS C315 0.1UF C617 0.1UF VCCSUS1.8_0 VCCSUS1.8_1 VCCSUS1.8_2 VCCSUS1.8_3 VCCSUS1.8_4 VCCSUS1.8_5 F15 F16 VCCSUS1.8_6 VCCSUS1.8_7 F7 F8 K10 VCCLAN1.8_0 VCCLAN1.8_1 VCCLAN1.8_2 AB6 VCCRTC +V3.
A B C +V12S_PCI 19 4 9,15,19,20,22 INT_PIRQB# INT_PIRQD# 15,19,20,22 SLT1_PRSNT1# C103 0.01UF C116 SLT1_PRSNT2# 0.
A B C 18,40 +V3.3S_PCI R93 0 -V12S 9,16,17,18,24,25,26,29,32,33,34,39,40 +V5PCISLT3 +V3.3ALWAYS R89 NO_STUFF_0 3 6 0 6 RP54C NO_STUFF_0 4 5 RP15D 0 4 5 RP54D NO_STUFF_0 18 +V5S_PCI R85 0 INT_PIRQD# RP15C PCI_SLT3INTB# 3 15,22 INT_PIRQF# 9,15,18,20,22 INT_PIRQB# 15,22,34 INT_PIRQH# 18,24,25,26,34,39,40 PCI_SLT3INTD# SLT3_PRSNT1# C436 C120 SLT3_PRSNT2# 0.01UF 0.
A B Qbuffers used for isolation during suspend as well as 5V->3.
B C D E 200 199 150 149 A 101 100 151 102 152 J35A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 5049 4 5251 2 1 20 DOCK_SMBDATA 20 DOCK_CLKRUN# 20 DOCK_REQB# 20 DOCK_PIRQC# 20 DOCK_PIRQB# 20 DOCK_GNT4# GND0 V_DC0 V_DC1 GND1 GND2 RED_RTN RED VSYNC HSYNC GND3 GND4 NC0 SM_DATA SYSACT# CLKRUN# PC_REQ# GND5 CD2 NC1 NC2 CD3#/GND INTD# INTC# GND6 GNT# J35C REQ# GND7 PERR# SERR# GND8 STOP# TRDY# GND9 LOCK# FRAME# GND10 C/BE1# C/BE0# GND11 AD29 AD28 GND12 AD25 AD24 GND13 AD21 AD
A B 4 15,18,19,20 15,18,19,20 15,18,19,20 15,18,19,20 PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_STOP# 15,18,19,20 15,18,19,20 15,18,19 15,18,19,20 PCI_SERR# PCI_DEVSEL# PCI_PERR# PCI_LOCK# 15 PCI_REQ0# 15,18 15,18 Pull-ups for PCI_GNT#0 15,19 and PCI_GNT#3 are by 15,20 PCI slots 15,23,34 3 PCI_REQ1# PCI_REQ2# PCI_REQ3# PCI_REQ4# 5,15,16,17,18,19,20,34 RP93A RP96B RP94D RP94C 1 2 4 3 8 7 5 6 8.2K 8.2K 8.2K 8.2K RP94B RP94A RP96C RP96D 2 1 3 4 7 8 6 5 8.2K 8.2K 8.2K 8.2K RP93D 4 5 8.
A B C 16 IDE_PDD[15:0] 4 4,5,6,9,10,14,17,19,28,29,30,31,32,33,36,37,40 +V3.3S R28947 IDE_D_PRST# 24 IDE_PRI_RST# D IDE_PDD[15:0] 3 RP100C 6 4.
A B C D E Primary IDE Power +V5S_IDE_P +V5S 4,9,17,19,20,31,32,33,35,36,37,40 4,9,17,19,20,31,32,33,35,36,37,40 +V5S 1 C366 2 3 4 74HC14 11 1 4 3 IDE_PPWR2 2 R232 NO_STUFF_0 SI4925DY SI4925DY SECONDARY IDE +V5S PWR ON DC-DC MODULE 14 4,9,17,19,20,31,32,33,35,36,37,40 4 U45A 74HC14 7 8 5 6 +V5S_IDE_P R245 U40F 13 +V5S_IDE_S R239 100K 10 4,9,17,19,20,31,32,33,35,36,37,40 +V5S C369 1000PF 34,40 IDE_PPWR_EN 7 0.
A 17,26,40 4 B C D E +V5ALWAYS +V5 18,19,24,26,34,39,40 R476 NO_STUFF_0 4 R477 0 +V5_USB1 +V3.3ALWAYS 9,16,17,18,19,24,26,29,32,33,34,39,40 1 0.1UF 2 C76 RP12A 10K 1K 1 2 3 4 GND IN EN1 EN2 OC1# OUT1 OUT2 OC2# 8 7 6 5 7 R80 1K USB_OC0# 16 U14 8 R81 RP12B 10K FER,EMI,1206,3A,25%,50OHM100MHZ 1 2 FB17 50OHM USBPWR_CONNC USBPWR_CONND FER,EMI,1206,3A,25%,50OHM100MHZ 1 2 FB16 50OHM USBD_VCC + C28 + C37 0.1UF 100uF C43 100uF USB_OC1# 16 C27 TPS2052 60OHM@100MHZ FB12D 4 5 3 0.
A +V5ALWAYS B C D E 17,25,40 +V5 18,19,24,25,34,39,40 R475 0 RP12C 10K 6 4 RP97A 10K 4 USB_OC2# 16 U2 +V5_USB2 C9 R8 R10 1 2 3 4 1K 1K 0.1UF GND IN EN1 EN2 OC1# OUT1 OUT2 OC2# 8 7 6 5 9,16,17,18,19,24,25,29,32,33,34,39,40 1 3 +V3.3ALWAYS 8 R474 NO_STUFF_0 USBPWR_CONNA USBPWR_CONNB 1 FB19 50OHM 2 USB_OC4# 16 0.
A B LAN_PHYCLK Enable Disable 4 J12 Shunt (Default) No Shunt C D +V3.3 14,17,19,21,24,29,34,36,40 NOTE: Disable LAN_PHYCLK when not using LAN Interface 2 4 +V3.3_LAN R2 1 Bulk caps should be 4.7uF or higher. NO_STUFF_0.01_1% C39 C42 4.7UF 0.1UF 0.1UF 0.1UF 0.1UF C40 C3 C4 4.7UH 2 +V3_L_LAN 1 1 1 C11 1 C8 0.1UF C12 Optional cap: C652 value 6pF - 12pF if needed for magnetics 4.
A B C D E 4 4 4,5,6,9,10,14,17,19,23,29,30,31,32,33,36,37,40 +V3.
A B 9,16,17,18,19,24,25,26,32,33,34,39,40 C D +V3.3ALWAYS 2 1 NO_STUFF_0.01_1% R14 2 J20 C6 22UF C424 C426 C428 C423 0.1UF 0.1UF 0.1UF 0.1UF P90-P92 needs to be at VCC for boot mode programming. They are already pulled up in the design. MD0, MD1 needs to be at Vss. Jumper for J22 needs to be populated. System needs to supply +V3ALWAYS to flash connector. 1 Measurement Point +V3.3ALWAYS_KBC 21,30 KSC Testpoint Header Program Y3 +V3.
A B C +V3.3ALWAYS_KBC Circuitry provides an interrupt to the SMC every 1s while in suspend (this allows the SMC to complete housekeeping functions while suspended) 4 D 14 14 U8B E 21,29 14 U8C 4 U8D R25 3 +V3.3ALWAYS_KBC 4 5 74HC04 1M 7 R13 0 21,29 6 9 8 7 SMC_INITCLK 24,29 74HC04 74HC04 1 21,29 7 C55 4.7uF NOTE: When flashing the KSC INSURE you short J8. Not doing so will permanently damage the KSC. R15 2 +V3.3ALWAYS_KBC R12 4.
A B C D E J49 +V5S PPT_PNF# 32 J49 1-2 (Default) 2-3 Q19 +V3.3S_SIO CON3_HDR +V3.
A B 7 9 11 13 15 17 19 21 23 25 27 29 31 33 RP102C RP102A 3 RP102B 1 1K 60OHM@100MHZ 3 6 FB6C 4 5 FB6D 1 8 FB11A 2 7 FB11B 31 PPT_PE 31 PPT_BUSY/WAIT# 31 PPT_ACK# 31 PPT_PD7 1K E 60OHM@100MHZ 1 8 FB6A 2 7 FB6B 31 PPT_PNF# 31 PPT_SLCT 6 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 1K D +V5S 8 1 3 8 J72 4 1K 6 1K RP104C 2 FLOPPY CONNECTOR 7 1 RP104A 3 4,9,17,19,20,24,31,33,35,36,37,40 C PARALLEL PORT PPT_L_PNF# PPT_L_SLCT J4 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4
A B C D E +V5S 4,9,17,19,20,24,31,32,35,36,37,40 KBC_SCANOUT[15:0] 29 CBTD has integrated diode for 5V to 3.
A B 9,19,22,35,40 +V12S C D E LPC POWERED ON SUSPEND RAIL FOR ADD-IN H8 CARD +V3.3_LPCSLOT J57 5,15,16,17,18,19,20,22 +V3.3_LPCSLOT +V3.3S_ICH 16,29,33 9,15,18,19,22 15,22 16,21,22,32 3 +V12S 1 9,19,22,35,40 2 LPC Debug Slot J55 9,16,17,18,19,24,25,26,29,32,33,39,40 +V3.
A B C 4 D E 4 Fan Power Control 6 5 2 1 4 R83 C84 22UF Q9 3 1000PF C73 0.1UF U15 SI3457DV C97 1 2 100K 3 CON2_HDR J24 1N4148 1 R79 1M +V5_FAN + 3 4,9,17,19,20,24,31,32,33,36,37,40 +V5S Q8 BSS138 3 FAN_ON 1 2 29,34 3 9,19,22,34,40 +V12S J14 C44 0.1UF 4,9,17,19,20,24,31,32,33,36,37,40 +V5S 3 2 1 CON3_HDR Desktop Fan Header 2 C47 0.
B C D +V3.3S 14,17,19,21,24,27,29,34,40 +V3.3 INTERPOSER_PRES# 3 7 74HC00 INTERPOSER_PRES# 8 9 74HC00 7 OFF_BOARD_VR_PWRGD 4 29,34 U11D 12 11 VR_ON 1 VIN ON_BOARD_VCCVID_ON 8 EN 13 4,5,6,9,10,14,17,19,23,28,29,30,31,32,33,37,40 +V3.3S 6 7 74HC00 4,5,6,9,10,14,17,19,23,28,29,30,31,32,33,37,40 6 74HC08 C53 10UF 7 R291 10K 14,17,19,21,24,27,29,34,40 +V3.3 14 U50D 13 11 12 10K R285 VR_PWRGD_CK408# 14 3 1 +VCC_VID U13 5 +V3.
5 4 +VDC 3 2 Decoupling 36,37,40 Bulk decoupling values are tuned to Intels IMVP II 5Phase VR design. Circuits using other converter topologies may have different requirements.
5 4 +V5 3 2 1 18,19,24,25,26,34,40 U43 C388 150uF C380 150uF C372 150uF C367 0.1UF VIN0 VIN1 VIN2 VIN3 VIN4 VSENSE C362 47pF NC/Comp PG_EN PWRGD C361 1 R217 2 1 25.5k_1% BOOT 2 L13 1 Single point sense near load R172 2 10uH D C281 0.1UF FSEL PGND0 PGND1 SS/ENA PGND2 PGND3 VBAIS PGND4 Note for layout: This part has special pad on it's underside NO_STUFF_10K_1% 9,16,17,18,19,24,25,26,29,32,33,34,40 +V3.3ALWAYS R163 R162 100_1% 100_1% C628 R206 0.
4 3 HDM Connector Assembly (base board) -V12S +V5S 4,9,17,19,20,24,31,32,33,35,36,37 4,9,17,19,20,24,31,32,33,35,36,37 DS6 GREEN +V1.8S 3 1 7,8,17 R164 147_1% 9,16,17,18,19,24,25,26,29,32,33,34,39 +V3.3ALWAYS R110 2 1 NO_STUFF_0.01_1% C200 22UF GREEN R105 9,16,17,18,19,24,25,26,29,32,33,34,399,16,17,18,19,24,25,26,29,32,33,34,39 9,16,17,18,19,24,25,26,29,32,33,34,39 9,16,17,18,19,24,25,26,29,32,33,34,39 +V3.3ALWAYS +V3.3ALWAYS +V3.3ALWAYS +V3.3ALWAYS +UNUSEDV2.
A B 1 PS_ON_SW# ATX PS Turner ATX C SW5 D Power On Sequence PG 40 PWR_PWROK U5A PG 36 3 4 PM_PWROK ICH3 4 4 PG 21 PG 16 PM_THRM# PM_SLP_S3# PG 5 PM_LANPWROK PM_BATLOW# PM_PWRBTN# H_PWRGD PM_RSMRST# ADM1023 VR_PWRGD MASTER_RESET# SMC_SHUTDOWN 3 DOCKING U5B PG 15 7 2 U7C PG 21 PCI_ICH_RST# PM_SLP_S5# PG 40 E LPC PG 34 3 Q2 PG 27 SMC_ONOFF# SMC SMC_RST# U7D MAX809 PG 30 PG 27 Fan Power PG 35 FAN_ON PG 29 SMC_RES# PG 29 SMC_PROG_RST# PCI_RST_SLOTS# 2 LAN Core
A B PS_ON_SW# C SW5 4 SMC_SHUTDOWN PCI_RST_SLOTS# PCI_ICH_RST# U5A MASTER_RESET# PG18 PG 36 PG 16 PM_RSMRST# Core VR PG 36 Q10 DOCKING PG 21 ITP PG 5 U8 PG 30 PG 30 PG29 R=0 PCI_RST_ONBD1# R=0 LPC SLOT PG 34 3 AGP SLOT PG 9 U23 EPROM PG 30 SMC SMC_RST# U7D PG 29 PCI_GATED_RST# U22 QSW PG 20 PCI_RST_ONBD2# 3 MAX809 4 ICH3-M PM_PWROK PG 40 2 PCI SLOTS PWR_PWROK PG 40 SW6 E Reset Map PG 40 DC/DC Turner D 2 SMC_RES# FWH PG 28 PG 29 SMC_PROG_RST# H_CPURST# MCH-M H_
