R Voltage Regulator-Down (VRD) 10.
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R Contents 1 Introduction ......................................................................................................................... 9 1.1 1.2 2 Processor Vcc Requirements ........................................................................................... 13 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 3 Applications ............................................................................................................ 9 Terminology....................................................
R 8.1 8.2 9 (PROPOSED) ................................................. 51 (PROPOSED) ................................................. 51 Output Indicators............................................................................................................... 53 9.1 9.2 9.3 9.4 9.5 10 Over-Voltage Protection (OVP) Over-Current Protection (OCP) VCC_PWRGD: Vcc Power Good Output (PROPOSED) ..................................... 53 VTTPWRGD: Vtt Power Good Output (REQUIRED)........................
R Figures Figure 2-1. Socket Load Line Window for Design Configuration 775_VR_CONFIG_04A15 Figure 2-2. Socket Load Line Window for Design Configuration 775_VR_CONFIG_04B16 Figure 2-3. VRD Phase Orientation .................................................................................. 19 Figure 2-4. Examples of High Volume Manufacturing Load Line Violations .................... 21 Figure 2-5. High Volume Manufacturing Compliant Load Line......................................... 21 Figure 2-6.
R Tables Table 1-1. Feature Support Terminology............................................................................ 9 Table 1-2. Glossary........................................................................................................... 10 Table 2-1. Socket Load Line Equations............................................................................ 13 Table 2-2. Vcc Regulator Design Parameters .................................................................. 14 Table 2-3.
R Revision History Revision Number Description Revision Date -001 Initial Release. June 2004 -002 • Updated Table 3-1 July 2004 • Added Note 5 Under Figure 4-2 • Added Note 1 Under Table 4-1 • Added Section 10.5 Resonance Suppression -003 • Updated Table 4-1Td4 information July 2004 -004 • Updated Table 2-2 April 2005 • Added Figure 2-3 • Added Table 2-5 • Updated Table 2-6 • Updated Table 2-11 • Changed 2.8.
R 8 Design Guide
Introduction R 1 Introduction 1.1 Applications This document defines the power delivery feature set necessary to support Intel processors’ Vcc power delivery requirements for desktop computer systems using the LGA775 socket. This includes design recommendations for DC to DC regulators, which convert the input supply voltage to a processor consumable Vcc voltage along with specific feature set implementation such as thermal monitoring and dynamic voltage identification.
Introduction R Table 1-2. Glossary Term 10 Description D-VID Dynamic Voltage Identification. A low power mode of operation where the processor instructs the VRD to operate at a lower voltage. DAC Digital to Analog Converter. DCR Direct Current Resistance. ESL Effective series inductance. ESR Effective series resistance. FET Field Effect Transistor. FR4 A type of printed circuit board (PCB) material. HVM High volume manufacturing. Icc Processor current.
Introduction R Term Description Socket Load Line Defines the characteristic impedance of the motherboard power delivery circuit to the node of regulation. Not the same as the processor load line that is published in the processor datasheet, which is defined across the processor Vccsense and Vsssense lands. In conjunction with high frequency decoupling, bulk decoupling, and robust power plane routing, design compliance to this parameter ensures that the processor voltage specifications are satisfied.
Introduction R 12 Design Guide
Processor Vcc Requirements R 2 Processor Vcc Requirements 2.1 Voltage and Current (REQUIRED) A six-bit VID code supplied by the processor to the VRD determines a reference output voltage as described in Section 6.2. The socket load lines in Section 2.2 show the relationship between Vcc and Icc for the processor at the motherboard-socket interface. Intel performs exhaustive testing against multiple software applications and software test vectors to identify valid processor Vcc operating ranges.
Processor Vcc Requirements R Table 2-2. Vcc Regulator Design Parameters VR Configuration Iccmax VR TDC Dynamic Icc RLL TOB Maximum VID 775_VR_CONFIG_04A 78 A 68 A 55 A 1.40 mΩ ±25 mV 1.4 V 775_VR_CONFIG_04B 119 A 101 A 95 A 1.00 mΩ ±19 mV 1.4 V 775_VR_CONFIG_05A 100A 85A 65A 1.00mΩ +/-19mV 1.4V 775_VR_CONFIG_05B 125A 115A 95A 1.00mΩ +/-19mV 1.
Processor Vcc Requirements R Figure 2-1. Socket Load Line Window for Design Configuration 775_VR_CONFIG_04A 0A 10 A 20 A 30 A 40 A 50 A 60 A 70 A 80 A 0.00 V -0.02 V -0.04 V -0.06 V -0.08 V -0.10 V -0.12 V -0.14 V -0.16 V -0.18 V Vmax Load Line NOTES: 1. 2. 3. Vtyp Load Line Vmin Load Line Presented as a deviation from VID. Socket load line Slope = 1.4 mΩ, TOB = ±25 mV Consult Table 2-1 for maximum current values Table 2-3.
Processor Vcc Requirements R Figure 2-2. Socket Load Line Window for Design Configuration 775_VR_CONFIG_04B 0A 20 A 40 A 60 A 80 A 100 A 120 A 0.00 V -0.02 V -0.04 V -0.06 V -0.08 V -0.10 V -0.12 V -0.14 V -0.16 V Vmax Load Line NOTES: 1. 2. 3. Vtyp Load Line Vmin Load Line Presented as a deviation from VID. Socket load line Slope = 1.0 mΩ, TOB = ±19 mV Consult Table 2-1 for maximum current values Table 2-4. Socket Load Line Window for Design Configuration 775_VR_CONFIG_04B NOTES: 1. 2. 3.
Processor Vcc Requirements R Reference nodes for socket load line measurements and voltage regulation are located in the land field between the socket cavity and the voltage regulator region with the highest phase count (see Figure 2-3); references for north and east phase configurations are identified in Table 2-5. It is recommended to place motherboard test points at these locations to enable load line calibration.
Processor Vcc Requirements R Table 2-5: Socket Load Line WindowSocket Load Line Window for Design Configurations 775_VR_CONFIG_05A and 775_VR_CONFIG_05B Icc Maximum Typical Minimum 0A 0.000 V -0.019 V -0.038 V 20 A -0.020 V -0.039 V -0.058 V 40 A -0.040 V -0.059 V -0.078 V 60 A -0.060 V -0.079 V -0.098 V 80 A -0.080 V -0.099 V -0.118 V 100 A -0.100 V -0.119 V -0.138 V 120 A -0.120 V -0.139 V -0.158 V 125 A -0.125 V -0.144 V -0.
Processor Vcc Requirements R Figure 2-3.
Processor Vcc Requirements R To properly calibrate the socket load line parameter, the VR designer must excite the processor socket with a current step that generates a voltage droop which must be checked against the load line window requirements. Table 2-8 identifies the steady state and transient current values to use for this calibration. For additional information, please consult the Socket Load Line Calculator for the appropriate Intel processor.
Processor Vcc Requirements R Figure 2-4.
Processor Vcc Requirements R 2.3 TOB: Voltage Tolerance Band (REQUIRED) Processor load line specifications must be guaranteed across component process variation, system temperature extremes, and age degradation limits. The VRD topology and component selection must maintain a 3-σ tolerance of the VRD Tolerance Band around the typical load line (see Section 2.2).
Processor Vcc Requirements R Table 2-7.
Processor Vcc Requirements R 2.3.2 TOB: Tolerance Band Calculation Reference TOB equations for each major current sense topology are provided in the next three subsections. Equations are presented in a manner for simple entry into a spreadsheet to simplify TOB calculation and design iterations. 2.3.3 Inductor RDC Current Sense TOB Calculations Inductor sensing is the best general approach to satisfying the tolerance band requirements.
Processor Vcc Requirements R 2.3.5 FET RDS-ON Current Sense TOB Calculations 2 2 2 TOBmanuf = (VID.kVID ) 2 + VAVP .(k gm + k RDS ) VAVP = I max .RAVP + / − TOB = TOBmanuf + Vripple + VTC Current can be determined by sensing the voltage across the VRD switching FET’s drain to source ‘on’ resistance. While this provides a direct method of voltage to current conversion, the standard FET RDS-ON tolerance of 20% – 30% is not acceptable to satisfy Intel’s tolerance band requirements.
Processor Vcc Requirements R 2.5 Stability (EXPECTED) The VRD must be unconditionally stable under all DC and transient conditions across the voltage and current ranges defined in Table 2-2 through Table 2-4 and Figure 2-1 and Figure 2-2. The VRD must also operate in a no-load condition: i.e., with no processor installed. Normally the noprocessor VID code will be 11111, disabling the VRD (see Table 9-1). 2.6 Dynamic Voltage Identification (REQUIRED) 2.6.
Processor Vcc Requirements R condition does not occur. In addition, reverse current into the AC-DC regulator must not impair the operation of the VRD, the AC-DC supply, or any other part of the system. Under all functional conditions, including D-VID, the Vcc supply must satisfy load line and overshoot constraints to avoid data corruption, system lock-up events, or system blue-screen failures. Figure 2-6.
Processor Vcc Requirements R Vcc slew rate between VRD no load (5 A) and full load (VR TDC) conditions. For this reason, the Vcc slewing must be tested under both loading conditions. During the D-VID test defined in the previous paragraph, Vcc droop and undershoot amplitudes must be limited to avoid processor damage and performance failures.
Processor Vcc Requirements R d. D-VID transition must be validated against above constraints from a starting VID of 0.8375 V to an ending VID of 1.6 V with an applied VR TDC Load. Figure 2-7. D-VID Transition Timing States Transition From Min To Max VID Transition From Max To Min VID 1.6V 1.6V 50µs 762.5mV 300µs Vcc Vcc 0.8375V 762.5mV Vcc Voltage Response 0.
Processor Vcc Requirements R Table 2-8. D-VID Validation Summary Table Parameter Minimum Typical Maximum VID 0.8375 V - 1.6000 V Voltage Transition 0.7575 V 0.762 5V 0.7675 V - - 350 µs 5A - VR TDC Transition Time Current Load NOTES: 1. 1 Time is measured from 0.4 V on rising edge of the first D-VID code to the convergent Vcc voltage value after the final D-VID code is transmitted 2.7 Processor Vcc Overshoot 2.7.
Processor Vcc Requirements R Maximum overshoot is validated by monitoring the voltage across the recommended test lands (defined in Section 2.2) while applying a current load release across the socket Vcc and Vss land field. Amperage values for performing this validation under each VRD design configuration are identified in Table 2-11.
Processor Vcc Requirements R Figure 2-9. Graphical Representation of Overshoot Parameters Figure 2-10.
Processor Vcc Requirements R Figure 2-11. Example Socket Vcc Overshoot Waveform 2.7.2 Example: Socket Vcc Overshoot Test To pass the overshoot specification, the amplitude constraint of Equation 2-4 and time duration requirement of TOS_MAX must be satisfied. This example references Figure 2-11. Amplitude Test Constraint: Overshoot amplitude, VOS, must be less than Vzc + VOS_MAX Input parameters VOS= 1.325 V – Obtained from direct measurement VZC = 1.285 V – Obtained from direct measurement VOS_Max = 0.
Processor Vcc Requirements R Overshoot Duration Analysis TOS = Final Crossing of Vzc – Initial Crossing of Vzc TOS = 35 µs – 15 µs = 20 µs < 25 µs = TOS_MAX Time duration test passed Amplitude and Time Duration Tests Passed => Overshoot specification is satisfied 2.
Processor Vcc Requirements R 2.8.2 High Frequency Decoupling The output filter includes high frequency decoupling to ensure ripple and package noise is suppressed to specified levels. Ripple limits are defined in section 2.3 and package noise limits are defined in appropriate processor datasheets in the form of a processor die load line. High frequency noise and ripple suppression are best minimized by 10 µF, 22 µF or 47 µF multilayer ceramic capacitors (MLCC’s).
Processor Vcc Requirements R 36 Design Guide
Vtt Requirements (REQUIRED) R 3 Vtt Requirements (REQUIRED) The Vtt regulator provides power to the processor VID, the chipset - processor front side bus, and miscellaneous buffer signals. This rail must settle to the voltage defined in Table 3-1 and assert an active-high VIDPWRGD output when in regulation (see section 9.2). The Vtt regulator controller does not include an enable signal; valid output voltage of Table 3-1 must be guaranteed by the timing protocol defined in Figure 4-1. 3.
Vtt Requirements (REQUIRED) R 4. 38 TDC is the thermal design current with the maximum number of signals in a low, current consuming state. It includes processor and chipset i/o buffer draw.
Vtt Requirements (REQUIRED) R Table 3-2. Vtt Measurement Lands Device 3.2 Supply Land Processor Vtt D25 Processor Vss D26 865 MCH Vtt F29 865 MCH Vss E29 910 MCH Vtt F29 910 MCH Vss E29 Processor-MCH Vtt Mismatch The Intel® Pentium® 4 processor Extreme Edition supporting Hyper-Threading Technology on 0.13 micron process requires the LGA775 Vtt regulator to sink and source current.
Vtt Requirements (REQUIRED) R 40 Design Guide
Power Sequencing (REQUIRED) R 4 Power Sequencing (REQUIRED) The VRD must correctly sequence power in accordance with Intel processor requirements. Figure 4-1 is a block diagram of the VRD connectivity with necessary signals and relevant power rails. Figure 4-2.provides the timing protocol for these signals and power rails in LGA775 platforms. Figure 4-1. Power-on Sequencing Block Diagram Vcc_PWRGD VID[5:0] Vcc VR Vcc Processor Output Enable VTTPWRGD Vtt VR Vtt Figure 4-2.
Power Sequencing (REQUIRED) R Table 4-1. Power Sequence Timing Parameters NOTES: 1. Parameter Minimum Typical Maximum TD1 1 ms - 50 ms TD3 0 ms - - TD4 0 ms - 500 ms TOFF - - 500 ms 1 . Applicable to all designs When the VRD has been enabled and is delivering current to the processor, it should shut down power within 500 ms of receiving either a de-asserted Output Enable or an ‘OFF’ VID code (111111 or 011111).
VRD Current Support (EXPECTED) R 5 VRD Current Support (EXPECTED) System boards supporting LGA775 socket processors must have voltage regulator designs compliant to electrical and thermal standards defined in Table 2-2. This includes full electrical support of Iccmax specifications and robust cooling solutions to support defined thermal design current (VR TDC) indefinitely within the envelope of system operating conditions.
VRD Current Support (EXPECTED) R 44 Design Guide
Control Inputs R 6 Control Inputs 6.1 Vcc Output Enable (REQUIRED) The VRD must include an input signal to enable the Vcc output. When disabled, the VRD output should be in a high-impedance state and should not source current. Once the VRD is operating after power-up, it should respond to a de-asserted output enable by turning off Vcc power within 500 ms. Consult Section 4 for Vcc power sequence information.
Control Inputs R Some designs may require additional VID bus loads. In this case, care should be taken to design the topology to avoid excessive undershoot and overshoot at each load. Failure to comply with these limits may lead to component damage or cause premature failure. The responsible engineer must identify minimum and maximum limits of each component and design a topology that ensures voltages stay within these limits at all times. Figure 6-1.
Control Inputs R Table 6-3. VRD10 Voltage Identification (VID) Table Processor Lands (0 = low, 1 = high) Processor Lands (0 = low, 1 = high) Vout (V) VID5 VID4 VID3 VID2 VID1 VID0 Vout(V) VID5 VID4 VID3 VID2 VID1 VID0 0 0 1 0 1 0 0.8375 0 1 1 0 1 0 1.2125 1 0 1 0 0 1 0.8500 1 1 1 0 0 1 1.2250 0 0 1 0 0 1 0.8625 0 1 1 0 0 1 1.2375 1 0 1 0 0 0 0.8750 1 1 1 0 0 0 1.2500 0 0 1 0 0 0 0.8875 0 1 1 0 0 0 1.2625 1 0 0 1 1 1 0.
Control Inputs R 6.2 Differential Remote Sense Input (REQUIRED) The PWM controller should include differential sense inputs to compensate for an output voltage offset of ≤ 300 mV in the power distribution path. The remote sense lines should draw no more than 10 mA, to minimize offset errors. Refer to Section 2.2 for the measurement location.
Input Voltage and Current R 7 Input Voltage and Current 7.1 Input Voltages (EXPECTED) VRD output voltage is supplied via DC-to-DC power conversion. To ensure proper operation, the input supplies to these regulators must satisfy the following conditions. 7.1.1 Desktop Input Voltages The main power source for the Vcc VRD is 12 V ±15% and 3.3 V for the Vtt supply. These voltages are supplied by an AC-DC power supply through a cable to the motherboard.
Input Voltage and Current R 50 Design Guide
Output Protection R 8 Output Protection These are features built into the VRD to prevent damage to itself, the processor, and other system components. 8.1 Over-Voltage Protection (OVP) (PROPOSED) An OVP circuit should monitor the output for an over-voltage condition. If the output is more than 200 mV above the maximum VID level, the VRD should shut off the Vcc supply to the processor. 8.
Output Protection R 52 Design Guide
Output Indicators R 9 Output Indicators 9.1 VCC_PWRGD: Vcc Power Good Output (PROPOSED) The Vcc VRD is to provide a power-good signal, which satisfies timing requirements defined in section 4. The signal must remain asserted when the VRD is operating, except for fault or shutdown conditions. Vcc_PWRGD must not be de-asserted during the D-VID operation. Table 9-1. Power Good Specifications Design Parameter Specification Signal Type Open-collector or equivalent Voltage Range 5.
Output Indicators R 9.3 Example VTTPWRGD Circuit Figure 9-1. VTTPWRGD Circuit The circuit in Figure 9-1 satisfies the power sequence and rise time requirements of the VTTPWRGD signal as defined in Section 4 and 9.2.1. The circuit consists of two functional blocks. The first circuit block is centered around transistors A and B, which detect the Vtt threshold and triggers the VTTPWRGD signal. The second block consists of transistors D and C, which establish the necessary rise time and signal polarity.
Output Indicators R recommended part number is MBT3904Dual, which is provided by several vendors. Transistors C and D are also contained in a single, 6-pin SOT363 package; recommended part numbers are PUMZ1 (Philips Semiconductor*), MBT3964DW1(ON Semiconductor*) or equivalent. 9.4 PROCHOT# and VRD Thermal Monitoring (EXPECTED) This section describes how to protect the voltage regulator design from heat damage while supporting thermal design current (VR TDC).
Output Indicators R positive comparator terminal). As the thermistor temperature increases due to system loading, the resistance will decrease. When the voltage drop across the thermistor falls below the trigger reference voltage, established by R1 and R2, the comparator will change state and bias the bipolar transistors. When biased, Q1 and Q2 provide the active low assertion of PROCHOT# and FORCEPR# compliant to Table 7 signaling specifications.
Output Indicators R Figure 9-3. Processor Load Schematic for PROCHOT# AND FORCEPR# termination (Single Load) Table 9-3. Thermal Monitor Specifications Parameter Minimum Typical 1 Maximum Vtt - Vtt Vcc(5) 4.75 V 5.00 V 5.25 V Q1 ‘on’ resistance - - 11 Ω PROCHOT# leakage current - - 200 µA PROCHOT# transition time 1.10 ns 100 ns - FORCEPR# leakage current FORCEPR# transition time - 200 µA 1.10 ns 100 ns PROCHOT# VOL (Maximum low voltage threshold) 0.
Output Indicators R NOTES: 1. 2. 9.5 Consult Table 3-1 for Vtt specifications. Bias for Q1and Q2 in the thermal monitor circuit is provided by the processor and chipset. Additional termination must not be integrated into the thermal monitoring circuit. Load Indicator Output (EXPECTED) To assist VRD circuit debug and validation, the PWM controller supplier may choose to include an output voltage that is a defined function of the VRD output current.
Motherboard Power Plane Layout R 10 Motherboard Power Plane Layout The motherboard layer stack-up must be designed to ensure robust, noise-free power delivery to the processor. Failure to minimize and balance power plane resistance may result in noncompliance to the die load line specification. A poorly planned stack-up or excessive holes in the power planes may increase system inductance and generate oscillation on the rail at the processor.
Motherboard Power Plane Layout R Figure 10-1. Reference Board Layer Stack-up L1 Soldermask Layer L1: Plated ½ oz. Copper L1-2 FR4 Layer Layer L2: L2: Unplated Unplated 1 1 oz. oz. Copper Copper CORE Layer L3: Unplated 1 oz. Copper L3-4 FR4 Layer L4: Plated ½ oz. Copper L4 Soldermask Table 10-1. Reference Board Layer Thickness Layer Minimum Typical Maximum L1 Soldermask 0.15 mils 0.65 mils 1.16 mils L1 1.08 mils 1.90 mils 2.72 mils L1-2 FR4 3.90 mils 4.40 mils 4.80 mils L2 1.00 mils 1.
Motherboard Power Plane Layout R Figure 10-2. Layer 1 Vcc Shape for Intel’s Reference Four-Layer Motherboard Figure 10-3.
Motherboard Power Plane Layout R Figure 10-4. Layer 3 Vss Routing for Intel’s Reference Four-Layer Motherboard Figure 10-5.
Motherboard Power Plane Layout R 10.4 Six-Layer Boards (EXPECTED) Six layer boards provide layout engineers with greater design flexibility compared to the FourLayer standard. Adjacent plane pairs of the same potential are not useful at higher frequencies, so the best approach is to maximize adjacent, closely spaced Vcc/Vss plane pairs.
Motherboard Power Plane Layout R 64 Design Guide
Electrical Simulation R 11 Electrical Simulation The following electrical models are enclosed to assist with VRD design analysis and component evaluation for load line compliance. The block diagram shown in Figure 11-1 is a simplified representation of the Vcc power delivery network of the Intel four-layer reference board interfaced with the LGA775 socket. The board model, detailed in Figure 11-4, characterizes the power plane layout of Figure 10-2 to Figure 10-5.
Electrical Simulation R The motherboard model of Figure 11-4 represents the power delivery path of Intel’s reference four-layer motherboard design. Input and output node locations are identified in Figure 11-5. Feedback to the PWM controller error amplifier should be tied to node ‘N2’, the socketmotherboard interface. Node ‘N1’ is the location where the ‘north’ phase inductors of the buck regulator ties to the ‘north’ motherboard power plane.
Electrical Simulation R Figure 11-2. Example Voltage Droop Observed at Node ‘N2’ Figure 11-2 provides an example voltage droop waveform at node ‘N2’, the socket-motherboard interface. The load line value is defined as ∆V/∆I with ∆V measured at this node and the current step observed through I_PWL (see Figure 11-7). The voltage amplitude is defined as the difference in the steady state voltage (prior to the transient) and the minimum voltage droop (consult Figure 11-2).
Electrical Simulation R Figure 11-3.
Electrical Simulation R Figure 11-4. Schematic Diagram for the Four-Layer Intel Reference Motherboard NOTE: Consult Figure 10-2 to Figure 10-5 for reference layout. Table 11-1. Parameter Values for the Schematic of Figure 11-4 Design Guide Parameter Value Comments RMB1 0.93 mΩ ‘North’ power plane parasitic resistance from the buck regulator output inductor to the LGA775 socket connection. RMB2 0.
Electrical Simulation R Figure 11-5.
Electrical Simulation R Figure 11-6. Schematic Representation of Bulk and High-Frequency Decoupling Capacitors NOTES: 1. 2. 3. C1 represents the parallel model for ‘north’ location bulk decoupling C2 represents the parallel model for high frequency decoupling located in the socket cavity C3 represents the parallel model for ‘east’ location bulk decoupling Table 11-2. Recommended Parameter Values for the Capacitors Models in Figure 11-6 Parameter Value Comments CMB1 3360 µF RMB1 1.
Electrical Simulation R Figure 11-7. Schematic Representation of the LGA775 Socket Table 11-3. Electrical Parameters for the Schematic of Figure 11-7 72 Parameter Value Comments RSKT1 0.38 mΩ LGA775 ‘north’ segment resistance RSKT2 1.13 mΩ LGA775 ‘center’ segment resistance RSKT3 0.29 mΩ LGA775 ‘east’ segment resistance RVTT1 0.42 mΩ Resistance of VTT Tool load board RVTT2 0.
Electrical Simulation R Figure 11-8. Current Load Step Profile for I_PWL from the Schematic of Figure 11-7 Current (A) Imax Imin t0 t1 t2 Time Table 11-4. I_PWL Current Parameters for Figure 11-7 and Figure 11-8 Parameter Value Comments t0 0s t1 250 µs t2 t1 + 1.25 µs Istep 95 A Current step for load line testing Imin 24 A Minimum current for simulation analysis Imax 119 A Maximum current for simulation analysis Simulation ‘time zero’ Time to initiate the current step.
Electrical Simulation R 74 Design Guide
Appendix: LGA775 Version 1 Pinmap R 12 Appendix: LGA775 Version 1 Pinmap Land Name A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A20M# A21# A22# A23# A24# A25# A26# A27# A28# A29# A3# A30# A31# A32# A33# A34# A35# A4# A5# A6# A7# A8# A9# ADS# ADSTB0# ADSTB1# Design Guide Land # U6 T4 U5 U4 V5 V4 W5 AB6 W6 Y6 Y4 K3 AA4 AD6 AA5 AB5 AC5 AB4 AF5 AF4 AG6 L5 AG4 AG5 AH4 AH5 AJ5 AJ6 P6 M5 L4 M4 R4 T5 D2 R6 AD5 Signal Buffer Type Source Synch Source Synch Source Synch Source Synch Source Synch Source
Appendix: LGA775 Version 1 Pinmap R Land Name AP0# AP1# BCLK0 BCLK1 BINIT# BNR# BOOTSELECT BPM0# BPM1# BPM2# BPM3# BPM4# BPM5# BPRI# BR0# BSEL0 BSEL1 BSEL2 COMP0 COMP1 COMP2 COMP3 D0# D1# D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D2# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D3# 76 Land # U2 U3 F28 G28 AD3 C2 Y1 AJ2 AJ1 AD2 AG2 AF2 AG3 G8 F3 G29 H30 G30 A13 T1 G2 R1 B4 C5 B10 C11 D8 B12 C12 D11 G9 F8 F9 E9 A4 D7 E10 D10 F11 F12 D13 E13 G13 F14 G14 C6 Signal Buffer Type Common Clock Commo
Appendix: LGA775 Version 1 Pinmap R Land Name D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# D4# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D5# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D6# D60# D61# D62# D63# D7# D8# D9# DBI0# DBI1# DBI2# DBI3# DBR# DBSY# Design Guide Land # F15 G15 G16 E15 E16 G18 G17 F17 F18 E18 A5 E19 F20 E21 F21 G21 E22 D22 G22 D20 D17 B6 A14 C15 C14 B15 C18 B16 A17 B18 C21 B21 B7 B19 A19 A22 B22 A7 A10 A11 A8 G11 D19 C20 AC2 B2 Signal Buffer Type Source Synch Sou
Appendix: LGA775 Version 1 Pinmap R Land Name DEFER# DP0# DP1# DP2# DP3# DRDY# DSTBN0# DSTBN1# DSTBN2# DSTBN3# DSTBP0# DSTBP1# DSTBP2# DSTBP3# FC10 FC11 FC12 FC16 FC17 FC18 FC3 FC4 FC5 FC7 FERR#/PBE# FORCEPR# GTLREF_SEL GTLREF0 GTLREF1 HIT# HITM# IERR# IGNNE# IMPSEL INIT# ITP_CLK0 ITP_CLK1 LINT0 LINT1 LL_ID0 LL_ID1 LOCK# MCERR# MSID0 MSID1 PROCHOT# 78 Land # G7 J16 H15 H16 J17 C1 C8 G12 G20 A16 B9 E12 G19 C17 E24 AM5 AM7 AN7 Y3 AE3 J2 T2 F2 G5 R3 AK6 H29 H1 H2 D4 E4 AB2 N2 F6 P3 AK3 AJ3 K1 L1 V2 AA2 C3 A
Appendix: LGA775 Version 1 Pinmap R Design Guide Land Name Land # PWRGOOD REQ0# REQ1# REQ2# REQ3# REQ4# RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESET# RS0# RS1# RS2# RSP# SKTOCC# SMI# STPCLK# TCK TDI TDO TESTHI0 TESTHI1 TESTHI10 TESTHI11 TESTHI12 TESTHI13 N1 K4 J5 M6 K6 J6 A20 AC4 AE4 AE6 AH2 C9 D1 D14 D16 E23 E5 E6 E7 F23 F29 G10 B13 J3 N4 N5 P5
Appendix: LGA775 Version 1 Pinmap R Land Name TESTHI2 TESTHI3 TESTHI4 TESTHI5 TESTHI6 TESTHI7 TESTHI8 TESTHI9 THERMDA THERMDC THERMTRIP# TMS TRDY# TRST# VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC 80 Land # F25 G25 G27 G26 G24 F24 G3 G4 AL1 AK1 M2 AC1 E3 AG1 AA8 AB8 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30 AC8 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD8 AE11 AE12 AE14 AE15 AE18 AE19 AE21 AE22 AE23 AE9 AF11 AF12 Signal Buf
Appendix: LGA775 Version 1 Pinmap R Land Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Design Guide Land # AF14 AF15 AF18 AF19 AF21 AF22 AF8 AF9 AG11 AG12 AG14 AG15 AG18 AG19 AG21 AG22 AG25 AG26 AG27 AG28 AG29 AG30 AG8 AG9 AH11 AH12 AH14 AH15 AH18 AH19 AH21 AH22 AH25 AH26 AH27 AH28 AH29 AH30 AH8 AH9 AJ11 AJ12 AJ14 AJ15 AJ18 AJ19 Signal Buffer Type Power/Other Pow
Appendix: LGA775 Version 1 Pinmap R Land Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC 82 Land # AJ21 AJ22 AJ25 AJ26 AJ8 AJ9 AK11 AK12 AK14 AK15 AK18 AK19 AK21 AK22 AK25 AK26 AK8 AK9 AL11 AL12 AL14 AL15 AL18 AL19 AL21 AL22 AL25 AL26 AL29 AL30 AL8 AL9 AM11 AM12 AM14 AM15 AM18 AM19 AM21 AM22 AM25 AM26 AM29 AM30 AM8 AM9 Signal Buffer Type Power/Other Power/Other Pow
Appendix: LGA775 Version 1 Pinmap R Land Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Design Guide Land # AN11 AN12 AN14 AN15 AN18 AN19 AN21 AN22 AN25 AN26 AN29 AN30 AN8 AN9 J10 J11 J12 J13 J14 J15 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J8 J9 K23 K24 K25 K26 K27 K28 K29 K30 K8 L8 M23 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other
Appendix: LGA775 Version 1 Pinmap R Land Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC 84 Land # M24 M25 M26 M27 M28 M29 M30 M8 N23 N24 N25 N26 N27 N28 N29 N30 N8 P8 R8 T23 T24 T25 T26 T27 T28 T29 T30 T8 U23 U24 U25 U26 U27 U28 U29 U30 U8 V8 W23 W24 W25 W26 W27 W28 W29 W30 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Appendix: LGA775 Version 1 Pinmap R Land Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC_MB_REGULATIO N VCC_SENSE VCCA VCCIOPLL VCCPLL VID0 VID1 VID2 VID3 VID4 VID5 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Design Guide Land # W8 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 Y8 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other AN5 AN3 A23 C23 D23 AM2 AL5 AM3 AL6 AK4 AL4 A12
Appendix: LGA775 Version 1 Pinmap R Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 86 Land # AB27 AB28 AB29 AB30 AB7 AC3 AC6 AC7 AD4 AD7 AE10 AE13 AE16 AE17 AE2 AE20 AE24 AE25 AE26 AE27 AE28 AE29 AE30 AE5 AE7 AF10 AF13 AF16 AF17 AF20 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF3 AF30 AF6 AF7 AG10 AG13 AG16 AG17 AG20 Signal Buffer Type Power/Other Power/Other Power/O
Appendix: LGA775 Version 1 Pinmap R Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Design Guide Land # AG23 AG24 AG7 AH1 AH10 AH13 AH16 AH17 AH20 AH23 AH24 AH3 AH6 AH7 AJ10 AJ13 AJ16 AJ17 AJ20 AJ23 AJ24 AJ27 AJ28 AJ29 AJ30 AJ4 AJ7 AK10 AK13 AK16 AK17 AK2 AK20 AK23 AK24 AK27 AK28 AK29 AK30 AK5 AK7 AL10 AL13 AL16 AL17 AL20 Signal Buffer Type Power/Other Power/O
Appendix: LGA775 Version 1 Pinmap R Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 88 Land # AL23 AL24 AL27 AL28 AL3 AL7 AM1 AM10 AM13 AM16 AM17 AM20 AM23 AM24 AM27 AM28 AM4 AN1 AN10 AN13 AN16 AN17 AN2 AN20 AN23 AN24 AN27 AN28 B1 B11 B14 B17 B20 B24 B5 B8 C10 C13 C16 C19 C22 C24 C4 C7 D12 D15 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other
Appendix: LGA775 Version 1 Pinmap R Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Design Guide Land # D18 D21 D24 D3 D5 D6 D9 E11 E14 E17 E2 E20 E25 E26 E27 E28 E29 E8 F10 F13 F16 F19 F22 F4 F7 G1 H10 H11 H12 H13 H14 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H3 H6 H7 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/O
Appendix: LGA775 Version 1 Pinmap R Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 90 Land # H8 H9 J4 J7 K2 K5 K7 L23 L24 L25 L26 L27 L28 L29 L3 L30 L6 L7 M1 M7 N3 N6 N7 P23 P24 P25 P26 P27 P28 P29 P30 P4 P7 R2 R23 R24 R25 R26 R27 R28 R29 R30 R5 R7 T3 T6 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Pow
Appendix: LGA775 Version 1 Pinmap R Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS_MB_REGULATION VSS_SENSE VSSA VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT Design Guide Land # T7 U1 U7 V23 V24 V25 V26 V27 V28 V29 V3 V30 V6 V7 W4 W7 Y2 Y5 Y7 AN6 AN4 B23 A25 A26 A27 A28 A29 A30 B25 B26 B27 B28 B29 B30 C25 C26 C27 C28 C29 C30 D25 D26 D27 D28 D29 D30 Signal Buffer Type Power/Other Power/Other Power/Other Power/Oth
Appendix: LGA775 Version 1 Pinmap R Land Name VTT_OUT_LEFT VTT_OUT_RIGHT VTT_SEL VTTPWRGD 92 Land # J1 AA1 F27 AM6 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Direction Output Output Output Input Design Guide
